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-rw-r--r--embassy-stm32/src/qspi/enums.rs16
-rw-r--r--embassy-stm32/src/qspi/mod.rs5
-rw-r--r--examples/stm32f7/src/bin/qspi.rs1
-rw-r--r--examples/stm32h742/src/bin/qspi.rs1
-rw-r--r--examples/stm32l432/src/bin/qspi_mmap.rs3
5 files changed, 24 insertions, 2 deletions
diff --git a/embassy-stm32/src/qspi/enums.rs b/embassy-stm32/src/qspi/enums.rs
index 9ec4c1b43..fa5e36d06 100644
--- a/embassy-stm32/src/qspi/enums.rs
+++ b/embassy-stm32/src/qspi/enums.rs
@@ -331,3 +331,19 @@ impl From<DummyCycles> for u8 {
331 } 331 }
332 } 332 }
333} 333}
334
335#[allow(missing_docs)]
336#[derive(Copy, Clone)]
337pub enum SampleShifting {
338 None,
339 HalfCycle,
340}
341
342impl From<SampleShifting> for bool {
343 fn from(value: SampleShifting) -> Self {
344 match value {
345 SampleShifting::None => false,
346 SampleShifting::HalfCycle => true,
347 }
348 }
349}
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 0df057c53..1e20d7cd3 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -58,6 +58,8 @@ pub struct Config {
58 pub fifo_threshold: FIFOThresholdLevel, 58 pub fifo_threshold: FIFOThresholdLevel,
59 /// Minimum number of cycles that chip select must be high between issued commands 59 /// Minimum number of cycles that chip select must be high between issued commands
60 pub cs_high_time: ChipSelectHighTime, 60 pub cs_high_time: ChipSelectHighTime,
61 /// Shift sampling point of input data (none, or half-cycle)
62 pub sample_shifting: SampleShifting,
61} 63}
62 64
63impl Default for Config { 65impl Default for Config {
@@ -68,6 +70,7 @@ impl Default for Config {
68 prescaler: 128, 70 prescaler: 128,
69 fifo_threshold: FIFOThresholdLevel::_17Bytes, 71 fifo_threshold: FIFOThresholdLevel::_17Bytes,
70 cs_high_time: ChipSelectHighTime::_5Cycle, 72 cs_high_time: ChipSelectHighTime::_5Cycle,
73 sample_shifting: SampleShifting::None,
71 } 74 }
72 } 75 }
73} 76}
@@ -120,7 +123,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
120 T::REGS.cr().modify(|w| { 123 T::REGS.cr().modify(|w| {
121 w.set_en(true); 124 w.set_en(true);
122 //w.set_tcen(false); 125 //w.set_tcen(false);
123 w.set_sshift(false); 126 w.set_sshift(config.sample_shifting.into());
124 w.set_fthres(config.fifo_threshold.into()); 127 w.set_fthres(config.fifo_threshold.into());
125 w.set_prescaler(config.prescaler); 128 w.set_prescaler(config.prescaler);
126 w.set_fsel(fsel.into()); 129 w.set_fsel(fsel.into());
diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs
index bd3287964..ab29ddeff 100644
--- a/examples/stm32f7/src/bin/qspi.rs
+++ b/examples/stm32f7/src/bin/qspi.rs
@@ -279,6 +279,7 @@ async fn main(_spawner: Spawner) -> ! {
279 prescaler: 16, 279 prescaler: 16,
280 cs_high_time: ChipSelectHighTime::_1Cycle, 280 cs_high_time: ChipSelectHighTime::_1Cycle,
281 fifo_threshold: FIFOThresholdLevel::_16Bytes, 281 fifo_threshold: FIFOThresholdLevel::_16Bytes,
282 sample_shifting: SampleShifting::None,
282 }; 283 };
283 let driver = Qspi::new_bank1( 284 let driver = Qspi::new_bank1(
284 p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config, 285 p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config,
diff --git a/examples/stm32h742/src/bin/qspi.rs b/examples/stm32h742/src/bin/qspi.rs
index aee07f3f2..50e37ec52 100644
--- a/examples/stm32h742/src/bin/qspi.rs
+++ b/examples/stm32h742/src/bin/qspi.rs
@@ -272,6 +272,7 @@ async fn main(_spawner: Spawner) -> ! {
272 prescaler: 16, 272 prescaler: 16,
273 cs_high_time: ChipSelectHighTime::_1Cycle, 273 cs_high_time: ChipSelectHighTime::_1Cycle,
274 fifo_threshold: FIFOThresholdLevel::_16Bytes, 274 fifo_threshold: FIFOThresholdLevel::_16Bytes,
275 sample_shifting: SampleShifting::None,
275 }; 276 };
276 let driver = Qspi::new_blocking_bank1(p.QUADSPI, p.PD11, p.PD12, p.PE2, p.PD13, p.PB2, p.PB10, config); 277 let driver = Qspi::new_blocking_bank1(p.QUADSPI, p.PD11, p.PD12, p.PE2, p.PD13, p.PB2, p.PB10, config);
277 let mut flash = FlashMemory::new(driver); 278 let mut flash = FlashMemory::new(driver);
diff --git a/examples/stm32l432/src/bin/qspi_mmap.rs b/examples/stm32l432/src/bin/qspi_mmap.rs
index 86a20eb3d..075458fe5 100644
--- a/examples/stm32l432/src/bin/qspi_mmap.rs
+++ b/examples/stm32l432/src/bin/qspi_mmap.rs
@@ -7,7 +7,7 @@
7use defmt::info; 7use defmt::info;
8use embassy_stm32::mode; 8use embassy_stm32::mode;
9use embassy_stm32::qspi::enums::{ 9use embassy_stm32::qspi::enums::{
10 AddressSize, ChipSelectHighTime, DummyCycles, FIFOThresholdLevel, MemorySize, QspiWidth, 10 AddressSize, ChipSelectHighTime, DummyCycles, FIFOThresholdLevel, MemorySize, QspiWidth, SampleShifting,
11}; 11};
12use embassy_stm32::qspi::{self, Instance, TransferConfig}; 12use embassy_stm32::qspi::{self, Instance, TransferConfig};
13pub struct FlashMemory<I: Instance> { 13pub struct FlashMemory<I: Instance> {
@@ -252,6 +252,7 @@ async fn main(_spawner: Spawner) {
252 prescaler: 200, 252 prescaler: 200,
253 cs_high_time: ChipSelectHighTime::_1Cycle, 253 cs_high_time: ChipSelectHighTime::_1Cycle,
254 fifo_threshold: FIFOThresholdLevel::_16Bytes, 254 fifo_threshold: FIFOThresholdLevel::_16Bytes,
255 sample_shifting: SampleShifting::None,
255 }; 256 };
256 let driver = qspi::Qspi::new_bank1(p.QUADSPI, p.PB1, p.PB0, p.PA7, p.PA6, p.PA3, p.PA2, p.DMA2_CH7, config); 257 let driver = qspi::Qspi::new_bank1(p.QUADSPI, p.PB1, p.PB0, p.PA7, p.PA6, p.PA3, p.PA2, p.DMA2_CH7, config);
257 let mut flash = FlashMemory::new(driver); 258 let mut flash = FlashMemory::new(driver);