diff options
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 15 | ||||
| -rw-r--r-- | embassy/src/interrupt.rs | 9 |
2 files changed, 5 insertions, 19 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index 024a86c91..63bbe5a77 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -187,13 +187,6 @@ impl<'d, T: Instance> Uarte<'d, T> { | |||
| 187 | s.endtx_waker.wake(); | 187 | s.endtx_waker.wake(); |
| 188 | r.intenclr.write(|w| w.endtx().clear()); | 188 | r.intenclr.write(|w| w.endtx().clear()); |
| 189 | } | 189 | } |
| 190 | |||
| 191 | if r.events_rxto.read().bits() != 0 { | ||
| 192 | r.intenclr.write(|w| w.rxto().clear()); | ||
| 193 | } | ||
| 194 | if r.events_txstopped.read().bits() != 0 { | ||
| 195 | r.intenclr.write(|w| w.txstopped().clear()); | ||
| 196 | } | ||
| 197 | } | 190 | } |
| 198 | } | 191 | } |
| 199 | 192 | ||
| @@ -208,15 +201,9 @@ impl<'a, T: Instance> Drop for Uarte<'a, T> { | |||
| 208 | info!("did_stoprx {} did_stoptx {}", did_stoprx, did_stoptx); | 201 | info!("did_stoprx {} did_stoptx {}", did_stoprx, did_stoptx); |
| 209 | 202 | ||
| 210 | // Wait for rxto or txstopped, if needed. | 203 | // Wait for rxto or txstopped, if needed. |
| 211 | r.intenset.write(|w| w.rxto().set().txstopped().set()); | ||
| 212 | while (did_stoprx && r.events_rxto.read().bits() == 0) | 204 | while (did_stoprx && r.events_rxto.read().bits() == 0) |
| 213 | || (did_stoptx && r.events_txstopped.read().bits() == 0) | 205 | || (did_stoptx && r.events_txstopped.read().bits() == 0) |
| 214 | { | 206 | {} |
| 215 | info!("uarte drop: wfe"); | ||
| 216 | cortex_m::asm::wfe(); | ||
| 217 | } | ||
| 218 | |||
| 219 | cortex_m::asm::sev(); | ||
| 220 | 207 | ||
| 221 | // Finally we can disable! | 208 | // Finally we can disable! |
| 222 | r.enable.write(|w| w.enable().disabled()); | 209 | r.enable.write(|w| w.enable().disabled()); |
diff --git a/embassy/src/interrupt.rs b/embassy/src/interrupt.rs index df3a79ccc..7848ee698 100644 --- a/embassy/src/interrupt.rs +++ b/embassy/src/interrupt.rs | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | use atomic_polyfill::{compiler_fence, AtomicPtr, Ordering}; | ||
| 2 | use core::mem; | ||
| 1 | use core::ptr; | 3 | use core::ptr; |
| 2 | use cortex_m::peripheral::NVIC; | 4 | use cortex_m::peripheral::NVIC; |
| 3 | 5 | ||
| 4 | use atomic_polyfill::{compiler_fence, AtomicPtr, Ordering}; | ||
| 5 | |||
| 6 | pub use embassy_macros::interrupt_declare as declare; | 6 | pub use embassy_macros::interrupt_declare as declare; |
| 7 | pub use embassy_macros::interrupt_take as take; | 7 | pub use embassy_macros::interrupt_take as take; |
| 8 | 8 | ||
| @@ -124,9 +124,8 @@ impl<T: Interrupt + ?Sized> InterruptExt for T { | |||
| 124 | #[inline] | 124 | #[inline] |
| 125 | fn set_priority(&self, prio: Self::Priority) { | 125 | fn set_priority(&self, prio: Self::Priority) { |
| 126 | unsafe { | 126 | unsafe { |
| 127 | cortex_m::peripheral::Peripherals::steal() | 127 | let mut nvic: cortex_m::peripheral::NVIC = mem::transmute(()); |
| 128 | .NVIC | 128 | nvic.set_priority(NrWrap(self.number()), prio.into()) |
| 129 | .set_priority(NrWrap(self.number()), prio.into()) | ||
| 130 | } | 129 | } |
| 131 | } | 130 | } |
| 132 | } | 131 | } |
