diff options
| -rw-r--r-- | embassy-stm32/src/fmc/mod.rs | 10 | ||||
| m--------- | stm32-data | 0 |
2 files changed, 7 insertions, 3 deletions
diff --git a/embassy-stm32/src/fmc/mod.rs b/embassy-stm32/src/fmc/mod.rs index 856a4adca..4d48721d1 100644 --- a/embassy-stm32/src/fmc/mod.rs +++ b/embassy-stm32/src/fmc/mod.rs | |||
| @@ -27,9 +27,13 @@ where | |||
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | fn memory_controller_enable(&mut self) { | 29 | fn memory_controller_enable(&mut self) { |
| 30 | // The FMCEN bit of the FMC_BCR2..4 registers is don’t | 30 | // fmc v1 and v2 does not have the fmcen bit |
| 31 | // care. It is only enabled through the FMC_BCR1 register. | 31 | // fsmc v1, v2 and v3 does not have the fmcen bit |
| 32 | unsafe { T::regs().bcr1().modify(|r| r.set_fmcen(true)) }; | 32 | // This is a "not" because it is expected that all future versions have this bit |
| 33 | #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1)))] | ||
| 34 | unsafe { | ||
| 35 | T::regs().bcr1().modify(|r| r.set_fmcen(true)) | ||
| 36 | }; | ||
| 33 | } | 37 | } |
| 34 | 38 | ||
| 35 | fn source_clock_hz(&self) -> u32 { | 39 | fn source_clock_hz(&self) -> u32 { |
diff --git a/stm32-data b/stm32-data | |||
| Subproject 96decdd6114d78813c1f748fb878a45e1b03bf7 | Subproject cc93f9d10395077770bebefb6b9488e06b0e581 | ||
