aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--embassy-stm32/src/timer/mod.rs36
1 files changed, 17 insertions, 19 deletions
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 04919659b..8cd47aed4 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -88,7 +88,23 @@ pub(crate) mod sealed {
88 pub trait GeneralPurpose32bitInstance: GeneralPurpose16bitInstance { 88 pub trait GeneralPurpose32bitInstance: GeneralPurpose16bitInstance {
89 fn regs_gp32() -> crate::pac::timer::TimGp32; 89 fn regs_gp32() -> crate::pac::timer::TimGp32;
90 90
91 fn set_frequency(&mut self, frequency: Hertz); 91 fn set_frequency(&mut self, frequency: Hertz) {
92 use core::convert::TryInto;
93 let f = frequency.0;
94 assert!(f > 0);
95 let timer_f = Self::frequency().0;
96 let pclk_ticks_per_timer_period = (timer_f / f) as u64;
97 let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 32)).try_into());
98 let arr: u32 = unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into()));
99
100 let regs = Self::regs_gp32();
101 regs.psc().write(|r| r.set_psc(psc));
102 regs.arr().write(|r| r.set_arr(arr));
103
104 regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
105 regs.egr().write(|r| r.set_ug(true));
106 regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
107 }
92 } 108 }
93 109
94 pub trait AdvancedControlInstance: GeneralPurpose16bitInstance { 110 pub trait AdvancedControlInstance: GeneralPurpose16bitInstance {
@@ -352,24 +368,6 @@ macro_rules! impl_32bit_timer {
352 fn regs_gp32() -> crate::pac::timer::TimGp32 { 368 fn regs_gp32() -> crate::pac::timer::TimGp32 {
353 crate::pac::$inst 369 crate::pac::$inst
354 } 370 }
355
356 fn set_frequency(&mut self, frequency: Hertz) {
357 use core::convert::TryInto;
358 let f = frequency.0;
359 assert!(f > 0);
360 let timer_f = Self::frequency().0;
361 let pclk_ticks_per_timer_period = (timer_f / f) as u64;
362 let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 32)).try_into());
363 let arr: u32 = unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into()));
364
365 let regs = Self::regs_gp32();
366 regs.psc().write(|r| r.set_psc(psc));
367 regs.arr().write(|r| r.set_arr(arr));
368
369 regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
370 regs.egr().write(|r| r.set_ug(true));
371 regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
372 }
373 } 371 }
374 }; 372 };
375} 373}