3 files changed, 10 insertions, 2 deletions

diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index d8706ee39..c8ae7a357 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - chore: Updated stm32-metapac and stm32-data dependencies
 - feat: stm32/adc/v3: allow DMA reads to loop through enable channels
 - fix: Fix XSPI not disabling alternate bytes when they were previously enabled
+- fix: Fix stm32h7rs init when using external flash via XSPI
 
 ## 0.3.0 - 2025-08-12
 
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index e4a8ff0ab..3be98c462 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -526,7 +526,7 @@ fn init_hw(config: Config) -> Peripherals {
             }
         });
 
-        #[cfg(not(any(stm32f1, stm32wb, stm32wl)))]
+        #[cfg(not(any(stm32f1, stm32wb, stm32wl, stm32h7rs)))]
         rcc::enable_and_reset_with_cs::<peripherals::SYSCFG>(cs);
         #[cfg(not(any(stm32h5, stm32h7, stm32h7rs, stm32wb, stm32wl)))]
         rcc::enable_and_reset_with_cs::<peripherals::PWR>(cs);
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 837210b6a..331bab7a0 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -1,7 +1,7 @@
 use core::ops::RangeInclusive;
 
 #[cfg(stm32h7rs)]
-use stm32_metapac::rcc::vals::Plldivst;
+use stm32_metapac::rcc::vals::{Plldivst, Xspisel};
 
 use crate::pac;
 pub use crate::pac::rcc::vals::{
@@ -430,6 +430,13 @@ pub(crate) unsafe fn init(config: Config) {
     }
     while !RCC.cr().read().hsirdy() {}
 
+    #[cfg(stm32h7rs)]
+    {
+        // Switch the XSPI clock source so it will use HSI
+        RCC.ahbperckselr().modify(|w| w.set_xspi1sel(Xspisel::HCLK5));
+        RCC.ahbperckselr().modify(|w| w.set_xspi2sel(Xspisel::HCLK5));
+    };
+
     // Use the HSI clock as system clock during the actual clock setup
     RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
     while RCC.cfgr().read().sws() != Sysclk::HSI {}