5 files changed, 53 insertions, 48 deletions

diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 93a1f4f64..eb48fd6fe 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -17,6 +17,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: Added support for more OctoSPI configurations (e.g. APS6408 RAM) ([#4581](https://github.com/embassy-rs/embassy/pull/4581))
 - fix: stm32/usart: fix bug with blocking flush in buffered uart ([#4648](https://github.com/embassy-rs/embassy/pull/4648))
 - fix: stm32/(ospi/hspi/xspi): Fix the alternate bytes register config sticking around for subsequent writes
+- feat: Configurable gpio speed for QSPI
 
 ## 0.4.0 - 2025-08-26
 
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index c0cd216f0..0644069a6 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -48,6 +48,7 @@ impl Default for TransferConfig {
 
 /// QSPI driver configuration.
 #[derive(Clone, Copy)]
+#[non_exhaustive]
 pub struct Config {
     /// Flash memory size representend as 2^[0-32], as reasonable minimum 1KiB(9) was chosen.
     /// If you need other value the whose predefined use `Other` variant.
@@ -62,6 +63,8 @@ pub struct Config {
     pub cs_high_time: ChipSelectHighTime,
     /// Shift sampling point of input data (none, or half-cycle)
     pub sample_shifting: SampleShifting,
+    /// GPIO Speed
+    pub gpio_speed: Speed,
 }
 
 impl Default for Config {
@@ -73,6 +76,7 @@ impl Default for Config {
             fifo_threshold: FIFOThresholdLevel::_17Bytes,
             cs_high_time: ChipSelectHighTime::_5Cycle,
             sample_shifting: SampleShifting::None,
+            gpio_speed: Speed::VeryHigh,
         }
     }
 }
@@ -286,14 +290,14 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             None,
             config,
@@ -314,14 +318,14 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             None,
             config,
@@ -345,14 +349,14 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             new_dma!(dma),
             config,
@@ -374,14 +378,14 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             new_dma!(dma),
             config,
diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs
index ab29ddeff..80652b865 100644
--- a/examples/stm32f7/src/bin/qspi.rs
+++ b/examples/stm32f7/src/bin/qspi.rs
@@ -273,14 +273,14 @@ async fn main(_spawner: Spawner) -> ! {
     let p = embassy_stm32::init(config);
     info!("Embassy initialized");
 
-    let config = QspiCfg {
-        memory_size: MemorySize::_8MiB,
-        address_size: AddressSize::_24bit,
-        prescaler: 16,
-        cs_high_time: ChipSelectHighTime::_1Cycle,
-        fifo_threshold: FIFOThresholdLevel::_16Bytes,
-        sample_shifting: SampleShifting::None,
-    };
+    let mut config = QspiCfg::default();
+    config.memory_size = MemorySize::_8MiB;
+    config.address_size = AddressSize::_24bit;
+    config.prescaler = 16;
+    config.cs_high_time = ChipSelectHighTime::_1Cycle;
+    config.fifo_threshold = FIFOThresholdLevel::_16Bytes;
+    config.sample_shifting = SampleShifting::None;
+
     let driver = Qspi::new_bank1(
         p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config,
     );
diff --git a/examples/stm32h742/src/bin/qspi.rs b/examples/stm32h742/src/bin/qspi.rs
index 50e37ec52..9e79d7089 100644
--- a/examples/stm32h742/src/bin/qspi.rs
+++ b/examples/stm32h742/src/bin/qspi.rs
@@ -266,14 +266,14 @@ async fn main(_spawner: Spawner) -> ! {
     let p = embassy_stm32::init(config);
     info!("Embassy initialized");
 
-    let config = QspiCfg {
-        memory_size: MemorySize::_8MiB,
-        address_size: AddressSize::_24bit,
-        prescaler: 16,
-        cs_high_time: ChipSelectHighTime::_1Cycle,
-        fifo_threshold: FIFOThresholdLevel::_16Bytes,
-        sample_shifting: SampleShifting::None,
-    };
+    let mut config = QspiCfg::default();
+    config.memory_size = MemorySize::_8MiB;
+    config.address_size = AddressSize::_24bit;
+    config.prescaler = 16;
+    config.cs_high_time = ChipSelectHighTime::_1Cycle;
+    config.fifo_threshold = FIFOThresholdLevel::_16Bytes;
+    config.sample_shifting = SampleShifting::None;
+
     let driver = Qspi::new_blocking_bank1(p.QUADSPI, p.PD11, p.PD12, p.PE2, p.PD13, p.PB2, p.PB10, config);
     let mut flash = FlashMemory::new(driver);
     let flash_id = flash.read_id();
diff --git a/examples/stm32l432/src/bin/qspi_mmap.rs b/examples/stm32l432/src/bin/qspi_mmap.rs
index 075458fe5..feabdd532 100644
--- a/examples/stm32l432/src/bin/qspi_mmap.rs
+++ b/examples/stm32l432/src/bin/qspi_mmap.rs
@@ -246,14 +246,14 @@ const MEMORY_ADDR: u32 = 0x00000000 as u32;
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
 
-    let config = qspi::Config {
-        memory_size: MemorySize::_16MiB,
-        address_size: AddressSize::_24bit,
-        prescaler: 200,
-        cs_high_time: ChipSelectHighTime::_1Cycle,
-        fifo_threshold: FIFOThresholdLevel::_16Bytes,
-        sample_shifting: SampleShifting::None,
-    };
+    let mut config = qspi::Config::default();
+    config.memory_size = MemorySize::_16MiB;
+    config.address_size = AddressSize::_24bit;
+    config.prescaler = 200;
+    config.cs_high_time = ChipSelectHighTime::_1Cycle;
+    config.fifo_threshold = FIFOThresholdLevel::_16Bytes;
+    config.sample_shifting = SampleShifting::None;
+
     let driver = qspi::Qspi::new_bank1(p.QUADSPI, p.PB1, p.PB0, p.PA7, p.PA6, p.PA3, p.PA2, p.DMA2_CH7, config);
     let mut flash = FlashMemory::new(driver);
     let mut wr_buf = [0u8; 256];