3 files changed, 78 insertions, 216 deletions

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index ee88d4541..f45a571f2 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -430,6 +430,8 @@ fn main() {
 
     let mut clock_names = BTreeSet::new();
 
+    let mut rcc_cfgr_regs = BTreeMap::new();
+
     for p in METADATA.peripherals {
         if !singletons.contains(&p.name.to_string()) {
             continue;
@@ -508,6 +510,16 @@ fn main() {
                     let field_name = format_ident!("{}", field_name);
                     let enum_name = format_ident!("{}", enum_name);
 
+                    if !rcc_cfgr_regs.contains_key(mux.register) {
+                        rcc_cfgr_regs.insert(mux.register, Vec::new());
+                    }
+
+                    rcc_cfgr_regs.get_mut(mux.register).unwrap().push((
+                        fieldset_name.clone(),
+                        field_name.clone(),
+                        enum_name.clone(),
+                    ));
+
                     let match_arms: TokenStream = enumm
                         .variants
                         .iter()
@@ -590,6 +602,63 @@ fn main() {
         }
     }
 
+    for (rcc_cfgr_reg, fields) in rcc_cfgr_regs {
+        println!("cargo:rustc-cfg={}", rcc_cfgr_reg.to_ascii_lowercase());
+
+        let struct_fields: Vec<_> = fields
+            .iter()
+            .map(|(_fieldset, fieldname, enum_name)| {
+                quote! {
+                    pub #fieldname: Option<crate::pac::rcc::vals::#enum_name>
+                }
+            })
+            .collect();
+
+        let field_names: Vec<_> = fields
+            .iter()
+            .map(|(_fieldset, fieldname, _enum_name)| fieldname)
+            .collect();
+
+        let inits: Vec<_> = fields
+            .iter()
+            .map(|(fieldset, fieldname, _enum_name)| {
+                let setter = format_ident!("set_{}", fieldname);
+                quote! {
+                    match self.#fieldname {
+                        None => {}
+                        Some(val) => {
+                            crate::pac::RCC.#fieldset()
+                                .modify(|w| w.#setter(val));
+                        }
+                    };
+                }
+            })
+            .collect();
+
+        let cfgr_reg = format_ident!("{}", rcc_cfgr_reg);
+
+        g.extend(quote! {
+            #[derive(Clone, Copy)]
+            pub struct #cfgr_reg {
+                #( #struct_fields, )*
+            }
+
+            impl Default for #cfgr_reg {
+                fn default() -> Self {
+                    Self {
+                        #( #field_names: None, )*
+                    }
+                }
+            }
+
+            impl #cfgr_reg {
+                pub fn init(self) {
+                    #( #inits )*
+                }
+            }
+        });
+    }
+
     // Generate RCC
     clock_names.insert("sys".to_string());
     clock_names.insert("rtc".to_string());
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 02c3425d1..a61aae0e8 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -74,116 +74,6 @@ pub enum HrtimClockSource {
     PllClk,
 }
 
-#[cfg(all(stm32f3, not(rcc_f37)))]
-#[derive(Clone, Copy, PartialEq, Eq)]
-pub enum TimClockSource {
-    PClk2,
-    PllClk,
-}
-
-#[cfg(all(stm32f3, not(rcc_f37)))]
-#[derive(Clone, Copy)]
-pub struct TimClockSources {
-    pub tim1: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    pub tim2: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    pub tim34: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_B, package_C, package_D, package_E)),
-        stm32f358,
-        stm32f398
-    ))]
-    pub tim8: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    pub tim15: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    pub tim16: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    pub tim17: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-    pub tim20: TimClockSource,
-}
-
-#[cfg(all(stm32f3, not(rcc_f37)))]
-impl Default for TimClockSources {
-    fn default() -> Self {
-        Self {
-            tim1: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                all(stm32f302, any(package_D, package_E)),
-                stm32f398
-            ))]
-            tim2: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                all(stm32f302, any(package_D, package_E)),
-                stm32f398
-            ))]
-            tim34: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_B, package_C, package_D, package_E)),
-                stm32f358,
-                stm32f398
-            ))]
-            tim8: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                stm32f301,
-                stm32f318,
-                all(stm32f302, any(package_6, package_8)),
-                stm32f398
-            ))]
-            tim15: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                stm32f301,
-                stm32f318,
-                all(stm32f302, any(package_6, package_8)),
-                stm32f398
-            ))]
-            tim16: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                stm32f301,
-                stm32f318,
-                all(stm32f302, any(package_6, package_8)),
-                stm32f398
-            ))]
-            tim17: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-            tim20: TimClockSource::PClk2,
-        }
-    }
-}
-
 /// Clocks configutation
 #[non_exhaustive]
 pub struct Config {
@@ -209,8 +99,8 @@ pub struct Config {
     pub adc34: AdcClockSource,
     #[cfg(stm32f334)]
     pub hrtim: HrtimClockSource,
-    #[cfg(all(stm32f3, not(rcc_f37)))]
-    pub tim: TimClockSources,
+    #[cfg(cfgr3)]
+    pub cfgr3: crate::_generated::CFGR3,
 
     pub ls: super::LsConfig,
 }
@@ -240,8 +130,8 @@ impl Default for Config {
             adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(stm32f334)]
             hrtim: HrtimClockSource::BusClk,
-            #[cfg(all(stm32f3, not(rcc_f37)))]
-            tim: Default::default(),
+            #[cfg(cfgr3)]
+            cfgr3: Default::default(),
         }
     }
 }
@@ -477,107 +367,8 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(all(stm32f3, not(rcc_f37)))]
-    match config.tim.tim1 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    match config.tim.tim2 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    match config.tim.tim34 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_B, package_C, package_D, package_E)),
-        stm32f358,
-        stm32f398
-    ))]
-    match config.tim.tim8 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    match config.tim.tim15 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    match config.tim.tim16 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    match config.tim.tim17 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    }
-
-    #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-    match config.tim.tim20 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    }
+    #[cfg(cfgr3)]
+    config.cfgr3.init();
 
     set_clocks!(
         hsi: hsi,
diff --git a/examples/stm32f3/src/bin/usart_dma.rs b/examples/stm32f3/src/bin/usart_dma.rs
index 5234e53b9..7dc905adc 100644
--- a/examples/stm32f3/src/bin/usart_dma.rs
+++ b/examples/stm32f3/src/bin/usart_dma.rs
@@ -17,7 +17,9 @@ bind_interrupts!(struct Irqs {
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let p = embassy_stm32::init(Default::default());
+    let mut init_config = embassy_stm32::Config::default();
+    init_config.rcc.cfgr3.usart1sw = Some(embassy_stm32::pac::rcc::vals::Usart1sw::HSI);
+    let p = embassy_stm32::init(init_config);
     info!("Hello World!");
 
     let config = Config::default();