diff options
| -rw-r--r-- | embassy-stm32/src/adc/v3.rs | 32 | ||||
| -rw-r--r-- | embassy-stm32/src/dac/v2.rs | 6 | ||||
| -rw-r--r-- | embassy-stm32/src/dma/bdma.rs | 9 | ||||
| -rw-r--r-- | embassy-stm32/src/dma/dmamux.rs | 2 | ||||
| -rw-r--r-- | embassy-stm32/src/exti.rs | 2 | ||||
| -rw-r--r-- | embassy-stm32/src/rcc/mod.rs | 10 | ||||
| m--------- | stm32-data | 0 |
7 files changed, 37 insertions, 24 deletions
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 6f36daa23..387b62470 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs | |||
| @@ -9,11 +9,11 @@ pub const VDDA_CALIB_MV: u32 = 3000; | |||
| 9 | /// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock | 9 | /// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock |
| 10 | /// configuration. | 10 | /// configuration. |
| 11 | unsafe fn enable() { | 11 | unsafe fn enable() { |
| 12 | #[cfg(rcc_h7)] | 12 | #[cfg(stm32h7)] |
| 13 | crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true)); | 13 | crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true)); |
| 14 | #[cfg(rcc_g0)] | 14 | #[cfg(stm32g0)] |
| 15 | crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true)); | 15 | crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true)); |
| 16 | #[cfg(rcc_l4)] | 16 | #[cfg(stm32l4)] |
| 17 | crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true)); | 17 | crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true)); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| @@ -54,9 +54,9 @@ pub struct Vref; | |||
| 54 | impl<T: Instance> AdcPin<T> for Vref {} | 54 | impl<T: Instance> AdcPin<T> for Vref {} |
| 55 | impl<T: Instance> super::sealed::AdcPin<T> for Vref { | 55 | impl<T: Instance> super::sealed::AdcPin<T> for Vref { |
| 56 | fn channel(&self) -> u8 { | 56 | fn channel(&self) -> u8 { |
| 57 | #[cfg(not(rcc_g0))] | 57 | #[cfg(not(stm32g0))] |
| 58 | let val = 0; | 58 | let val = 0; |
| 59 | #[cfg(rcc_g0)] | 59 | #[cfg(stm32g0)] |
| 60 | let val = 13; | 60 | let val = 13; |
| 61 | val | 61 | val |
| 62 | } | 62 | } |
| @@ -66,9 +66,9 @@ pub struct Temperature; | |||
| 66 | impl<T: Instance> AdcPin<T> for Temperature {} | 66 | impl<T: Instance> AdcPin<T> for Temperature {} |
| 67 | impl<T: Instance> super::sealed::AdcPin<T> for Temperature { | 67 | impl<T: Instance> super::sealed::AdcPin<T> for Temperature { |
| 68 | fn channel(&self) -> u8 { | 68 | fn channel(&self) -> u8 { |
| 69 | #[cfg(not(rcc_g0))] | 69 | #[cfg(not(stm32g0))] |
| 70 | let val = 17; | 70 | let val = 17; |
| 71 | #[cfg(rcc_g0)] | 71 | #[cfg(stm32g0)] |
| 72 | let val = 12; | 72 | let val = 12; |
| 73 | val | 73 | val |
| 74 | } | 74 | } |
| @@ -78,9 +78,9 @@ pub struct Vbat; | |||
| 78 | impl<T: Instance> AdcPin<T> for Vbat {} | 78 | impl<T: Instance> AdcPin<T> for Vbat {} |
| 79 | impl<T: Instance> super::sealed::AdcPin<T> for Vbat { | 79 | impl<T: Instance> super::sealed::AdcPin<T> for Vbat { |
| 80 | fn channel(&self) -> u8 { | 80 | fn channel(&self) -> u8 { |
| 81 | #[cfg(not(rcc_g0))] | 81 | #[cfg(not(stm32g0))] |
| 82 | let val = 18; | 82 | let val = 18; |
| 83 | #[cfg(rcc_g0)] | 83 | #[cfg(stm32g0)] |
| 84 | let val = 14; | 84 | let val = 14; |
| 85 | val | 85 | val |
| 86 | } | 86 | } |
| @@ -281,7 +281,7 @@ impl<'d, T: Instance> Adc<'d, T> { | |||
| 281 | /// Calculates the system VDDA by sampling the internal VREF channel and comparing | 281 | /// Calculates the system VDDA by sampling the internal VREF channel and comparing |
| 282 | /// the result with the value stored at the factory. If the chip's VDDA is not stable, run | 282 | /// the result with the value stored at the factory. If the chip's VDDA is not stable, run |
| 283 | /// this before each ADC conversion. | 283 | /// this before each ADC conversion. |
| 284 | #[cfg(not(rcc_g0))] // TODO is this supposed to be public? | 284 | #[cfg(not(stm32g0))] // TODO is this supposed to be public? |
| 285 | #[allow(unused)] // TODO is this supposed to be public? | 285 | #[allow(unused)] // TODO is this supposed to be public? |
| 286 | fn calibrate(&mut self, vref: &mut Vref) { | 286 | fn calibrate(&mut self, vref: &mut Vref) { |
| 287 | let vref_cal = unsafe { crate::pac::VREFINTCAL.data().read().value() }; | 287 | let vref_cal = unsafe { crate::pac::VREFINTCAL.data().read().value() }; |
| @@ -363,11 +363,11 @@ impl<'d, T: Instance> Adc<'d, T> { | |||
| 363 | } | 363 | } |
| 364 | 364 | ||
| 365 | // Configure ADC | 365 | // Configure ADC |
| 366 | #[cfg(not(rcc_g0))] | 366 | #[cfg(not(stm32g0))] |
| 367 | T::regs() | 367 | T::regs() |
| 368 | .cfgr() | 368 | .cfgr() |
| 369 | .modify(|reg| reg.set_res(self.resolution.res())); | 369 | .modify(|reg| reg.set_res(self.resolution.res())); |
| 370 | #[cfg(rcc_g0)] | 370 | #[cfg(stm32g0)] |
| 371 | T::regs() | 371 | T::regs() |
| 372 | .cfgr1() | 372 | .cfgr1() |
| 373 | .modify(|reg| reg.set_res(self.resolution.res())); | 373 | .modify(|reg| reg.set_res(self.resolution.res())); |
| @@ -376,9 +376,9 @@ impl<'d, T: Instance> Adc<'d, T> { | |||
| 376 | Self::set_channel_sample_time(pin.channel(), self.sample_time); | 376 | Self::set_channel_sample_time(pin.channel(), self.sample_time); |
| 377 | 377 | ||
| 378 | // Select channel | 378 | // Select channel |
| 379 | #[cfg(not(rcc_g0))] | 379 | #[cfg(not(stm32g0))] |
| 380 | T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel())); | 380 | T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel())); |
| 381 | #[cfg(rcc_g0)] | 381 | #[cfg(stm32g0)] |
| 382 | T::regs() | 382 | T::regs() |
| 383 | .chselr() | 383 | .chselr() |
| 384 | .write(|reg| reg.set_chsel(pin.channel() as u32)); | 384 | .write(|reg| reg.set_chsel(pin.channel() as u32)); |
| @@ -400,14 +400,14 @@ impl<'d, T: Instance> Adc<'d, T> { | |||
| 400 | } | 400 | } |
| 401 | } | 401 | } |
| 402 | 402 | ||
| 403 | #[cfg(rcc_g0)] | 403 | #[cfg(stm32g0)] |
| 404 | unsafe fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) { | 404 | unsafe fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) { |
| 405 | T::regs() | 405 | T::regs() |
| 406 | .smpr() | 406 | .smpr() |
| 407 | .modify(|reg| reg.set_smp1(sample_time.sample_time())); | 407 | .modify(|reg| reg.set_smp1(sample_time.sample_time())); |
| 408 | } | 408 | } |
| 409 | 409 | ||
| 410 | #[cfg(not(rcc_g0))] | 410 | #[cfg(not(stm32g0))] |
| 411 | unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) { | 411 | unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) { |
| 412 | if ch <= 9 { | 412 | if ch <= 9 { |
| 413 | T::regs() | 413 | T::regs() |
diff --git a/embassy-stm32/src/dac/v2.rs b/embassy-stm32/src/dac/v2.rs index 751eebf79..9fb01fa94 100644 --- a/embassy-stm32/src/dac/v2.rs +++ b/embassy-stm32/src/dac/v2.rs | |||
| @@ -115,9 +115,11 @@ impl<'d, T: Instance> Dac<'d, T> { | |||
| 115 | // configuration. | 115 | // configuration. |
| 116 | #[cfg(rcc_h7)] | 116 | #[cfg(rcc_h7)] |
| 117 | crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true)); | 117 | crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true)); |
| 118 | #[cfg(rcc_g0)] | 118 | #[cfg(rcc_h7ab)] |
| 119 | crate::pac::RCC.apb1lenr().modify(|w| w.set_dac1en(true)); | ||
| 120 | #[cfg(stm32g0)] | ||
| 119 | crate::pac::RCC.apbenr1().modify(|w| w.set_dac1en(true)); | 121 | crate::pac::RCC.apbenr1().modify(|w| w.set_dac1en(true)); |
| 120 | #[cfg(rcc_l4)] | 122 | #[cfg(stm32l4)] |
| 121 | crate::pac::RCC.apb1enr1().modify(|w| w.set_dac1en(true)); | 123 | crate::pac::RCC.apb1enr1().modify(|w| w.set_dac1en(true)); |
| 122 | 124 | ||
| 123 | if channels >= 1 { | 125 | if channels >= 1 { |
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs index a37de2d63..2f0715cf6 100644 --- a/embassy-stm32/src/dma/bdma.rs +++ b/embassy-stm32/src/dma/bdma.rs | |||
| @@ -49,6 +49,12 @@ macro_rules! dma_num { | |||
| 49 | (BDMA) => { | 49 | (BDMA) => { |
| 50 | 0 | 50 | 0 |
| 51 | }; | 51 | }; |
| 52 | (BDMA1) => { | ||
| 53 | 0 | ||
| 54 | }; | ||
| 55 | (BDMA2) => { | ||
| 56 | 1 | ||
| 57 | }; | ||
| 52 | } | 58 | } |
| 53 | 59 | ||
| 54 | pub(crate) unsafe fn on_irq() { | 60 | pub(crate) unsafe fn on_irq() { |
| @@ -80,6 +86,9 @@ pub(crate) unsafe fn init() { | |||
| 80 | } | 86 | } |
| 81 | 87 | ||
| 82 | pac::dma_channels! { | 88 | pac::dma_channels! { |
| 89 | ($channel_peri:ident, BDMA1, bdma, $channel_num:expr, $dmamux:tt) => { | ||
| 90 | // BDMA1 in H7 doesn't use DMAMUX, which breaks | ||
| 91 | }; | ||
| 83 | ($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $dmamux:tt) => { | 92 | ($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $dmamux:tt) => { |
| 84 | impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri { | 93 | impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri { |
| 85 | 94 | ||
diff --git a/embassy-stm32/src/dma/dmamux.rs b/embassy-stm32/src/dma/dmamux.rs index fd076581b..971695a06 100644 --- a/embassy-stm32/src/dma/dmamux.rs +++ b/embassy-stm32/src/dma/dmamux.rs | |||
| @@ -28,7 +28,7 @@ pub(crate) mod sealed { | |||
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | pub struct DMAMUX1; | 30 | pub struct DMAMUX1; |
| 31 | #[cfg(rcc_h7)] | 31 | #[cfg(stm32h7)] |
| 32 | pub struct DMAMUX2; | 32 | pub struct DMAMUX2; |
| 33 | 33 | ||
| 34 | pub trait MuxChannel: sealed::MuxChannel + super::Channel { | 34 | pub trait MuxChannel: sealed::MuxChannel + super::Channel { |
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs index 07d086843..909d0ee88 100644 --- a/embassy-stm32/src/exti.rs +++ b/embassy-stm32/src/exti.rs | |||
| @@ -388,6 +388,6 @@ pub(crate) unsafe fn init() { | |||
| 388 | 388 | ||
| 389 | #[cfg(not(any(rcc_wb, rcc_wl5, rcc_f1)))] | 389 | #[cfg(not(any(rcc_wb, rcc_wl5, rcc_f1)))] |
| 390 | <crate::peripherals::SYSCFG as crate::rcc::sealed::RccPeripheral>::enable(); | 390 | <crate::peripherals::SYSCFG as crate::rcc::sealed::RccPeripheral>::enable(); |
| 391 | #[cfg(rcc_f1)] | 391 | #[cfg(stm32f1)] |
| 392 | <crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable(); | 392 | <crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable(); |
| 393 | } | 393 | } |
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 5c223bc43..01c66f76f 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs | |||
| @@ -33,18 +33,20 @@ pub struct Clocks { | |||
| 33 | pub apb2_tim: Hertz, | 33 | pub apb2_tim: Hertz, |
| 34 | #[cfg(any(rcc_wl5, rcc_u5))] | 34 | #[cfg(any(rcc_wl5, rcc_u5))] |
| 35 | pub apb3: Hertz, | 35 | pub apb3: Hertz, |
| 36 | #[cfg(any(rcc_h7))] | 36 | #[cfg(any(rcc_h7, rcc_h7ab))] |
| 37 | pub apb4: Hertz, | 37 | pub apb4: Hertz, |
| 38 | 38 | ||
| 39 | // AHB | 39 | // AHB |
| 40 | pub ahb1: Hertz, | 40 | pub ahb1: Hertz, |
| 41 | #[cfg(any( | 41 | #[cfg(any( |
| 42 | rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_g4, rcc_u5, rcc_wb, rcc_wl5 | 42 | rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb, rcc_wl5 |
| 43 | ))] | 43 | ))] |
| 44 | pub ahb2: Hertz, | 44 | pub ahb2: Hertz, |
| 45 | #[cfg(any(rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_u5, rcc_wb, rcc_wl5))] | 45 | #[cfg(any( |
| 46 | rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5 | ||
| 47 | ))] | ||
| 46 | pub ahb3: Hertz, | 48 | pub ahb3: Hertz, |
| 47 | #[cfg(any(rcc_h7))] | 49 | #[cfg(any(rcc_h7, rcc_h7ab))] |
| 48 | pub ahb4: Hertz, | 50 | pub ahb4: Hertz, |
| 49 | 51 | ||
| 50 | #[cfg(any(rcc_f4, rcc_f410, rcc_f7))] | 52 | #[cfg(any(rcc_f4, rcc_f410, rcc_f7))] |
diff --git a/stm32-data b/stm32-data | |||
| Subproject 608581a8960b95c4d472f59d0b028b47053d587 | Subproject cb78ac90ba8607d6bb38296607c02e28c60391f | ||
