diff options
| -rw-r--r-- | stm32-metapac/build.rs | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs index 91b76b2a4..46660d9bd 100644 --- a/stm32-metapac/build.rs +++ b/stm32-metapac/build.rs | |||
| @@ -219,7 +219,12 @@ fn main() { | |||
| 219 | } | 219 | } |
| 220 | "spi" => { | 220 | "spi" => { |
| 221 | if let Some(clock) = &p.clock { | 221 | if let Some(clock) = &p.clock { |
| 222 | let reg = clock.to_ascii_lowercase(); | 222 | // Workaround for APB1 register being split on some chip families |
| 223 | let reg = if chip.family == "STM32H7" && clock == "APB1" { | ||
| 224 | format!("{}l", clock.to_ascii_lowercase()) | ||
| 225 | } else { | ||
| 226 | clock.to_ascii_lowercase() | ||
| 227 | }; | ||
| 223 | let field = name.to_ascii_lowercase(); | 228 | let field = name.to_ascii_lowercase(); |
| 224 | peripheral_rcc_table.push(vec