diff options
| -rw-r--r-- | embassy-stm32/src/spi/v2.rs | 45 | ||||
| -rw-r--r-- | embassy-stm32/src/spi/v3.rs | 50 |
2 files changed, 34 insertions, 61 deletions
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs index 488e80ef8..83ff70009 100644 --- a/embassy-stm32/src/spi/v2.rs +++ b/embassy-stm32/src/spi/v2.rs | |||
| @@ -1,9 +1,8 @@ | |||
| 1 | #![macro_use] | 1 | #![macro_use] |
| 2 | 2 | ||
| 3 | use crate::dma::NoDma; | 3 | use crate::dma::NoDma; |
| 4 | use crate::gpio::{AnyPin, Pin}; | 4 | use crate::gpio::sealed::Pin; |
| 5 | use crate::pac::gpio::vals::{Afr, Moder}; | 5 | use crate::gpio::AnyPin; |
| 6 | use crate::pac::gpio::Gpio; | ||
| 7 | use crate::pac::spi; | 6 | use crate::pac::spi; |
| 8 | use crate::spi::{ | 7 | use crate::spi::{ |
| 9 | ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel, | 8 | ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel, |
| @@ -68,12 +67,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 68 | let miso = miso.degrade_optional(); | 67 | let miso = miso.degrade_optional(); |
| 69 | 68 | ||
| 70 | unsafe { | 69 | unsafe { |
| 71 | sck.as_ref() | 70 | sck.as_ref().map(|x| { |
| 72 | .map(|x| Self::configure_pin(x.block(), x.pin() as _, sck_af)); | 71 | x.set_as_af(sck_af, crate::gpio::sealed::AFType::OutputPushPull); |
| 73 | mosi.as_ref() | 72 | x.set_speed(crate::gpio::Speed::VeryHigh); |
| 74 | .map(|x| Self::configure_pin(x.block(), x.pin() as _, mosi_af)); | 73 | }); |
| 75 | miso.as_ref() | 74 | mosi.as_ref().map(|x| { |
| 76 | .map(|x| Self::configure_pin(x.block(), x.pin() as _, miso_af)); | 75 | x.set_as_af(mosi_af, crate::gpio::sealed::AFType::OutputPushPull); |
| 76 | x.set_speed(crate::gpio::Speed::VeryHigh); | ||
| 77 | }); | ||
| 78 | miso.as_ref().map(|x| { | ||
| 79 | x.set_as_af(miso_af, crate::gpio::sealed::AFType::Input); | ||
| 80 | x.set_speed(crate::gpio::Speed::VeryHigh); | ||
| 81 | }); | ||
| 77 | } | 82 | } |
| 78 | 83 | ||
| 79 | let pclk = T::frequency(); | 84 | let pclk = T::frequency(); |
| @@ -122,16 +127,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 122 | } | 127 | } |
| 123 | } | 128 | } |
| 124 | 129 | ||
| 125 | unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) { | ||
| 126 | let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; | ||
| 127 | block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); | ||
| 128 | block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); | ||
| 129 | } | ||
| 130 | |||
| 131 | unsafe fn unconfigure_pin(block: Gpio, pin: usize) { | ||
| 132 | block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG)); | ||
| 133 | } | ||
| 134 | |||
| 135 | fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { | 130 | fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { |
| 136 | match clocks.0 / freq.0 { | 131 | match clocks.0 / freq.0 { |
| 137 | 0 => unreachable!(), | 132 | 0 => unreachable!(), |
| @@ -322,15 +317,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 322 | impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> { | 317 | impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> { |
| 323 | fn drop(&mut self) { | 318 | fn drop(&mut self) { |
| 324 | unsafe { | 319 | unsafe { |
| 325 | self.sck | 320 | self.sck.as_ref().map(|x| x.set_as_analog()); |
| 326 | .as_ref() | 321 | self.mosi.as_ref().map(|x| x.set_as_analog()); |
| 327 | .map(|x| Self::unconfigure_pin(x.block(), x.pin() as _)); | 322 | self.miso.as_ref().map(|x| x.set_as_analog()); |
| 328 | self.mosi | ||
| 329 | .as_ref() | ||
| 330 | .map(|x| Self::unconfigure_pin(x.block(), x.pin() as _)); | ||
| 331 | self.miso | ||
| 332 | .as_ref() | ||
| 333 | .map(|x| Self::unconfigure_pin(x.block(), x.pin() as _)); | ||
| 334 | } | 323 | } |
| 335 | } | 324 | } |
| 336 | } | 325 | } |
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs index ef0f123f1..e8ef33176 100644 --- a/embassy-stm32/src/spi/v3.rs +++ b/embassy-stm32/src/spi/v3.rs | |||
| @@ -1,9 +1,8 @@ | |||
| 1 | #![macro_use] | 1 | #![macro_use] |
| 2 | 2 | ||
| 3 | use crate::dma::NoDma; | 3 | use crate::dma::NoDma; |
| 4 | use crate::gpio::{AnyPin, Pin}; | 4 | use crate::gpio::sealed::Pin; |
| 5 | use crate::pac::gpio::vals::{Afr, Moder}; | 5 | use crate::gpio::AnyPin; |
| 6 | use crate::pac::gpio::Gpio; | ||
| 7 | use crate::pac::spi; | 6 | use crate::pac::spi; |
| 8 | use crate::spi::{ | 7 | use crate::spi::{ |
| 9 | ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel, | 8 | ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel, |
| @@ -70,14 +69,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 70 | let miso = miso.degrade_optional(); | 69 | let miso = miso.degrade_optional(); |
| 71 | 70 | ||
| 72 | unsafe { | 71 | unsafe { |
| 73 | sck.as_ref() | 72 | sck.as_ref().map(|x| { |
| 74 | .map(|x| Self::configure_pin(x.block(), x.pin() as _, sck_af)); | 73 | x.set_as_af(sck_af, crate::gpio::sealed::AFType::OutputPushPull); |
| 75 | //sck.block().otyper().modify(|w| w.set_ot(Pin::pin(sck) as _, crate::pac::gpio::vals::Ot::PUSHPULL)); | 74 | x.set_speed(crate::gpio::Speed::VeryHigh); |
| 76 | sck.as_ref() | 75 | }); |
| 77 | .map(|x| Self::configure_pin(x.block(), x.pin() as _, mosi_af)); | 76 | mosi.as_ref().map(|x| { |
| 78 | //mosi.block().otyper().modify(|w| w.set_ot(Pin::pin(mosi) as _, crate::pac::gpio::vals::Ot::PUSHPULL)); | 77 | x.set_as_af(mosi_af, crate::gpio::sealed::AFType::OutputPushPull); |
| 79 | sck.as_ref() | 78 | x.set_speed(crate::gpio::Speed::VeryHigh); |
| 80 | .map(|x| Self::configure_pin(x.block(), x.pin() as _, miso_af)); | 79 | }); |
| 80 | miso.as_ref().map(|x| { | ||
| 81 | x.set_as_af(miso_af, crate::gpio::sealed::AFType::Input); | ||
| 82 | x.set_speed(crate::gpio::Speed::VeryHigh); | ||
| 83 | }); | ||
| 81 | } | 84 | } |
| 82 | 85 | ||
| 83 | let pclk = T::frequency(); | 86 | let pclk = T::frequency(); |
| @@ -137,19 +140,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 137 | } | 140 | } |
| 138 | } | 141 | } |
| 139 | 142 | ||
| 140 | unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) { | ||
| 141 | let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; | ||
| 142 | block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); | ||
| 143 | block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); | ||
| 144 | block | ||
| 145 | .ospeedr() | ||
| 146 | .modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED)); | ||
| 147 | } | ||
| 148 | |||
| 149 | unsafe fn unconfigure_pin(block: Gpio, pin: usize) { | ||
| 150 | block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG)); | ||
| 151 | } | ||
| 152 | |||
| 153 | fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { | 143 | fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { |
| 154 | match clocks.0 / freq.0 { | 144 | match clocks.0 / freq.0 { |
| 155 | 0 => unreachable!(), | 145 | 0 => unreachable!(), |
| @@ -346,15 +336,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 346 | impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> { | 336 | impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> { |
| 347 | fn drop(&mut self) { | 337 | fn drop(&mut self) { |
| 348 | unsafe { | 338 | unsafe { |
| 349 | self.sck | 339 | self.sck.as_ref().map(|x| x.set_as_analog()); |
| 350 | .as_ref() | 340 | self.mosi.as_ref().map(|x| x.set_as_analog()); |
| 351 | .map(|x| Self::unconfigure_pin(x.block(), x.pin() as _)); | 341 | self.miso.as_ref().map(|x| x.set_as_analog()); |
| 352 | self.mosi | ||
| 353 | .as_ref() | ||
| 354 | .map(|x| Self::unconfigure_pin(x.block(), x.pin() as _)); | ||
| 355 | self.miso | ||
| 356 | .as_ref() | ||
| 357 | .map(|x| Self::unconfigure_pin(x.block(), x.pin() as _)); | ||
| 358 | } | 342 | } |
| 359 | } | 343 | } |
| 360 | } | 344 | } |
