33 files changed, 8667 insertions, 0 deletions

diff --git a/embassy-stm32/src/can/bx/filter.rs b/embassy-stm32/src/can/bx/filter.rs
new file mode 100644
index 000000000..acd2e4688
--- /dev/null
+++ b/embassy-stm32/src/can/bx/filter.rs
@@ -0,0 +1,510 @@
+//! Filter bank API.
+
+use core::marker::PhantomData;
+
+use crate::pac::can::RegisterBlock;
+use crate::{ExtendedId, Fifo, FilterOwner, Id, Instance, MasterInstance, StandardId};
+
+const F32_RTR: u32 = 0b010; // set the RTR bit to match remote frames
+const F32_IDE: u32 = 0b100; // set the IDE bit to match extended identifiers
+const F16_RTR: u16 = 0b10000;
+const F16_IDE: u16 = 0b01000;
+
+/// A 16-bit filter list entry.
+///
+/// This can match data and remote frames using standard IDs.
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub struct ListEntry16(u16);
+
+/// A 32-bit filter list entry.
+///
+/// This can match data and remote frames using extended or standard IDs.
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub struct ListEntry32(u32);
+
+/// A 16-bit identifier mask.
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub struct Mask16 {
+    id: u16,
+    mask: u16,
+}
+
+/// A 32-bit identifier mask.
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub struct Mask32 {
+    id: u32,
+    mask: u32,
+}
+
+impl ListEntry16 {
+    /// Creates a filter list entry that accepts data frames with the given standard ID.
+    ///
+    /// This entry will *not* accept remote frames with the same ID.
+    pub fn data_frames_with_id(id: StandardId) -> Self {
+        Self(id.as_raw() << 5)
+    }
+
+    /// Creates a filter list entry that accepts remote frames with the given standard ID.
+    pub fn remote_frames_with_id(id: StandardId) -> Self {
+        Self(id.as_raw() << 5 | F16_RTR)
+    }
+}
+
+impl ListEntry32 {
+    /// Creates a filter list entry that accepts data frames with the given ID.
+    ///
+    /// This entry will *not* accept remote frames with the same ID.
+    ///
+    /// The filter will only accept *either* standard *or* extended frames, depending on `id`.
+    pub fn data_frames_with_id(id: impl Into<Id>) -> Self {
+        match id.into() {
+            Id::Standard(id) => Self(u32::from(id.as_raw()) << 21),
+            Id::Extended(id) => Self(id.as_raw() << 3 | F32_IDE),
+        }
+    }
+
+    /// Creates a filter list entry that accepts remote frames with the given ID.
+    pub fn remote_frames_with_id(id: impl Into<Id>) -> Self {
+        match id.into() {
+            Id::Standard(id) => Self(u32::from(id.as_raw()) << 21 | F32_RTR),
+            Id::Extended(id) => Self(id.as_raw() << 3 | F32_IDE | F32_RTR),
+        }
+    }
+}
+
+impl Mask16 {
+    /// Creates a 16-bit identifier mask that accepts all frames.
+    ///
+    /// This will accept both standard and extended data and remote frames with any ID.
+    pub fn accept_all() -> Self {
+        Self { id: 0, mask: 0 }
+    }
+
+    /// Creates a 16-bit identifier mask that accepts all frames with the given standard
+    /// ID and mask combination.
+    ///
+    /// Filter logic: `frame_accepted = (incoming_id & mask) == (id & mask)`
+    ///
+    /// A mask of all all ones (`0x7FF`) matches an exact ID, a mask of 0 matches all IDs.
+    ///
+    /// Both data and remote frames with `id` will be accepted. Any extended frames will be
+    /// rejected.
+    pub fn frames_with_std_id(id: StandardId, mask: StandardId) -> Self {
+        Self {
+            id: id.as_raw() << 5,
+            mask: mask.as_raw() << 5 | F16_IDE, // also require IDE = 0
+        }
+    }
+
+    /// Make the filter accept data frames only.
+    pub fn data_frames_only(&mut self) -> &mut Self {
+        self.id &= !F16_RTR; // RTR = 0
+        self.mask |= F16_RTR;
+        self
+    }
+
+    /// Make the filter accept remote frames only.
+    pub fn remote_frames_only(&mut self) -> &mut Self {
+        self.id |= F16_RTR; // RTR = 1
+        self.mask |= F16_RTR;
+        self
+    }
+}
+
+impl Mask32 {
+    /// Creates a 32-bit identifier mask that accepts all frames.
+    ///
+    /// This will accept both standard and extended data and remote frames with any ID.
+    pub fn accept_all() -> Self {
+        Self { id: 0, mask: 0 }
+    }
+
+    /// Creates a 32-bit identifier mask that accepts all frames with the given extended
+    /// ID and mask combination.
+    ///
+    /// Filter logic: `frame_accepted = (incoming_id & mask) == (id & mask)`
+    ///
+    /// A mask of all all ones (`0x1FFF_FFFF`) matches an exact ID, a mask of 0 matches all IDs.
+    ///
+    /// Both data and remote frames with `id` will be accepted. Standard frames will be rejected.
+    pub fn frames_with_ext_id(id: ExtendedId, mask: ExtendedId) -> Self {
+        Self {
+            id: id.as_raw() << 3 | F32_IDE,
+            mask: mask.as_raw() << 3 | F32_IDE, // also require IDE = 1
+        }
+    }
+
+    /// Creates a 32-bit identifier mask that accepts all frames with the given standard
+    /// ID and mask combination.
+    ///
+    /// Filter logic: `frame_accepted = (incoming_id & mask) == (id & mask)`
+    ///
+    /// A mask of all all ones (`0x7FF`) matches the exact ID, a mask of 0 matches all IDs.
+    ///
+    /// Both data and remote frames with `id` will be accepted. Extended frames will be rejected.
+    pub fn frames_with_std_id(id: StandardId, mask: StandardId) -> Self {
+        Self {
+            id: u32::from(id.as_raw()) << 21,
+            mask: u32::from(mask.as_raw()) << 21 | F32_IDE, // also require IDE = 0
+        }
+    }
+
+    /// Make the filter accept data frames only.
+    pub fn data_frames_only(&mut self) -> &mut Self {
+        self.id &= !F32_RTR; // RTR = 0
+        self.mask |= F32_RTR;
+        self
+    }
+
+    /// Make the filter accept remote frames only.
+    pub fn remote_frames_only(&mut self) -> &mut Self {
+        self.id |= F32_RTR; // RTR = 1
+        self.mask |= F32_RTR;
+        self
+    }
+}
+
+/// The configuration of a filter bank.
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub enum BankConfig {
+    List16([ListEntry16; 4]),
+    List32([ListEntry32; 2]),
+    Mask16([Mask16; 2]),
+    Mask32(Mask32),
+}
+
+impl From<[ListEntry16; 4]> for BankConfig {
+    #[inline]
+    fn from(entries: [ListEntry16; 4]) -> Self {
+        Self::List16(entries)
+    }
+}
+
+impl From<[ListEntry32; 2]> for BankConfig {
+    #[inline]
+    fn from(entries: [ListEntry32; 2]) -> Self {
+        Self::List32(entries)
+    }
+}
+
+impl From<[Mask16; 2]> for BankConfig {
+    #[inline]
+    fn from(entries: [Mask16; 2]) -> Self {
+        Self::Mask16(entries)
+    }
+}
+
+impl From<Mask32> for BankConfig {
+    #[inline]
+    fn from(filter: Mask32) -> Self {
+        Self::Mask32(filter)
+    }
+}
+
+/// Interface to the filter banks of a CAN peripheral.
+pub struct MasterFilters<'a, I: FilterOwner> {
+    /// Number of assigned filter banks.
+    ///
+    /// On chips with splittable filter banks, this value can be dynamic.
+    bank_count: u8,
+    _can: PhantomData<&'a mut I>,
+}
+
+// NOTE: This type mutably borrows the CAN instance and has unique access to the registers while it
+// exists.
+impl<I: FilterOwner> MasterFilters<'_, I> {
+    pub(crate) unsafe fn new() -> Self {
+        let can = &*I::REGISTERS;
+
+        // Enable initialization mode.
+        can.fmr.modify(|_, w| w.finit().set_bit());
+
+        // Read the filter split value.
+        let bank_count = can.fmr.read().can2sb().bits();
+
+        // (Reset value of CAN2SB is 0x0E, 14, which, in devices with 14 filter banks, assigns all
+        // of them to the master peripheral, and in devices with 28, assigns them 50/50 to
+        // master/slave instances)
+
+        Self {
+            bank_count,
+            _can: PhantomData,
+        }
+    }
+
+    fn registers(&self) -> &RegisterBlock {
+        unsafe { &*I::REGISTERS }
+    }
+
+    fn banks_imm(&self) -> FilterBanks<'_> {
+        FilterBanks {
+            start_idx: 0,
+            bank_count: self.bank_count,
+            can: self.registers(),
+        }
+    }
+
+    /// Returns the number of filter banks currently assigned to this instance.
+    ///
+    /// Chips with splittable filter banks may start out with some banks assigned to the master
+    /// instance and some assigned to the slave instance.
+    pub fn num_banks(&self) -> u8 {
+        self.bank_count
+    }
+
+    /// Disables all enabled filter banks.
+    ///
+    /// This causes all incoming frames to be disposed.
+    pub fn clear(&mut self) -> &mut Self {
+        self.banks_imm().clear();
+        self
+    }
+
+    /// Disables a filter bank.
+    ///
+    /// If `index` is out of bounds, this will panic.
+    pub fn disable_bank(&mut self, index: u8) -> &mut Self {
+        self.banks_imm().disable(index);
+        self
+    }
+
+    /// Configures a filter bank according to `config` and enables it.
+    ///
+    /// Each filter bank is associated with one of the two RX FIFOs, configured by the [`Fifo`]
+    /// passed to this function. In the event that both FIFOs are configured to accept an incoming
+    /// frame, the accepting filter bank with the lowest index wins. The FIFO state is ignored, so
+    /// if the FIFO is full, it will overflow, even if the other FIFO is also configured to accept
+    /// the frame.
+    ///
+    /// # Parameters
+    ///
+    /// - `index`: the filter index.
+    /// - `fifo`: the receive FIFO the filter should pass accepted messages to.
+    /// - `config`: the filter configuration.
+    pub fn enable_bank(
+        &mut self,
+        index: u8,
+        fifo: Fifo,
+        config: impl Into<BankConfig>,
+    ) -> &mut Self {
+        self.banks_imm().enable(index, fifo, config.into());
+        self
+    }
+}
+
+impl<I: MasterInstance> MasterFilters<'_, I> {
+    /// Sets the index at which the filter banks owned by the slave peripheral start.
+    pub fn set_split(&mut self, split_index: u8) -> &mut Self {
+        assert!(split_index <= I::NUM_FILTER_BANKS);
+        self.registers()
+            .fmr
+            .modify(|_, w| unsafe { w.can2sb().bits(split_index) });
+        self.bank_count = split_index;
+        self
+    }
+
+    /// Accesses the filters assigned to the slave peripheral.
+    pub fn slave_filters(&mut self) -> SlaveFilters<'_, I> {
+        // NB: This mutably borrows `self`, so it has full access to the filter bank registers.
+        SlaveFilters {
+            start_idx: self.bank_count,
+            bank_count: I::NUM_FILTER_BANKS - self.bank_count,
+            _can: PhantomData,
+        }
+    }
+}
+
+impl<I: FilterOwner> Drop for MasterFilters<'_, I> {
+    #[inline]
+    fn drop(&mut self) {
+        let can = self.registers();
+
+        // Leave initialization mode.
+        can.fmr.modify(|_, w| w.finit().clear_bit());
+    }
+}
+
+/// Interface to the filter banks assigned to a slave peripheral.
+pub struct SlaveFilters<'a, I: Instance> {
+    start_idx: u8,
+    bank_count: u8,
+    _can: PhantomData<&'a mut I>,
+}
+
+impl<I: Instance> SlaveFilters<'_, I> {
+    fn registers(&self) -> &RegisterBlock {
+        unsafe { &*I::REGISTERS }
+    }
+
+    fn banks_imm(&self) -> FilterBanks<'_> {
+        FilterBanks {
+            start_idx: self.start_idx,
+            bank_count: self.bank_count,
+            can: self.registers(),
+        }
+    }
+
+    /// Returns the number of filter banks currently assigned to this instance.
+    ///
+    /// Chips with splittable filter banks may start out with some banks assigned to the master
+    /// instance and some assigned to the slave instance.
+    pub fn num_banks(&self) -> u8 {
+        self.bank_count
+    }
+
+    /// Disables all enabled filter banks.
+    ///
+    /// This causes all incoming frames to be disposed.
+    pub fn clear(&mut self) -> &mut Self {
+        self.banks_imm().clear();
+        self
+    }
+
+    /// Disables a filter bank.
+    ///
+    /// If `index` is out of bounds, this will panic.
+    pub fn disable_bank(&mut self, index: u8) -> &mut Self {
+        self.banks_imm().disable(index);
+        self
+    }
+
+    /// Configures a filter bank according to `config` and enables it.
+    ///
+    /// # Parameters
+    ///
+    /// - `index`: the filter index.
+    /// - `fifo`: the receive FIFO the filter should pass accepted messages to.
+    /// - `config`: the filter configuration.
+    pub fn enable_bank(
+        &mut self,
+        index: u8,
+        fifo: Fifo,
+        config: impl Into<BankConfig>,
+    ) -> &mut Self {
+        self.banks_imm().enable(index, fifo, config.into());
+        self
+    }
+}
+
+struct FilterBanks<'a> {
+    start_idx: u8,
+    bank_count: u8,
+    can: &'a RegisterBlock,
+}
+
+impl FilterBanks<'_> {
+    fn clear(&mut self) {
+        let mask = filter_bitmask(self.start_idx, self.bank_count);
+
+        self.can.fa1r.modify(|r, w| {
+            let bits = r.bits();
+            // Clear all bits in `mask`.
+            unsafe { w.bits(bits & !mask) }
+        });
+    }
+
+    fn assert_bank_index(&self, index: u8) {
+        assert!((self.start_idx..self.start_idx + self.bank_count).contains(&index));
+    }
+
+    fn disable(&mut self, index: u8) {
+        self.assert_bank_index(index);
+
+        self.can
+            .fa1r
+            .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << index)) })
+    }
+
+    fn enable(&mut self, index: u8, fifo: Fifo, config: BankConfig) {
+        self.assert_bank_index(index);
+
+        // Configure mode.
+        let mode = matches!(config, BankConfig::List16(_) | BankConfig::List32(_));
+        self.can.fm1r.modify(|r, w| {
+            let mut bits = r.bits();
+            if mode {
+                bits |= 1 << index;
+            } else {
+                bits &= !(1 << index);
+            }
+            unsafe { w.bits(bits) }
+        });
+
+        // Configure scale.
+        let scale = matches!(config, BankConfig::List32(_) | BankConfig::Mask32(_));
+        self.can.fs1r.modify(|r, w| {
+            let mut bits = r.bits();
+            if scale {
+                bits |= 1 << index;
+            } else {
+                bits &= !(1 << index);
+            }
+            unsafe { w.bits(bits) }
+        });
+
+        // Configure filter register.
+        let (fxr1, fxr2);
+        match config {
+            BankConfig::List16([a, b, c, d]) => {
+                fxr1 = (u32::from(b.0) << 16) | u32::from(a.0);
+                fxr2 = (u32::from(d.0) << 16) | u32::from(c.0);
+            }
+            BankConfig::List32([a, b]) => {
+                fxr1 = a.0;
+                fxr2 = b.0;
+            }
+            BankConfig::Mask16([a, b]) => {
+                fxr1 = (u32::from(a.mask) << 16) | u32::from(a.id);
+                fxr2 = (u32::from(b.mask) << 16) | u32::from(b.id);
+            }
+            BankConfig::Mask32(a) => {
+                fxr1 = a.id;
+                fxr2 = a.mask;
+            }
+        };
+        let bank = &self.can.fb[usize::from(index)];
+        bank.fr1.write(|w| unsafe { w.bits(fxr1) });
+        bank.fr2.write(|w| unsafe { w.bits(fxr2) });
+
+        // Assign to the right FIFO
+        self.can.ffa1r.modify(|r, w| unsafe {
+            let mut bits = r.bits();
+            match fifo {
+                Fifo::Fifo0 => bits &= !(1 << index),
+                Fifo::Fifo1 => bits |= 1 << index,
+            }
+            w.bits(bits)
+        });
+
+        // Set active.
+        self.can
+            .fa1r
+            .modify(|r, w| unsafe { w.bits(r.bits() | (1 << index)) })
+    }
+}
+
+/// Computes a bitmask for per-filter-bank registers that only includes filters in the given range.
+fn filter_bitmask(start_idx: u8, bank_count: u8) -> u32 {
+    let count_mask = (1 << bank_count) - 1; // `bank_count` 1-bits
+    count_mask << start_idx
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_filter_bitmask() {
+        assert_eq!(filter_bitmask(0, 1), 0x1);
+        assert_eq!(filter_bitmask(1, 1), 0b10);
+        assert_eq!(filter_bitmask(0, 4), 0xf);
+        assert_eq!(filter_bitmask(1, 3), 0xe);
+        assert_eq!(filter_bitmask(8, 1), 0x100);
+        assert_eq!(filter_bitmask(8, 4), 0xf00);
+    }
+}
diff --git a/embassy-stm32/src/can/bx/frame.rs b/embassy-stm32/src/can/bx/frame.rs
new file mode 100644
index 000000000..c1089b044
--- /dev/null
+++ b/embassy-stm32/src/can/bx/frame.rs
@@ -0,0 +1,255 @@
+#[cfg(test)]
+mod tests;
+
+use core::cmp::Ordering;
+use core::ops::{Deref, DerefMut};
+
+use crate::{Id, IdReg};
+
+/// A CAN data or remote frame.
+#[derive(Clone, Debug, Eq)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub struct Frame {
+    pub(crate) id: IdReg,
+    pub(crate) data: Data,
+}
+
+impl Frame {
+    /// Creates a new data frame.
+    pub fn new_data(id: impl Into<Id>, data: impl Into<Data>) -> Self {
+        let id = match id.into() {
+            Id::Standard(id) => IdReg::new_standard(id),
+            Id::Extended(id) => IdReg::new_extended(id),
+        };
+
+        Self {
+            id,
+            data: data.into(),
+        }
+    }
+
+    /// Creates a new remote frame with configurable data length code (DLC).
+    ///
+    /// # Panics
+    ///
+    /// This function will panic if `dlc` is not inside the valid range `0..=8`.
+    pub fn new_remote(id: impl Into<Id>, dlc: u8) -> Self {
+        assert!(dlc <= 8);
+
+        let mut frame = Self::new_data(id, []);
+        // Just extend the data length, even with no data present. The API does not hand out this
+        // `Data` object.
+        frame.data.len = dlc;
+        frame.id = frame.id.with_rtr(true);
+        frame
+    }
+
+    /// Returns true if this frame is an extended frame.
+    #[inline]
+    pub fn is_extended(&self) -> bool {
+        self.id.is_extended()
+    }
+
+    /// Returns true if this frame is a standard frame.
+    #[inline]
+    pub fn is_standard(&self) -> bool {
+        self.id.is_standard()
+    }
+
+    /// Returns true if this frame is a remote frame.
+    #[inline]
+    pub fn is_remote_frame(&self) -> bool {
+        self.id.rtr()
+    }
+
+    /// Returns true if this frame is a data frame.
+    #[inline]
+    pub fn is_data_frame(&self) -> bool {
+        !self.is_remote_frame()
+    }
+
+    /// Returns the frame identifier.
+    #[inline]
+    pub fn id(&self) -> Id {
+        self.id.to_id()
+    }
+
+    /// Returns the priority of this frame.
+    #[inline]
+    pub fn priority(&self) -> FramePriority {
+        FramePriority(self.id)
+    }
+
+    /// Returns the data length code (DLC) which is in the range 0..8.
+    ///
+    /// For data frames the DLC value always matches the length of the data.
+    /// Remote frames do not carry any data, yet the DLC can be greater than 0.
+    #[inline]
+    pub fn dlc(&self) -> u8 {
+        self.data.len() as u8
+    }
+
+    /// Returns the frame data (0..8 bytes in length) if this is a data frame.
+    ///
+    /// If this is a remote frame, returns `None`.
+    pub fn data(&self) -> Option<&Data> {
+        if self.is_data_frame() {
+            Some(&self.data)
+        } else {
+            None
+        }
+    }
+}
+
+impl PartialEq for Frame {
+    fn eq(&self, other: &Self) -> bool {
+        match (self.data(), other.data()) {
+            (None, None) => self.id.eq(&other.id),
+            (Some(a), Some(b)) => self.id.eq(&other.id) && a.eq(b),
+            (None, Some(_)) | (Some(_), None) => false,
+        }
+    }
+}
+
+/// Priority of a CAN frame.
+///
+/// Returned by [`Frame::priority`].
+///
+/// The priority of a frame is determined by the bits that are part of the *arbitration field*.
+/// These consist of the frame identifier bits (including the *IDE* bit, which is 0 for extended
+/// frames and 1 for standard frames), as well as the *RTR* bit, which determines whether a frame
+/// is a data or remote frame. Lower values of the *arbitration field* have higher priority.
+///
+/// This struct wraps the *arbitration field* and implements `PartialOrd` and `Ord` accordingly,
+/// ordering higher priorities greater than lower ones.
+#[derive(Debug, Copy, Clone)]
+pub struct FramePriority(IdReg);
+
+/// Ordering is based on the Identifier and frame type (data vs. remote) and can be used to sort
+/// frames by priority.
+impl Ord for FramePriority {
+    fn cmp(&self, other: &Self) -> Ordering {
+        self.0.cmp(&other.0)
+    }
+}
+
+impl PartialOrd for FramePriority {
+    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+        Some(self.cmp(other))
+    }
+}
+
+impl PartialEq for FramePriority {
+    fn eq(&self, other: &Self) -> bool {
+        self.cmp(other) == Ordering::Equal
+    }
+}
+
+impl Eq for FramePriority {}
+
+/// Payload of a CAN data frame.
+///
+/// Contains 0 to 8 Bytes of data.
+///
+/// `Data` implements `From<[u8; N]>` for all `N` up to 8, which provides a convenient lossless
+/// conversion from fixed-length arrays.
+#[derive(Debug, Copy, Clone)]
+pub struct Data {
+    pub(crate) len: u8,
+    pub(crate) bytes: [u8; 8],
+}
+
+impl Data {
+    /// Creates a data payload from a raw byte slice.
+    ///
+    /// Returns `None` if `data` contains more than 8 Bytes (which is the maximum).
+    ///
+    /// `Data` can also be constructed from fixed-length arrays up to length 8 via `From`/`Into`.
+    pub fn new(data: &[u8]) -> Option<Self> {
+        if data.len() > 8 {
+            return None;
+        }
+
+        let mut bytes = [0; 8];
+        bytes[..data.len()].copy_from_slice(data);
+
+        Some(Self {
+            len: data.len() as u8,
+            bytes,
+        })
+    }
+
+    /// Creates an empty data payload containing 0 bytes.
+    #[inline]
+    pub const fn empty() -> Self {
+        Self {
+            len: 0,
+            bytes: [0; 8],
+        }
+    }
+}
+
+impl Deref for Data {
+    type Target = [u8];
+
+    #[inline]
+    fn deref(&self) -> &[u8] {
+        &self.bytes[..usize::from(self.len)]
+    }
+}
+
+impl DerefMut for Data {
+    #[inline]
+    fn deref_mut(&mut self) -> &mut [u8] {
+        &mut self.bytes[..usize::from(self.len)]
+    }
+}
+
+impl AsRef<[u8]> for Data {
+    #[inline]
+    fn as_ref(&self) -> &[u8] {
+        self.deref()
+    }
+}
+
+impl AsMut<[u8]> for Data {
+    #[inline]
+    fn as_mut(&mut self) -> &mut [u8] {
+        self.deref_mut()
+    }
+}
+
+impl PartialEq for Data {
+    fn eq(&self, other: &Self) -> bool {
+        self.as_ref() == other.as_ref()
+    }
+}
+
+impl Eq for Data {}
+
+#[cfg(feature = "unstable-defmt")]
+impl defmt::Format for Data {
+    fn format(&self, fmt: defmt::Formatter<'_>) {
+        self.as_ref().format(fmt)
+    }
+}
+
+macro_rules! data_from_array {
+    ( $($len:literal),+ ) => {
+        $(
+            impl From<[u8; $len]> for Data {
+                #[inline]
+                fn from(arr: [u8; $len]) -> Self {
+                    let mut bytes = [0; 8];
+                    bytes[..$len].copy_from_slice(&arr);
+                    Self {
+                        len: $len,
+                        bytes,
+                    }
+                }
+            }
+        )+
+    };
+}
+
+data_from_array!(0, 1, 2, 3, 4, 5, 6, 7, 8);
diff --git a/embassy-stm32/src/can/bx/id.rs b/embassy-stm32/src/can/bx/id.rs
new file mode 100644
index 000000000..9fdcd8319
--- /dev/null
+++ b/embassy-stm32/src/can/bx/id.rs
@@ -0,0 +1,113 @@
+//! CAN Identifiers.
+
+/// Standard 11-bit CAN Identifier (`0..=0x7FF`).
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub struct StandardId(u16);
+
+impl StandardId {
+    /// CAN ID `0`, the highest priority.
+    pub const ZERO: Self = Self(0);
+
+    /// CAN ID `0x7FF`, the lowest priority.
+    pub const MAX: Self = Self(0x7FF);
+
+    /// Tries to create a `StandardId` from a raw 16-bit integer.
+    ///
+    /// This will return `None` if `raw` is out of range of an 11-bit integer (`> 0x7FF`).
+    #[inline]
+    pub const fn new(raw: u16) -> Option<Self> {
+        if raw <= 0x7FF {
+            Some(Self(raw))
+        } else {
+            None
+        }
+    }
+
+    /// Creates a new `StandardId` without checking if it is inside the valid range.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure that `raw` is in the valid range, otherwise the behavior is
+    /// undefined.
+    #[inline]
+    pub const unsafe fn new_unchecked(raw: u16) -> Self {
+        Self(raw)
+    }
+
+    /// Returns this CAN Identifier as a raw 16-bit integer.
+    #[inline]
+    pub fn as_raw(&self) -> u16 {
+        self.0
+    }
+}
+
+/// Extended 29-bit CAN Identifier (`0..=1FFF_FFFF`).
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub struct ExtendedId(u32);
+
+impl ExtendedId {
+    /// CAN ID `0`, the highest priority.
+    pub const ZERO: Self = Self(0);
+
+    /// CAN ID `0x1FFFFFFF`, the lowest priority.
+    pub const MAX: Self = Self(0x1FFF_FFFF);
+
+    /// Tries to create a `ExtendedId` from a raw 32-bit integer.
+    ///
+    /// This will return `None` if `raw` is out of range of an 29-bit integer (`> 0x1FFF_FFFF`).
+    #[inline]
+    pub const fn new(raw: u32) -> Option<Self> {
+        if raw <= 0x1FFF_FFFF {
+            Some(Self(raw))
+        } else {
+            None
+        }
+    }
+
+    /// Creates a new `ExtendedId` without checking if it is inside the valid range.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure that `raw` is in the valid range, otherwise the behavior is
+    /// undefined.
+    #[inline]
+    pub const unsafe fn new_unchecked(raw: u32) -> Self {
+        Self(raw)
+    }
+
+    /// Returns this CAN Identifier as a raw 32-bit integer.
+    #[inline]
+    pub fn as_raw(&self) -> u32 {
+        self.0
+    }
+
+    /// Returns the Base ID part of this extended identifier.
+    pub fn standard_id(&self) -> StandardId {
+        // ID-28 to ID-18
+        StandardId((self.0 >> 18) as u16)
+    }
+}
+
+/// A CAN Identifier (standard or extended).
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub enum Id {
+    /// Standard 11-bit Identifier (`0..=0x7FF`).
+    Standard(StandardId),
+
+    /// Extended 29-bit Identifier (`0..=0x1FFF_FFFF`).
+    Extended(ExtendedId),
+}
+
+impl From<StandardId> for Id {
+    #[inline]
+    fn from(id: StandardId) -> Self {
+        Id::Standard(id)
+    }
+}
+
+impl From<ExtendedId> for Id {
+    #[inline]
+    fn from(id: ExtendedId) -> Self {
+        Id::Extended(id)
+    }
+}
diff --git a/embassy-stm32/src/can/bx/interrupt.rs b/embassy-stm32/src/can/bx/interrupt.rs
new file mode 100644
index 000000000..17aacf8e0
--- /dev/null
+++ b/embassy-stm32/src/can/bx/interrupt.rs
@@ -0,0 +1,130 @@
+//! Interrupt types.
+
+use core::ops;
+
+#[allow(unused_imports)] // for intra-doc links only
+use crate::{Can, Rx0};
+
+/// bxCAN interrupt sources.
+///
+/// These can be individually enabled and disabled in the bxCAN peripheral. Note that the bxCAN
+/// peripheral only exposes 4 interrupts to the microcontroller:
+///
+/// * TX
+/// * RX FIFO 1
+/// * RX FIFO 2
+/// * SCE (Status Change Error)
+///
+/// This means that some of the interrupts listed here will result in the same interrupt handler
+/// being invoked.
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Interrupt {
+    /// Fires the **TX** interrupt when one of the transmit mailboxes returns to empty state.
+    ///
+    /// This usually happens because its message was either transmitted successfully, or
+    /// transmission was aborted successfully.
+    ///
+    /// The interrupt handler must clear the interrupt condition by calling
+    /// [`Can::clear_request_completed_flag`] or [`Can::clear_tx_interrupt`].
+    TransmitMailboxEmpty = 1 << 0,
+
+    /// Fires the **RX FIFO 0** interrupt when FIFO 0 holds a message.
+    ///
+    /// The interrupt handler must clear the interrupt condition by receiving all messages from the
+    /// FIFO by calling [`Can::receive`] or [`Rx0::receive`].
+    Fifo0MessagePending = 1 << 1,
+
+    /// Fires the **RX FIFO 0** interrupt when FIFO 0 holds 3 incoming messages.
+    ///
+    /// The interrupt handler must clear the interrupt condition by receiving at least one message
+    /// from the FIFO (making it no longer "full"). This can be done by calling [`Can::receive`] or
+    /// [`Rx0::receive`].
+    Fifo0Full = 1 << 2,
+
+    /// Fires the **RX FIFO 0** interrupt when FIFO 0 drops an incoming message.
+    ///
+    /// The interrupt handler must clear the interrupt condition by calling [`Can::receive`] or
+    /// [`Rx0::receive`] (which will return an error).
+    Fifo0Overrun = 1 << 3,
+
+    /// Fires the **RX FIFO 1** interrupt when FIFO 1 holds a message.
+    ///
+    /// Behavior is otherwise identical to [`Self::Fifo0MessagePending`].
+    Fifo1MessagePending = 1 << 4,
+
+    /// Fires the **RX FIFO 1** interrupt when FIFO 1 holds 3 incoming messages.
+    ///
+    /// Behavior is otherwise identical to [`Self::Fifo0Full`].
+    Fifo1Full = 1 << 5,
+
+    /// Fires the **RX FIFO 1** interrupt when FIFO 1 drops an incoming message.
+    ///
+    /// Behavior is otherwise identical to [`Self::Fifo0Overrun`].
+    Fifo1Overrun = 1 << 6,
+
+    Error = 1 << 15,
+
+    /// Fires the **SCE** interrupt when an incoming CAN frame is detected while the peripheral is
+    /// in sleep mode.
+    ///
+    /// The interrupt handler must clear the interrupt condition by calling
+    /// [`Can::clear_wakeup_interrupt`].
+    Wakeup = 1 << 16,
+
+    /// Fires the **SCE** interrupt when the peripheral enters sleep mode.
+    ///
+    /// The interrupt handler must clear the interrupt condition by calling
+    /// [`Can::clear_sleep_interrupt`].
+    Sleep = 1 << 17,
+}
+
+bitflags::bitflags! {
+    /// A set of bxCAN interrupts.
+    pub struct Interrupts: u32 {
+        const TRANSMIT_MAILBOX_EMPTY = 1 << 0;
+        const FIFO0_MESSAGE_PENDING = 1 << 1;
+        const FIFO0_FULL = 1 << 2;
+        const FIFO0_OVERRUN = 1 << 3;
+        const FIFO1_MESSAGE_PENDING = 1 << 4;
+        const FIFO1_FULL = 1 << 5;
+        const FIFO1_OVERRUN = 1 << 6;
+        const ERROR = 1 << 15;
+        const WAKEUP = 1 << 16;
+        const SLEEP = 1 << 17;
+    }
+}
+
+impl From<Interrupt> for Interrupts {
+    #[inline]
+    fn from(i: Interrupt) -> Self {
+        Self::from_bits_truncate(i as u32)
+    }
+}
+
+/// Adds an interrupt to the interrupt set.
+impl ops::BitOrAssign<Interrupt> for Interrupts {
+    #[inline]
+    fn bitor_assign(&mut self, rhs: Interrupt) {
+        *self |= Self::from(rhs);
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn interrupt_flags() {
+        assert_eq!(Interrupts::from(Interrupt::Sleep), Interrupts::SLEEP);
+        assert_eq!(
+            Interrupts::from(Interrupt::TransmitMailboxEmpty),
+            Interrupts::TRANSMIT_MAILBOX_EMPTY
+        );
+
+        let mut ints = Interrupts::FIFO0_FULL;
+        ints |= Interrupt::Fifo1Full;
+        assert_eq!(ints, Interrupts::FIFO0_FULL | Interrupts::FIFO1_FULL);
+    }
+}
diff --git a/embassy-stm32/src/can/bx/mod.rs b/embassy-stm32/src/can/bx/mod.rs
new file mode 100644
index 000000000..3cfc09c85
--- /dev/null
+++ b/embassy-stm32/src/can/bx/mod.rs
@@ -0,0 +1,1100 @@
+//! Driver for the STM32 bxCAN peripheral.
+//!
+//! This crate provides a reusable driver for the bxCAN peripheral found in many low- to middle-end
+//! STM32 microcontrollers. HALs for compatible chips can reexport this crate and implement its
+//! traits to easily expose a featureful CAN driver.
+//!
+//! # Features
+//!
+//! - Supports both single- and dual-peripheral configurations (where one bxCAN instance manages the
+//!   filters of a secondary instance).
+//! - Handles standard and extended frames, and data and remote frames.
+//! - Support for interrupts emitted by the bxCAN peripheral.
+//! - Transmission respects CAN IDs and protects against priority inversion (a lower-priority frame
+//!   may be dequeued when enqueueing a higher-priority one).
+//! - Implements the [`embedded-hal`] traits for interoperability.
+//! - Support for both RX FIFOs (as [`Rx0`] and [`Rx1`]).
+//!
+//! # Limitations
+//!
+//! - Support for querying error states and handling error interrupts is incomplete.
+//!
+//! # Cargo Features
+//!
+//! | Feature | Description |
+//! |---------|-------------|
+//! | `unstable-defmt` | Implements [`defmt`]'s `Format` trait for the types in this crate.[^1] |
+//!
+//! [^1]: The specific version of defmt is unspecified and may be updated in a patch release.
+//!
+//! [`defmt`]: https://docs.rs/defmt
+//! [`embedded-hal`]: https://docs.rs/embedded-hal
+
+#![doc(html_root_url = "https://docs.rs/bxcan/0.7.0")]
+// Deny a few warnings in doctests, since rustdoc `allow`s many warnings by default
+#![doc(test(attr(deny(unused_imports, unused_must_use))))]
+#![no_std]
+#![allow(clippy::unnecessary_operation)] // lint is bugged
+
+mod embedded_hal;
+pub mod filter;
+mod frame;
+mod id;
+mod interrupt;
+
+#[allow(clippy::all)] // generated code
+mod pac;
+
+pub use id::{ExtendedId, Id, StandardId};
+
+pub use crate::frame::{Data, Frame, FramePriority};
+pub use crate::interrupt::{Interrupt, Interrupts};
+pub use crate::pac::can::RegisterBlock;
+
+use crate::filter::MasterFilters;
+use core::cmp::{Ord, Ordering};
+use core::convert::{Infallible, TryInto};
+use core::marker::PhantomData;
+use core::mem;
+use core::ptr::NonNull;
+
+use self::pac::generic::*; // To make the PAC extraction build
+
+/// A bxCAN peripheral instance.
+///
+/// This trait is meant to be implemented for a HAL-specific type that represent ownership of
+/// the CAN peripheral (and any pins required by it, although that is entirely up to the HAL).
+///
+/// # Safety
+///
+/// It is only safe to implement this trait, when:
+///
+/// * The implementing type has ownership of the peripheral, preventing any other accesses to the
+///   register block.
+/// * `REGISTERS` is a pointer to that peripheral's register block and can be safely accessed for as
+///   long as ownership or a borrow of the implementing type is present.
+pub unsafe trait Instance {
+    /// Pointer to the instance's register block.
+    const REGISTERS: *mut RegisterBlock;
+}
+
+/// A bxCAN instance that owns filter banks.
+///
+/// In master-slave-instance setups, only the master instance owns the filter banks, and needs to
+/// split some of them off for use by the slave instance. In that case, the master instance should
+/// implement [`FilterOwner`] and [`MasterInstance`], while the slave instance should only implement
+/// [`Instance`].
+///
+/// In single-instance configurations, the instance owns all filter banks and they can not be split
+/// off. In that case, the instance should implement [`Instance`] and [`FilterOwner`].
+///
+/// # Safety
+///
+/// This trait must only be implemented if the instance does, in fact, own its associated filter
+/// banks, and `NUM_FILTER_BANKS` must be correct.
+pub unsafe trait FilterOwner: Instance {
+    /// The total number of filter banks available to the instance.
+    ///
+    /// This is usually either 14 or 28, and should be specified in the chip's reference manual or
+    /// datasheet.
+    const NUM_FILTER_BANKS: u8;
+}
+
+/// A bxCAN master instance that shares filter banks with a slave instance.
+///
+/// In master-slave-instance setups, this trait should be implemented for the master instance.
+///
+/// # Safety
+///
+/// This trait must only be implemented when there is actually an associated slave instance.
+pub unsafe trait MasterInstance: FilterOwner {}
+
+// TODO: what to do with these?
+/*
+#[derive(Debug, Copy, Clone, Eq, PartialEq, Format)]
+pub enum Error {
+    Stuff,
+    Form,
+    Acknowledgement,
+    BitRecessive,
+    BitDominant,
+    Crc,
+    Software,
+}*/
+
+/// Error that indicates that an incoming message has been lost due to buffer overrun.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub struct OverrunError {
+    _priv: (),
+}
+
+/// Identifier of a CAN message.
+///
+/// Can be either a standard identifier (11bit, Range: 0..0x3FF) or a
+/// extendended identifier (29bit , Range: 0..0x1FFFFFFF).
+///
+/// The `Ord` trait can be used to determine the frame’s priority this ID
+/// belongs to.
+/// Lower identifier values have a higher priority. Additionally standard frames
+/// have a higher priority than extended frames and data frames have a higher
+/// priority than remote frames.
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+struct IdReg(u32);
+
+impl IdReg {
+    const STANDARD_SHIFT: u32 = 21;
+
+    const EXTENDED_SHIFT: u32 = 3;
+
+    const IDE_MASK: u32 = 0x0000_0004;
+
+    const RTR_MASK: u32 = 0x0000_0002;
+
+    /// Creates a new standard identifier (11bit, Range: 0..0x7FF)
+    ///
+    /// Panics for IDs outside the allowed range.
+    fn new_standard(id: StandardId) -> Self {
+        Self(u32::from(id.as_raw()) << Self::STANDARD_SHIFT)
+    }
+
+    /// Creates a new extendended identifier (29bit , Range: 0..0x1FFFFFFF).
+    ///
+    /// Panics for IDs outside the allowed range.
+    fn new_extended(id: ExtendedId) -> IdReg {
+        Self(id.as_raw() << Self::EXTENDED_SHIFT | Self::IDE_MASK)
+    }
+
+    fn from_register(reg: u32) -> IdReg {
+        Self(reg & 0xFFFF_FFFE)
+    }
+
+    /// Sets the remote transmission (RTR) flag. This marks the identifier as
+    /// being part of a remote frame.
+    #[must_use = "returns a new IdReg without modifying `self`"]
+    fn with_rtr(self, rtr: bool) -> IdReg {
+        if rtr {
+            Self(self.0 | Self::RTR_MASK)
+        } else {
+            Self(self.0 & !Self::RTR_MASK)
+        }
+    }
+
+    /// Returns the identifier.
+    fn to_id(self) -> Id {
+        if self.is_extended() {
+            Id::Extended(unsafe { ExtendedId::new_unchecked(self.0 >> Self::EXTENDED_SHIFT) })
+        } else {
+            Id::Standard(unsafe {
+                StandardId::new_unchecked((self.0 >> Self::STANDARD_SHIFT) as u16)
+            })
+        }
+    }
+
+    /// Returns `true` if the identifier is an extended identifier.
+    fn is_extended(self) -> bool {
+        self.0 & Self::IDE_MASK != 0
+    }
+
+    /// Returns `true` if the identifier is a standard identifier.
+    fn is_standard(self) -> bool {
+        !self.is_extended()
+    }
+
+    /// Returns `true` if the identifer is part of a remote frame (RTR bit set).
+    fn rtr(self) -> bool {
+        self.0 & Self::RTR_MASK != 0
+    }
+}
+
+/// `IdReg` is ordered by priority.
+impl Ord for IdReg {
+    fn cmp(&self, other: &Self) -> Ordering {
+        // When the IDs match, data frames have priority over remote frames.
+        let rtr = self.rtr().cmp(&other.rtr()).reverse();
+
+        let id_a = self.to_id();
+        let id_b = other.to_id();
+        match (id_a, id_b) {
+            (Id::Standard(a), Id::Standard(b)) => {
+                // Lower IDs have priority over higher IDs.
+                a.as_raw().cmp(&b.as_raw()).reverse().then(rtr)
+            }
+            (Id::Extended(a), Id::Extended(b)) => a.as_raw().cmp(&b.as_raw()).reverse().then(rtr),
+            (Id::Standard(a), Id::Extended(b)) => {
+                // Standard frames have priority over extended frames if their Base IDs match.
+                a.as_raw()
+                    .cmp(&b.standard_id().as_raw())
+                    .reverse()
+                    .then(Ordering::Greater)
+            }
+            (Id::Extended(a), Id::Standard(b)) => a
+                .standard_id()
+                .as_raw()
+                .cmp(&b.as_raw())
+                .reverse()
+                .then(Ordering::Less),
+        }
+    }
+}
+
+impl PartialOrd for IdReg {
+    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+        Some(self.cmp(other))
+    }
+}
+
+/// Configuration proxy returned by [`Can::modify_config`].
+#[must_use = "`CanConfig` leaves the peripheral in uninitialized state, call `CanConfig::enable` or explicitly drop the value"]
+pub struct CanConfig<'a, I: Instance> {
+    can: &'a mut Can<I>,
+}
+
+impl<I: Instance> CanConfig<'_, I> {
+    /// Configures the bit timings.
+    ///
+    /// You can use <http://www.bittiming.can-wiki.info/> to calculate the `btr` parameter. Enter
+    /// parameters as follows:
+    ///
+    /// - *Clock Rate*: The input clock speed to the CAN peripheral (*not* the CPU clock speed).
+    ///   This is the clock rate of the peripheral bus the CAN peripheral is attached to (eg. APB1).
+    /// - *Sample Point*: Should normally be left at the default value of 87.5%.
+    /// - *SJW*: Should normally be left at the default value of 1.
+    ///
+    /// Then copy the `CAN_BUS_TIME` register value from the table and pass it as the `btr`
+    /// parameter to this method.
+    pub fn set_bit_timing(self, btr: u32) -> Self {
+        self.can.set_bit_timing(btr);
+        self
+    }
+
+    /// Enables or disables loopback mode: Internally connects the TX and RX
+    /// signals together.
+    pub fn set_loopback(self, enabled: bool) -> Self {
+        let can = self.can.registers();
+        can.btr.modify(|_, w| w.lbkm().bit(enabled));
+        self
+    }
+
+    /// Enables or disables silent mode: Disconnects the TX signal from the pin.
+    pub fn set_silent(self, enabled: bool) -> Self {
+        let can = self.can.registers();
+        can.btr.modify(|_, w| w.silm().bit(enabled));
+        self
+    }
+
+    /// Enables or disables automatic retransmission of messages.
+    ///
+    /// If this is enabled, the CAN peripheral will automatically try to retransmit each frame
+    /// until it can be sent. Otherwise, it will try only once to send each frame.
+    ///
+    /// Automatic retransmission is enabled by default.
+    pub fn set_automatic_retransmit(self, enabled: bool) -> Self {
+        let can = self.can.registers();
+        can.mcr.modify(|_, w| w.nart().bit(!enabled));
+        self
+    }
+
+    /// Leaves initialization mode and enables the peripheral.
+    ///
+    /// To sync with the CAN bus, this will block until 11 consecutive recessive bits are detected
+    /// on the bus.
+    ///
+    /// If you want to finish configuration without enabling the peripheral, you can call
+    /// [`CanConfig::leave_disabled`] or [`drop`] the [`CanConfig`] instead.
+    pub fn enable(mut self) {
+        self.leave_init_mode();
+
+        match nb::block!(self.can.enable_non_blocking()) {
+            Ok(()) => {}
+            Err(void) => match void {},
+        }
+
+        // Don't run the destructor.
+        mem::forget(self);
+    }
+
+    /// Leaves initialization mode, but keeps the peripheral in sleep mode.
+    ///
+    /// Before the [`Can`] instance can be used, you have to enable it by calling
+    /// [`Can::enable_non_blocking`].
+    pub fn leave_disabled(mut self) {
+        self.leave_init_mode();
+    }
+
+    /// Leaves initialization mode, enters sleep mode.
+    fn leave_init_mode(&mut self) {
+        let can = self.can.registers();
+        can.mcr
+            .modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
+        loop {
+            let msr = can.msr.read();
+            if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
+                break;
+            }
+        }
+    }
+}
+
+impl<I: Instance> Drop for CanConfig<'_, I> {
+    #[inline]
+    fn drop(&mut self) {
+        self.leave_init_mode();
+    }
+}
+
+/// Builder returned by [`Can::builder`].
+#[must_use = "`CanBuilder` leaves the peripheral in uninitialized state, call `CanBuilder::enable` or `CanBuilder::leave_disabled`"]
+pub struct CanBuilder<I: Instance> {
+    can: Can<I>,
+}
+
+impl<I: Instance> CanBuilder<I> {
+    /// Configures the bit timings.
+    ///
+    /// You can use <http://www.bittiming.can-wiki.info/> to calculate the `btr` parameter. Enter
+    /// parameters as follows:
+    ///
+    /// - *Clock Rate*: The input clock speed to the CAN peripheral (*not* the CPU clock speed).
+    ///   This is the clock rate of the peripheral bus the CAN peripheral is attached to (eg. APB1).
+    /// - *Sample Point*: Should normally be left at the default value of 87.5%.
+    /// - *SJW*: Should normally be left at the default value of 1.
+    ///
+    /// Then copy the `CAN_BUS_TIME` register value from the table and pass it as the `btr`
+    /// parameter to this method.
+    pub fn set_bit_timing(mut self, btr: u32) -> Self {
+        self.can.set_bit_timing(btr);
+        self
+    }
+
+    /// Enables or disables loopback mode: Internally connects the TX and RX
+    /// signals together.
+    pub fn set_loopback(self, enabled: bool) -> Self {
+        let can = self.can.registers();
+        can.btr.modify(|_, w| w.lbkm().bit(enabled));
+        self
+    }
+
+    /// Enables or disables silent mode: Disconnects the TX signal from the pin.
+    pub fn set_silent(self, enabled: bool) -> Self {
+        let can = self.can.registers();
+        can.btr.modify(|_, w| w.silm().bit(enabled));
+        self
+    }
+
+    /// Enables or disables automatic retransmission of messages.
+    ///
+    /// If this is enabled, the CAN peripheral will automatically try to retransmit each frame
+    /// until it can be sent. Otherwise, it will try only once to send each frame.
+    ///
+    /// Automatic retransmission is enabled by default.
+    pub fn set_automatic_retransmit(self, enabled: bool) -> Self {
+        let can = self.can.registers();
+        can.mcr.modify(|_, w| w.nart().bit(!enabled));
+        self
+    }
+
+    /// Leaves initialization mode and enables the peripheral.
+    ///
+    /// To sync with the CAN bus, this will block until 11 consecutive recessive bits are detected
+    /// on the bus.
+    ///
+    /// If you want to finish configuration without enabling the peripheral, you can call
+    /// [`CanBuilder::leave_disabled`] instead.
+    pub fn enable(mut self) -> Can<I> {
+        self.leave_init_mode();
+
+        match nb::block!(self.can.enable_non_blocking()) {
+            Ok(()) => self.can,
+            Err(void) => match void {},
+        }
+    }
+
+    /// Returns the [`Can`] interface without enabling it.
+    ///
+    /// This leaves initialization mode, but keeps the peripheral in sleep mode instead of enabling
+    /// it.
+    ///
+    /// Before the [`Can`] instance can be used, you have to enable it by calling
+    /// [`Can::enable_non_blocking`].
+    pub fn leave_disabled(mut self) -> Can<I> {
+        self.leave_init_mode();
+        self.can
+    }
+
+    /// Leaves initialization mode, enters sleep mode.
+    fn leave_init_mode(&mut self) {
+        let can = self.can.registers();
+        can.mcr
+            .modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
+        loop {
+            let msr = can.msr.read();
+            if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
+                break;
+            }
+        }
+    }
+}
+
+/// Interface to a bxCAN peripheral.
+pub struct Can<I: Instance> {
+    instance: I,
+}
+
+impl<I> Can<I>
+where
+    I: Instance,
+{
+    /// Creates a [`CanBuilder`] for constructing a CAN interface.
+    pub fn builder(instance: I) -> CanBuilder<I> {
+        let can_builder = CanBuilder {
+            can: Can { instance },
+        };
+
+        let can_reg = can_builder.can.registers();
+        // Enter init mode.
+        can_reg
+            .mcr
+            .modify(|_, w| w.sleep().clear_bit().inrq().set_bit());
+        loop {
+            let msr = can_reg.msr.read();
+            if msr.slak().bit_is_clear() && msr.inak().bit_is_set() {
+                break;
+            }
+        }
+
+        can_builder
+    }
+
+    fn registers(&self) -> &RegisterBlock {
+        unsafe { &*I::REGISTERS }
+    }
+
+    fn set_bit_timing(&mut self, btr: u32) {
+        // Mask of all non-reserved BTR bits, except the mode flags.
+        const MASK: u32 = 0x037F_03FF;
+
+        let can = self.registers();
+        can.btr.modify(|r, w| unsafe {
+            let mode_bits = r.bits() & 0xC000_0000;
+            w.bits(mode_bits | (btr & MASK))
+        });
+    }
+
+    /// Returns a reference to the peripheral instance.
+    ///
+    /// This allows accessing HAL-specific data stored in the instance type.
+    pub fn instance(&mut self) -> &mut I {
+        &mut self.instance
+    }
+
+    /// Disables the CAN interface and returns back the raw peripheral it was created from.
+    ///
+    /// The peripheral is disabled by setting `RESET` in `CAN_MCR`, which causes the peripheral to
+    /// enter sleep mode.
+    pub fn free(self) -> I {
+        self.registers().mcr.write(|w| w.reset().set_bit());
+        self.instance
+    }
+
+    /// Configure bit timings and silent/loop-back mode.
+    ///
+    /// Calling this method will enter initialization mode.
+    pub fn modify_config(&mut self) -> CanConfig<'_, I> {
+        let can = self.registers();
+
+        // Enter init mode.
+        can.mcr
+            .modify(|_, w| w.sleep().clear_bit().inrq().set_bit());
+        loop {
+            let msr = can.msr.read();
+            if msr.slak().bit_is_clear() && msr.inak().bit_is_set() {
+                break;
+            }
+        }
+
+        CanConfig { can: self }
+    }
+
+    /// Configures the automatic wake-up feature.
+    ///
+    /// This is turned off by default.
+    ///
+    /// When turned on, an incoming frame will cause the peripheral to wake up from sleep and
+    /// receive the frame. If enabled, [`Interrupt::Wakeup`] will also be triggered by the incoming
+    /// frame.
+    pub fn set_automatic_wakeup(&mut self, enabled: bool) {
+        let can = self.registers();
+        can.mcr.modify(|_, w| w.awum().bit(enabled));
+    }
+
+    /// Leaves initialization mode and enables the peripheral (non-blocking version).
+    ///
+    /// Usually, it is recommended to call [`CanConfig::enable`] instead. This method is only needed
+    /// if you want non-blocking initialization.
+    ///
+    /// If this returns [`WouldBlock`][nb::Error::WouldBlock], the peripheral will enable itself
+    /// in the background. The peripheral is enabled and ready to use when this method returns
+    /// successfully.
+    pub fn enable_non_blocking(&mut self) -> nb::Result<(), Infallible> {
+        let can = self.registers();
+        let msr = can.msr.read();
+        if msr.slak().bit_is_set() {
+            can.mcr
+                .modify(|_, w| w.abom().set_bit().sleep().clear_bit());
+            Err(nb::Error::WouldBlock)
+        } else {
+            Ok(())
+        }
+    }
+
+    /// Puts the peripheral in a sleep mode to save power.
+    ///
+    /// While in sleep mode, an incoming CAN frame will trigger [`Interrupt::Wakeup`] if enabled.
+    pub fn sleep(&mut self) {
+        let can = self.registers();
+        can.mcr
+            .modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
+        loop {
+            let msr = can.msr.read();
+            if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
+                break;
+            }
+        }
+    }
+
+    /// Wakes up from sleep mode.
+    ///
+    /// Note that this will not trigger [`Interrupt::Wakeup`], only reception of an incoming CAN
+    /// frame will cause that interrupt.
+    pub fn wakeup(&mut self) {
+        let can = self.registers();
+        can.mcr
+            .modify(|_, w| w.sleep().clear_bit().inrq().clear_bit());
+        loop {
+            let msr = can.msr.read();
+            if msr.slak().bit_is_clear() && msr.inak().bit_is_clear() {
+                break;
+            }
+        }
+    }
+
+    /// Starts listening for a CAN interrupt.
+    pub fn enable_interrupt(&mut self, interrupt: Interrupt) {
+        self.enable_interrupts(Interrupts::from_bits_truncate(interrupt as u32))
+    }
+
+    /// Starts listening for a set of CAN interrupts.
+    pub fn enable_interrupts(&mut self, interrupts: Interrupts) {
+        self.registers()
+            .ier
+            .modify(|r, w| unsafe { w.bits(r.bits() | interrupts.bits()) })
+    }
+
+    /// Stops listening for a CAN interrupt.
+    pub fn disable_interrupt(&mut self, interrupt: Interrupt) {
+        self.disable_interrupts(Interrupts::from_bits_truncate(interrupt as u32))
+    }
+
+    /// Stops listening for a set of CAN interrupts.
+    pub fn disable_interrupts(&mut self, interrupts: Interrupts) {
+        self.registers()
+            .ier
+            .modify(|r, w| unsafe { w.bits(r.bits() & !interrupts.bits()) })
+    }
+
+    /// Clears the pending flag of [`Interrupt::Sleep`].
+    pub fn clear_sleep_interrupt(&self) {
+        let can = self.registers();
+        // Read-only register with write-1-to-clear, so `&self` is sufficient.
+        can.msr.write(|w| w.slaki().set_bit());
+    }
+
+    /// Clears the pending flag of [`Interrupt::Wakeup`].
+    pub fn clear_wakeup_interrupt(&self) {
+        let can = self.registers();
+        // Read-only register with write-1-to-clear, so `&self` is sufficient.
+        can.msr.write(|w| w.wkui().set_bit());
+    }
+
+    /// Clears the "Request Completed" (RQCP) flag of a transmit mailbox.
+    ///
+    /// Returns the [`Mailbox`] whose flag was cleared. If no mailbox has the flag set, returns
+    /// `None`.
+    ///
+    /// Once this function returns `None`, a pending [`Interrupt::TransmitMailboxEmpty`] is
+    /// considered acknowledged.
+    pub fn clear_request_completed_flag(&mut self) -> Option<Mailbox> {
+        let can = self.registers();
+        let tsr = can.tsr.read();
+        if tsr.rqcp0().bit_is_set() {
+            can.tsr.modify(|_, w| w.rqcp0().set_bit());
+            Some(Mailbox::Mailbox0)
+        } else if tsr.rqcp1().bit_is_set() {
+            can.tsr.modify(|_, w| w.rqcp1().set_bit());
+            Some(Mailbox::Mailbox1)
+        } else if tsr.rqcp2().bit_is_set() {
+            can.tsr.modify(|_, w| w.rqcp2().set_bit());
+            Some(Mailbox::Mailbox2)
+        } else {
+            None
+        }
+    }
+
+    /// Clears a pending TX interrupt ([`Interrupt::TransmitMailboxEmpty`]).
+    ///
+    /// This does not return the mailboxes that have finished tranmission. If you need that
+    /// information, call [`Can::clear_request_completed_flag`] instead.
+    pub fn clear_tx_interrupt(&mut self) {
+        while self.clear_request_completed_flag().is_some() {}
+    }
+
+    /// Puts a CAN frame in a free transmit mailbox for transmission on the bus.
+    ///
+    /// Frames are transmitted to the bus based on their priority (see [`FramePriority`]).
+    /// Transmit order is preserved for frames with identical priority.
+    ///
+    /// If all transmit mailboxes are full, and `frame` has a higher priority than the
+    /// lowest-priority message in the transmit mailboxes, transmission of the enqueued frame is
+    /// cancelled and `frame` is enqueued instead. The frame that was replaced is returned as
+    /// [`TransmitStatus::dequeued_frame`].
+    pub fn transmit(&mut self, frame: &Frame) -> nb::Result<TransmitStatus, Infallible> {
+        // Safety: We have a `&mut self` and have unique access to the peripheral.
+        unsafe { Tx::<I>::conjure().transmit(frame) }
+    }
+
+    /// Returns `true` if no frame is pending for transmission.
+    pub fn is_transmitter_idle(&self) -> bool {
+        // Safety: Read-only operation.
+        unsafe { Tx::<I>::conjure().is_idle() }
+    }
+
+    /// Attempts to abort the sending of a frame that is pending in a mailbox.
+    ///
+    /// If there is no frame in the provided mailbox, or its transmission succeeds before it can be
+    /// aborted, this function has no effect and returns `false`.
+    ///
+    /// If there is a frame in the provided mailbox, and it is canceled successfully, this function
+    /// returns `true`.
+    pub fn abort(&mut self, mailbox: Mailbox) -> bool {
+        // Safety: We have a `&mut self` and have unique access to the peripheral.
+        unsafe { Tx::<I>::conjure().abort(mailbox) }
+    }
+
+    /// Returns a received frame if available.
+    ///
+    /// This will first check FIFO 0 for a message or error. If none are available, FIFO 1 is
+    /// checked.
+    ///
+    /// Returns `Err` when a frame was lost due to buffer overrun.
+    pub fn receive(&mut self) -> nb::Result<Frame, OverrunError> {
+        // Safety: We have a `&mut self` and have unique access to the peripheral.
+        let mut rx0 = unsafe { Rx0::<I>::conjure() };
+        let mut rx1 = unsafe { Rx1::<I>::conjure() };
+
+        match rx0.receive() {
+            Err(nb::Error::WouldBlock) => rx1.receive(),
+            result => result,
+        }
+    }
+
+    /// Returns a reference to the RX FIFO 0.
+    pub fn rx0(&mut self) -> &mut Rx0<I> {
+        // Safety: We take `&mut self` and the return value lifetimes are tied to `self`'s lifetime.
+        unsafe { Rx0::conjure_by_ref() }
+    }
+
+    /// Returns a reference to the RX FIFO 1.
+    pub fn rx1(&mut self) -> &mut Rx1<I> {
+        // Safety: We take `&mut self` and the return value lifetimes are tied to `self`'s lifetime.
+        unsafe { Rx1::conjure_by_ref() }
+    }
+
+    /// Splits this `Can` instance into transmitting and receiving halves, by reference.
+    pub fn split_by_ref(&mut self) -> (&mut Tx<I>, &mut Rx0<I>, &mut Rx1<I>) {
+        // Safety: We take `&mut self` and the return value lifetimes are tied to `self`'s lifetime.
+        let tx = unsafe { Tx::conjure_by_ref() };
+        let rx0 = unsafe { Rx0::conjure_by_ref() };
+        let rx1 = unsafe { Rx1::conjure_by_ref() };
+        (tx, rx0, rx1)
+    }
+
+    /// Consumes this `Can` instance and splits it into transmitting and receiving halves.
+    pub fn split(self) -> (Tx<I>, Rx0<I>, Rx1<I>) {
+        // Safety: `Self` is not `Copy` and is destroyed by moving it into this method.
+        unsafe { (Tx::conjure(), Rx0::conjure(), Rx1::conjure()) }
+    }
+}
+
+impl<I: FilterOwner> Can<I> {
+    /// Accesses the filter banks owned by this CAN peripheral.
+    ///
+    /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
+    /// peripheral instead.
+    pub fn modify_filters(&mut self) -> MasterFilters<'_, I> {
+        unsafe { MasterFilters::new() }
+    }
+}
+
+/// Interface to the CAN transmitter part.
+pub struct Tx<I> {
+    _can: PhantomData<I>,
+}
+
+#[inline]
+const fn ok_mask(idx: usize) -> u32 {
+    0x02 << (8 * idx)
+}
+
+#[inline]
+const fn abort_mask(idx: usize) -> u32 {
+    0x80 << (8 * idx)
+}
+
+impl<I> Tx<I>
+where
+    I: Instance,
+{
+    unsafe fn conjure() -> Self {
+        Self { _can: PhantomData }
+    }
+
+    /// Creates a `&mut Self` out of thin air.
+    ///
+    /// This is only safe if it is the only way to access a `Tx<I>`.
+    unsafe fn conjure_by_ref<'a>() -> &'a mut Self {
+        // Cause out of bounds access when `Self` is not zero-sized.
+        [()][core::mem::size_of::<Self>()];
+
+        // Any aligned pointer is valid for ZSTs.
+        &mut *NonNull::dangling().as_ptr()
+    }
+
+    fn registers(&self) -> &RegisterBlock {
+        unsafe { &*I::REGISTERS }
+    }
+
+    /// Puts a CAN frame in a transmit mailbox for transmission on the bus.
+    ///
+    /// Frames are transmitted to the bus based on their priority (see [`FramePriority`]).
+    /// Transmit order is preserved for frames with identical priority.
+    ///
+    /// If all transmit mailboxes are full, and `frame` has a higher priority than the
+    /// lowest-priority message in the transmit mailboxes, transmission of the enqueued frame is
+    /// cancelled and `frame` is enqueued instead. The frame that was replaced is returned as
+    /// [`TransmitStatus::dequeued_frame`].
+    pub fn transmit(&mut self, frame: &Frame) -> nb::Result<TransmitStatus, Infallible> {
+        let can = self.registers();
+
+        // Get the index of the next free mailbox or the one with the lowest priority.
+        let tsr = can.tsr.read();
+        let idx = tsr.code().bits() as usize;
+
+        let frame_is_pending =
+            tsr.tme0().bit_is_clear() || tsr.tme1().bit_is_clear() || tsr.tme2().bit_is_clear();
+        let pending_frame = if frame_is_pending {
+            // High priority frames are transmitted first by the mailbox system.
+            // Frames with identical identifier shall be transmitted in FIFO order.
+            // The controller schedules pending frames of same priority based on the
+            // mailbox index instead. As a workaround check all pending mailboxes
+            // and only accept higher priority frames.
+            self.check_priority(0, frame.id)?;
+            self.check_priority(1, frame.id)?;
+            self.check_priority(2, frame.id)?;
+
+            let all_frames_are_pending =
+                tsr.tme0().bit_is_clear() && tsr.tme1().bit_is_clear() && tsr.tme2().bit_is_clear();
+            if all_frames_are_pending {
+                // No free mailbox is available. This can only happen when three frames with
+                // ascending priority (descending IDs) were requested for transmission and all
+                // of them are blocked by bus traffic with even higher priority.
+                // To prevent a priority inversion abort and replace the lowest priority frame.
+                self.read_pending_mailbox(idx)
+            } else {
+                // There was a free mailbox.
+                None
+            }
+        } else {
+            // All mailboxes are available: Send frame without performing any checks.
+            None
+        };
+
+        self.write_mailbox(idx, frame);
+
+        let mailbox = match idx {
+            0 => Mailbox::Mailbox0,
+            1 => Mailbox::Mailbox1,
+            2 => Mailbox::Mailbox2,
+            _ => unreachable!(),
+        };
+        Ok(TransmitStatus {
+            dequeued_frame: pending_frame,
+            mailbox,
+        })
+    }
+
+    /// Returns `Ok` when the mailbox is free or if it contains pending frame with a
+    /// lower priority (higher ID) than the identifier `id`.
+    fn check_priority(&self, idx: usize, id: IdReg) -> nb::Result<(), Infallible> {
+        let can = self.registers();
+
+        // Read the pending frame's id to check its priority.
+        assert!(idx < 3);
+        let tir = &can.tx[idx].tir.read();
+
+        // Check the priority by comparing the identifiers. But first make sure the
+        // frame has not finished the transmission (`TXRQ` == 0) in the meantime.
+        if tir.txrq().bit_is_set() && id <= IdReg::from_register(tir.bits()) {
+            // There's a mailbox whose priority is higher or equal
+            // the priority of the new frame.
+            return Err(nb::Error::WouldBlock);
+        }
+
+        Ok(())
+    }
+
+    fn write_mailbox(&mut self, idx: usize, frame: &Frame) {
+        let can = self.registers();
+
+        debug_assert!(idx < 3);
+        let mb = unsafe { &can.tx.get_unchecked(idx) };
+
+        mb.tdtr
+            .write(|w| unsafe { w.dlc().bits(frame.dlc() as u8) });
+        mb.tdlr.write(|w| unsafe {
+            w.bits(u32::from_ne_bytes(
+                frame.data.bytes[0..4].try_into().unwrap(),
+            ))
+        });
+        mb.tdhr.write(|w| unsafe {
+            w.bits(u32::from_ne_bytes(
+                frame.data.bytes[4..8].try_into().unwrap(),
+            ))
+        });
+        mb.tir
+            .write(|w| unsafe { w.bits(frame.id.0).txrq().set_bit() });
+    }
+
+    fn read_pending_mailbox(&mut self, idx: usize) -> Option<Frame> {
+        if self.abort_by_index(idx) {
+            let can = self.registers();
+            debug_assert!(idx < 3);
+            let mb = unsafe { &can.tx.get_unchecked(idx) };
+
+            // Read back the pending frame.
+            let mut pending_frame = Frame {
+                id: IdReg(mb.tir.read().bits()),
+                data: Data::empty(),
+            };
+            pending_frame.data.bytes[0..4].copy_from_slice(&mb.tdlr.read().bits().to_ne_bytes());
+            pending_frame.data.bytes[4..8].copy_from_slice(&mb.tdhr.read().bits().to_ne_bytes());
+            pending_frame.data.len = mb.tdtr.read().dlc().bits();
+
+            Some(pending_frame)
+        } else {
+            // Abort request failed because the frame was already sent (or being sent) on
+            // the bus. All mailboxes are now free. This can happen for small prescaler
+            // values (e.g. 1MBit/s bit timing with a source clock of 8MHz) or when an ISR
+            // has preempted the execution.
+            None
+        }
+    }
+
+    /// Tries to abort a pending frame. Returns `true` when aborted.
+    fn abort_by_index(&mut self, idx: usize) -> bool {
+        let can = self.registers();
+
+        can.tsr.write(|w| unsafe { w.bits(abort_mask(idx)) });
+
+        // Wait for the abort request to be finished.
+        loop {
+            let tsr = can.tsr.read().bits();
+            if tsr & abort_mask(idx) == 0 {
+                break tsr & ok_mask(idx) == 0;
+            }
+        }
+    }
+
+    /// Attempts to abort the sending of a frame that is pending in a mailbox.
+    ///
+    /// If there is no frame in the provided mailbox, or its transmission succeeds before it can be
+    /// aborted, this function has no effect and returns `false`.
+    ///
+    /// If there is a frame in the provided mailbox, and it is canceled successfully, this function
+    /// returns `true`.
+    pub fn abort(&mut self, mailbox: Mailbox) -> bool {
+        // If the mailbox is empty, the value of TXOKx depends on what happened with the previous
+        // frame in that mailbox. Only call abort_by_index() if the mailbox is not empty.
+        let tsr = self.registers().tsr.read();
+        let mailbox_empty = match mailbox {
+            Mailbox::Mailbox0 => tsr.tme0().bit_is_set(),
+            Mailbox::Mailbox1 => tsr.tme1().bit_is_set(),
+            Mailbox::Mailbox2 => tsr.tme2().bit_is_set(),
+        };
+        if mailbox_empty {
+            false
+        } else {
+            self.abort_by_index(mailbox as usize)
+        }
+    }
+
+    /// Returns `true` if no frame is pending for transmission.
+    pub fn is_idle(&self) -> bool {
+        let can = self.registers();
+        let tsr = can.tsr.read();
+        tsr.tme0().bit_is_set() && tsr.tme1().bit_is_set() && tsr.tme2().bit_is_set()
+    }
+
+    /// Clears the request complete flag for all mailboxes.
+    pub fn clear_interrupt_flags(&mut self) {
+        let can = self.registers();
+        can.tsr
+            .write(|w| w.rqcp2().set_bit().rqcp1().set_bit().rqcp0().set_bit());
+    }
+}
+
+/// Interface to receiver FIFO 0.
+pub struct Rx0<I> {
+    _can: PhantomData<I>,
+}
+
+impl<I> Rx0<I>
+where
+    I: Instance,
+{
+    unsafe fn conjure() -> Self {
+        Self { _can: PhantomData }
+    }
+
+    /// Creates a `&mut Self` out of thin air.
+    ///
+    /// This is only safe if it is the only way to access an `Rx<I>`.
+    unsafe fn conjure_by_ref<'a>() -> &'a mut Self {
+        // Cause out of bounds access when `Self` is not zero-sized.
+        [()][core::mem::size_of::<Self>()];
+
+        // Any aligned pointer is valid for ZSTs.
+        &mut *NonNull::dangling().as_ptr()
+    }
+
+    /// Returns a received frame if available.
+    ///
+    /// Returns `Err` when a frame was lost due to buffer overrun.
+    pub fn receive(&mut self) -> nb::Result<Frame, OverrunError> {
+        receive_fifo(self.registers(), 0)
+    }
+
+    fn registers(&self) -> &RegisterBlock {
+        unsafe { &*I::REGISTERS }
+    }
+}
+
+/// Interface to receiver FIFO 1.
+pub struct Rx1<I> {
+    _can: PhantomData<I>,
+}
+
+impl<I> Rx1<I>
+where
+    I: Instance,
+{
+    unsafe fn conjure() -> Self {
+        Self { _can: PhantomData }
+    }
+
+    /// Creates a `&mut Self` out of thin air.
+    ///
+    /// This is only safe if it is the only way to access an `Rx<I>`.
+    unsafe fn conjure_by_ref<'a>() -> &'a mut Self {
+        // Cause out of bounds access when `Self` is not zero-sized.
+        [()][core::mem::size_of::<Self>()];
+
+        // Any aligned pointer is valid for ZSTs.
+        &mut *NonNull::dangling().as_ptr()
+    }
+
+    /// Returns a received frame if available.
+    ///
+    /// Returns `Err` when a frame was lost due to buffer overrun.
+    pub fn receive(&mut self) -> nb::Result<Frame, OverrunError> {
+        receive_fifo(self.registers(), 1)
+    }
+
+    fn registers(&self) -> &RegisterBlock {
+        unsafe { &*I::REGISTERS }
+    }
+}
+
+fn receive_fifo(can: &RegisterBlock, fifo_nr: usize) -> nb::Result<Frame, OverrunError> {
+    assert!(fifo_nr < 2);
+    let rfr = &can.rfr[fifo_nr];
+    let rx = &can.rx[fifo_nr];
+
+    // Check if a frame is available in the mailbox.
+    let rfr_read = rfr.read();
+    if rfr_read.fmp().bits() == 0 {
+        return Err(nb::Error::WouldBlock);
+    }
+
+    // Check for RX FIFO overrun.
+    if rfr_read.fovr().bit_is_set() {
+        rfr.write(|w| w.fovr().set_bit());
+        return Err(nb::Error::Other(OverrunError { _priv: () }));
+    }
+
+    // Read the frame.
+    let mut frame = Frame {
+        id: IdReg(rx.rir.read().bits()),
+        data: [0; 8].into(),
+    };
+    frame.data[0..4].copy_from_slice(&rx.rdlr.read().bits().to_ne_bytes());
+    frame.data[4..8].copy_from_slice(&rx.rdhr.read().bits().to_ne_bytes());
+    frame.data.len = rx.rdtr.read().dlc().bits();
+
+    // Release the mailbox.
+    rfr.write(|w| w.rfom().set_bit());
+
+    Ok(frame)
+}
+
+/// Identifies one of the two receive FIFOs.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub enum Fifo {
+    Fifo0 = 0,
+    Fifo1 = 1,
+}
+
+/// Identifies one of the three transmit mailboxes.
+#[derive(Debug, Copy, Clone, Ord, PartialOrd, Eq, PartialEq)]
+#[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))]
+pub enum Mailbox {
+    /// Transmit mailbox 0
+    Mailbox0 = 0,
+    /// Transmit mailbox 1
+    Mailbox1 = 1,
+    /// Transmit mailbox 2
+    Mailbox2 = 2,
+}
+
+/// Contains information about a frame enqueued for transmission via [`Can::transmit`] or
+/// [`Tx::transmit`].
+pub struct TransmitStatus {
+    dequeued_frame: Option<Frame>,
+    mailbox: Mailbox,
+}
+
+impl TransmitStatus {
+    /// Returns the lower-priority frame that was dequeued to make space for the new frame.
+    #[inline]
+    pub fn dequeued_frame(&self) -> Option<&Frame> {
+        self.dequeued_frame.as_ref()
+    }
+
+    /// Returns the [`Mailbox`] the frame was enqueued in.
+    #[inline]
+    pub fn mailbox(&self) -> Mailbox {
+        self.mailbox
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can.rs b/embassy-stm32/src/can/bx/pac/can.rs
new file mode 100644
index 000000000..f190fdff4
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can.rs
@@ -0,0 +1,213 @@
+/// Register block of bxCAN peripherals.
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - CAN_MCR"]
+    pub(crate) mcr: MCR,
+    #[doc = "0x04 - CAN_MSR"]
+    pub(crate) msr: MSR,
+    #[doc = "0x08 - CAN_TSR"]
+    pub(crate) tsr: TSR,
+    #[doc = "0x0c - CAN_RF0R"]
+    pub(crate) rfr: [RFR; 2],
+    #[doc = "0x14 - CAN_IER"]
+    pub(crate) ier: IER,
+    #[doc = "0x18 - CAN_ESR"]
+    pub(crate) esr: ESR,
+    #[doc = "0x1c - CAN_BTR"]
+    pub(crate) btr: BTR,
+    _reserved7: [u8; 352usize],
+    #[doc = "0x180 - CAN Transmit cluster"]
+    pub(crate) tx: [TX; 3],
+    #[doc = "0x1b0 - CAN Receive cluster"]
+    pub(crate) rx: [RX; 2],
+    _reserved9: [u8; 48usize],
+    #[doc = "0x200 - CAN_FMR"]
+    pub(crate) fmr: FMR,
+    #[doc = "0x204 - CAN_FM1R"]
+    pub(crate) fm1r: FM1R,
+    _reserved11: [u8; 4usize],
+    #[doc = "0x20c - CAN_FS1R"]
+    pub(crate) fs1r: FS1R,
+    _reserved12: [u8; 4usize],
+    #[doc = "0x214 - CAN_FFA1R"]
+    pub(crate) ffa1r: FFA1R,
+    _reserved13: [u8; 4usize],
+    #[doc = "0x21c - CAN_FA1R"]
+    pub(crate) fa1r: FA1R,
+    _reserved14: [u8; 32usize],
+    #[doc = "0x240 - CAN Filter Bank cluster"]
+    pub(crate) fb: [FB; 28], // UP TO 28, but 14 in some devices
+}
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct TX {
+    #[doc = "0x00 - CAN_TI0R"]
+    pub tir: self::tx::TIR,
+    #[doc = "0x04 - CAN_TDT0R"]
+    pub tdtr: self::tx::TDTR,
+    #[doc = "0x08 - CAN_TDL0R"]
+    pub tdlr: self::tx::TDLR,
+    #[doc = "0x0c - CAN_TDH0R"]
+    pub tdhr: self::tx::TDHR,
+}
+#[doc = r"Register block"]
+#[doc = "CAN Transmit cluster"]
+pub mod tx;
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RX {
+    #[doc = "0x00 - CAN_RI0R"]
+    pub rir: self::rx::RIR,
+    #[doc = "0x04 - CAN_RDT0R"]
+    pub rdtr: self::rx::RDTR,
+    #[doc = "0x08 - CAN_RDL0R"]
+    pub rdlr: self::rx::RDLR,
+    #[doc = "0x0c - CAN_RDH0R"]
+    pub rdhr: self::rx::RDHR,
+}
+#[doc = r"Register block"]
+#[doc = "CAN Receive cluster"]
+pub mod rx;
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct FB {
+    #[doc = "0x00 - Filter bank 0 register 1"]
+    pub fr1: self::fb::FR1,
+    #[doc = "0x04 - Filter bank 0 register 2"]
+    pub fr2: self::fb::FR2,
+}
+#[doc = r"Register block"]
+#[doc = "CAN Filter Bank cluster"]
+pub mod fb;
+#[doc = "CAN_MCR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](mcr) module"]
+pub type MCR = crate::Reg<u32, _MCR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _MCR;
+#[doc = "`read()` method returns [mcr::R](mcr::R) reader structure"]
+impl crate::Readable for MCR {}
+#[doc = "`write(|w| ..)` method takes [mcr::W](mcr::W) writer structure"]
+impl crate::Writable for MCR {}
+#[doc = "CAN_MCR"]
+pub mod mcr;
+#[doc = "CAN_MSR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](msr) module"]
+pub type MSR = crate::Reg<u32, _MSR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _MSR;
+#[doc = "`read()` method returns [msr::R](msr::R) reader structure"]
+impl crate::Readable for MSR {}
+#[doc = "`write(|w| ..)` method takes [msr::W](msr::W) writer structure"]
+impl crate::Writable for MSR {}
+#[doc = "CAN_MSR"]
+pub mod msr;
+#[doc = "CAN_TSR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tsr](tsr) module"]
+pub type TSR = crate::Reg<u32, _TSR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _TSR;
+#[doc = "`read()` method returns [tsr::R](tsr::R) reader structure"]
+impl crate::Readable for TSR {}
+#[doc = "`write(|w| ..)` method takes [tsr::W](tsr::W) writer structure"]
+impl crate::Writable for TSR {}
+#[doc = "CAN_TSR"]
+pub mod tsr;
+#[doc = "CAN_RF0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfr](rfr) module"]
+pub type RFR = crate::Reg<u32, _RFR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _RFR;
+#[doc = "`read()` method returns [rfr::R](rfr::R) reader structure"]
+impl crate::Readable for RFR {}
+#[doc = "`write(|w| ..)` method takes [rfr::W](rfr::W) writer structure"]
+impl crate::Writable for RFR {}
+#[doc = "CAN_RF0R"]
+pub mod rfr;
+#[doc = "CAN_IER\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](ier) module"]
+pub type IER = crate::Reg<u32, _IER>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _IER;
+#[doc = "`read()` method returns [ier::R](ier::R) reader structure"]
+impl crate::Readable for IER {}
+#[doc = "`write(|w| ..)` method takes [ier::W](ier::W) writer structure"]
+impl crate::Writable for IER {}
+#[doc = "CAN_IER"]
+pub mod ier;
+#[doc = "CAN_ESR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [esr](esr) module"]
+pub type ESR = crate::Reg<u32, _ESR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _ESR;
+#[doc = "`read()` method returns [esr::R](esr::R) reader structure"]
+impl crate::Readable for ESR {}
+#[doc = "`write(|w| ..)` method takes [esr::W](esr::W) writer structure"]
+impl crate::Writable for ESR {}
+#[doc = "CAN_ESR"]
+pub mod esr;
+#[doc = "CAN_BTR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [btr](btr) module"]
+pub type BTR = crate::Reg<u32, _BTR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _BTR;
+#[doc = "`read()` method returns [btr::R](btr::R) reader structure"]
+impl crate::Readable for BTR {}
+#[doc = "`write(|w| ..)` method takes [btr::W](btr::W) writer structure"]
+impl crate::Writable for BTR {}
+#[doc = "CAN_BTR"]
+pub mod btr;
+#[doc = "CAN_FMR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fmr](fmr) module"]
+pub type FMR = crate::Reg<u32, _FMR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _FMR;
+#[doc = "`read()` method returns [fmr::R](fmr::R) reader structure"]
+impl crate::Readable for FMR {}
+#[doc = "`write(|w| ..)` method takes [fmr::W](fmr::W) writer structure"]
+impl crate::Writable for FMR {}
+#[doc = "CAN_FMR"]
+pub mod fmr;
+#[doc = "CAN_FM1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fm1r](fm1r) module"]
+pub type FM1R = crate::Reg<u32, _FM1R>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _FM1R;
+#[doc = "`read()` method returns [fm1r::R](fm1r::R) reader structure"]
+impl crate::Readable for FM1R {}
+#[doc = "`write(|w| ..)` method takes [fm1r::W](fm1r::W) writer structure"]
+impl crate::Writable for FM1R {}
+#[doc = "CAN_FM1R"]
+pub mod fm1r;
+#[doc = "CAN_FS1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fs1r](fs1r) module"]
+pub type FS1R = crate::Reg<u32, _FS1R>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _FS1R;
+#[doc = "`read()` method returns [fs1r::R](fs1r::R) reader structure"]
+impl crate::Readable for FS1R {}
+#[doc = "`write(|w| ..)` method takes [fs1r::W](fs1r::W) writer structure"]
+impl crate::Writable for FS1R {}
+#[doc = "CAN_FS1R"]
+pub mod fs1r;
+#[doc = "CAN_FFA1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ffa1r](ffa1r) module"]
+pub type FFA1R = crate::Reg<u32, _FFA1R>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _FFA1R;
+#[doc = "`read()` method returns [ffa1r::R](ffa1r::R) reader structure"]
+impl crate::Readable for FFA1R {}
+#[doc = "`write(|w| ..)` method takes [ffa1r::W](ffa1r::W) writer structure"]
+impl crate::Writable for FFA1R {}
+#[doc = "CAN_FFA1R"]
+pub mod ffa1r;
+#[doc = "CAN_FA1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fa1r](fa1r) module"]
+pub type FA1R = crate::Reg<u32, _FA1R>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _FA1R;
+#[doc = "`read()` method returns [fa1r::R](fa1r::R) reader structure"]
+impl crate::Readable for FA1R {}
+#[doc = "`write(|w| ..)` method takes [fa1r::W](fa1r::W) writer structure"]
+impl crate::Writable for FA1R {}
+#[doc = "CAN_FA1R"]
+pub mod fa1r;
diff --git a/embassy-stm32/src/can/bx/pac/can/btr.rs b/embassy-stm32/src/can/bx/pac/can/btr.rs
new file mode 100644
index 000000000..0a801c50e
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/btr.rs
@@ -0,0 +1,282 @@
+#[doc = "Reader of register BTR"]
+pub type R = crate::R<u32, super::BTR>;
+#[doc = "Writer for register BTR"]
+pub type W = crate::W<u32, super::BTR>;
+#[doc = "Register BTR `reset()`'s with value 0"]
+impl crate::ResetValue for super::BTR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "SILM\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SILM_A {
+    #[doc = "0: Normal operation"]
+    NORMAL = 0,
+    #[doc = "1: Silent Mode"]
+    SILENT = 1,
+}
+impl From<SILM_A> for bool {
+    #[inline(always)]
+    fn from(variant: SILM_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `SILM`"]
+pub type SILM_R = crate::R<bool, SILM_A>;
+impl SILM_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SILM_A {
+        match self.bits {
+            false => SILM_A::NORMAL,
+            true => SILM_A::SILENT,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NORMAL`"]
+    #[inline(always)]
+    pub fn is_normal(&self) -> bool {
+        *self == SILM_A::NORMAL
+    }
+    #[doc = "Checks if the value of the field is `SILENT`"]
+    #[inline(always)]
+    pub fn is_silent(&self) -> bool {
+        *self == SILM_A::SILENT
+    }
+}
+#[doc = "Write proxy for field `SILM`"]
+pub struct SILM_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SILM_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: SILM_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "Normal operation"]
+    #[inline(always)]
+    pub fn normal(self) -> &'a mut W {
+        self.variant(SILM_A::NORMAL)
+    }
+    #[doc = "Silent Mode"]
+    #[inline(always)]
+    pub fn silent(self) -> &'a mut W {
+        self.variant(SILM_A::SILENT)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
+        self.w
+    }
+}
+#[doc = "LBKM\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LBKM_A {
+    #[doc = "0: Loop Back Mode disabled"]
+    DISABLED = 0,
+    #[doc = "1: Loop Back Mode enabled"]
+    ENABLED = 1,
+}
+impl From<LBKM_A> for bool {
+    #[inline(always)]
+    fn from(variant: LBKM_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `LBKM`"]
+pub type LBKM_R = crate::R<bool, LBKM_A>;
+impl LBKM_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LBKM_A {
+        match self.bits {
+            false => LBKM_A::DISABLED,
+            true => LBKM_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LBKM_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LBKM_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `LBKM`"]
+pub struct LBKM_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LBKM_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: LBKM_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "Loop Back Mode disabled"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(LBKM_A::DISABLED)
+    }
+    #[doc = "Loop Back Mode enabled"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(LBKM_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
+        self.w
+    }
+}
+#[doc = "Reader of field `SJW`"]
+pub type SJW_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `SJW`"]
+pub struct SJW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SJW_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
+        self.w
+    }
+}
+#[doc = "Reader of field `TS2`"]
+pub type TS2_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `TS2`"]
+pub struct TS2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TS2_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 20)) | (((value as u32) & 0x07) << 20);
+        self.w
+    }
+}
+#[doc = "Reader of field `TS1`"]
+pub type TS1_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `TS1`"]
+pub struct TS1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TS1_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
+        self.w
+    }
+}
+#[doc = "Reader of field `BRP`"]
+pub type BRP_R = crate::R<u16, u16>;
+#[doc = "Write proxy for field `BRP`"]
+pub struct BRP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> BRP_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 31 - SILM"]
+    #[inline(always)]
+    pub fn silm(&self) -> SILM_R {
+        SILM_R::new(((self.bits >> 31) & 0x01) != 0)
+    }
+    #[doc = "Bit 30 - LBKM"]
+    #[inline(always)]
+    pub fn lbkm(&self) -> LBKM_R {
+        LBKM_R::new(((self.bits >> 30) & 0x01) != 0)
+    }
+    #[doc = "Bits 24:25 - SJW"]
+    #[inline(always)]
+    pub fn sjw(&self) -> SJW_R {
+        SJW_R::new(((self.bits >> 24) & 0x03) as u8)
+    }
+    #[doc = "Bits 20:22 - TS2"]
+    #[inline(always)]
+    pub fn ts2(&self) -> TS2_R {
+        TS2_R::new(((self.bits >> 20) & 0x07) as u8)
+    }
+    #[doc = "Bits 16:19 - TS1"]
+    #[inline(always)]
+    pub fn ts1(&self) -> TS1_R {
+        TS1_R::new(((self.bits >> 16) & 0x0f) as u8)
+    }
+    #[doc = "Bits 0:9 - BRP"]
+    #[inline(always)]
+    pub fn brp(&self) -> BRP_R {
+        BRP_R::new((self.bits & 0x03ff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bit 31 - SILM"]
+    #[inline(always)]
+    pub fn silm(&mut self) -> SILM_W {
+        SILM_W { w: self }
+    }
+    #[doc = "Bit 30 - LBKM"]
+    #[inline(always)]
+    pub fn lbkm(&mut self) -> LBKM_W {
+        LBKM_W { w: self }
+    }
+    #[doc = "Bits 24:25 - SJW"]
+    #[inline(always)]
+    pub fn sjw(&mut self) -> SJW_W {
+        SJW_W { w: self }
+    }
+    #[doc = "Bits 20:22 - TS2"]
+    #[inline(always)]
+    pub fn ts2(&mut self) -> TS2_W {
+        TS2_W { w: self }
+    }
+    #[doc = "Bits 16:19 - TS1"]
+    #[inline(always)]
+    pub fn ts1(&mut self) -> TS1_W {
+        TS1_W { w: self }
+    }
+    #[doc = "Bits 0:9 - BRP"]
+    #[inline(always)]
+    pub fn brp(&mut self) -> BRP_W {
+        BRP_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/esr.rs b/embassy-stm32/src/can/bx/pac/can/esr.rs
new file mode 100644
index 000000000..9ea7c5a24
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/esr.rs
@@ -0,0 +1,206 @@
+#[doc = "Reader of register ESR"]
+pub type R = crate::R<u32, super::ESR>;
+#[doc = "Writer for register ESR"]
+pub type W = crate::W<u32, super::ESR>;
+#[doc = "Register ESR `reset()`'s with value 0"]
+impl crate::ResetValue for super::ESR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `REC`"]
+pub type REC_R = crate::R<u8, u8>;
+#[doc = "Reader of field `TEC`"]
+pub type TEC_R = crate::R<u8, u8>;
+#[doc = "LEC\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LEC_A {
+    #[doc = "0: No Error"]
+    NOERROR = 0,
+    #[doc = "1: Stuff Error"]
+    STUFF = 1,
+    #[doc = "2: Form Error"]
+    FORM = 2,
+    #[doc = "3: Acknowledgment Error"]
+    ACK = 3,
+    #[doc = "4: Bit recessive Error"]
+    BITRECESSIVE = 4,
+    #[doc = "5: Bit dominant Error"]
+    BITDOMINANT = 5,
+    #[doc = "6: CRC Error"]
+    CRC = 6,
+    #[doc = "7: Set by software"]
+    CUSTOM = 7,
+}
+impl From<LEC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LEC_A) -> Self {
+        variant as _
+    }
+}
+#[doc = "Reader of field `LEC`"]
+pub type LEC_R = crate::R<u8, LEC_A>;
+impl LEC_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LEC_A {
+        match self.bits {
+            0 => LEC_A::NOERROR,
+            1 => LEC_A::STUFF,
+            2 => LEC_A::FORM,
+            3 => LEC_A::ACK,
+            4 => LEC_A::BITRECESSIVE,
+            5 => LEC_A::BITDOMINANT,
+            6 => LEC_A::CRC,
+            7 => LEC_A::CUSTOM,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOERROR`"]
+    #[inline(always)]
+    pub fn is_no_error(&self) -> bool {
+        *self == LEC_A::NOERROR
+    }
+    #[doc = "Checks if the value of the field is `STUFF`"]
+    #[inline(always)]
+    pub fn is_stuff(&self) -> bool {
+        *self == LEC_A::STUFF
+    }
+    #[doc = "Checks if the value of the field is `FORM`"]
+    #[inline(always)]
+    pub fn is_form(&self) -> bool {
+        *self == LEC_A::FORM
+    }
+    #[doc = "Checks if the value of the field is `ACK`"]
+    #[inline(always)]
+    pub fn is_ack(&self) -> bool {
+        *self == LEC_A::ACK
+    }
+    #[doc = "Checks if the value of the field is `BITRECESSIVE`"]
+    #[inline(always)]
+    pub fn is_bit_recessive(&self) -> bool {
+        *self == LEC_A::BITRECESSIVE
+    }
+    #[doc = "Checks if the value of the field is `BITDOMINANT`"]
+    #[inline(always)]
+    pub fn is_bit_dominant(&self) -> bool {
+        *self == LEC_A::BITDOMINANT
+    }
+    #[doc = "Checks if the value of the field is `CRC`"]
+    #[inline(always)]
+    pub fn is_crc(&self) -> bool {
+        *self == LEC_A::CRC
+    }
+    #[doc = "Checks if the value of the field is `CUSTOM`"]
+    #[inline(always)]
+    pub fn is_custom(&self) -> bool {
+        *self == LEC_A::CUSTOM
+    }
+}
+#[doc = "Write proxy for field `LEC`"]
+pub struct LEC_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LEC_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: LEC_A) -> &'a mut W {
+        {
+            self.bits(variant.into())
+        }
+    }
+    #[doc = "No Error"]
+    #[inline(always)]
+    pub fn no_error(self) -> &'a mut W {
+        self.variant(LEC_A::NOERROR)
+    }
+    #[doc = "Stuff Error"]
+    #[inline(always)]
+    pub fn stuff(self) -> &'a mut W {
+        self.variant(LEC_A::STUFF)
+    }
+    #[doc = "Form Error"]
+    #[inline(always)]
+    pub fn form(self) -> &'a mut W {
+        self.variant(LEC_A::FORM)
+    }
+    #[doc = "Acknowledgment Error"]
+    #[inline(always)]
+    pub fn ack(self) -> &'a mut W {
+        self.variant(LEC_A::ACK)
+    }
+    #[doc = "Bit recessive Error"]
+    #[inline(always)]
+    pub fn bit_recessive(self) -> &'a mut W {
+        self.variant(LEC_A::BITRECESSIVE)
+    }
+    #[doc = "Bit dominant Error"]
+    #[inline(always)]
+    pub fn bit_dominant(self) -> &'a mut W {
+        self.variant(LEC_A::BITDOMINANT)
+    }
+    #[doc = "CRC Error"]
+    #[inline(always)]
+    pub fn crc(self) -> &'a mut W {
+        self.variant(LEC_A::CRC)
+    }
+    #[doc = "Set by software"]
+    #[inline(always)]
+    pub fn custom(self) -> &'a mut W {
+        self.variant(LEC_A::CUSTOM)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
+        self.w
+    }
+}
+#[doc = "Reader of field `BOFF`"]
+pub type BOFF_R = crate::R<bool, bool>;
+#[doc = "Reader of field `EPVF`"]
+pub type EPVF_R = crate::R<bool, bool>;
+#[doc = "Reader of field `EWGF`"]
+pub type EWGF_R = crate::R<bool, bool>;
+impl R {
+    #[doc = "Bits 24:31 - REC"]
+    #[inline(always)]
+    pub fn rec(&self) -> REC_R {
+        REC_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - TEC"]
+    #[inline(always)]
+    pub fn tec(&self) -> TEC_R {
+        TEC_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 4:6 - LEC"]
+    #[inline(always)]
+    pub fn lec(&self) -> LEC_R {
+        LEC_R::new(((self.bits >> 4) & 0x07) as u8)
+    }
+    #[doc = "Bit 2 - BOFF"]
+    #[inline(always)]
+    pub fn boff(&self) -> BOFF_R {
+        BOFF_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - EPVF"]
+    #[inline(always)]
+    pub fn epvf(&self) -> EPVF_R {
+        EPVF_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 0 - EWGF"]
+    #[inline(always)]
+    pub fn ewgf(&self) -> EWGF_R {
+        EWGF_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 4:6 - LEC"]
+    #[inline(always)]
+    pub fn lec(&mut self) -> LEC_W {
+        LEC_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/fa1r.rs b/embassy-stm32/src/can/bx/pac/can/fa1r.rs
new file mode 100644
index 000000000..797e4e074
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/fa1r.rs
@@ -0,0 +1,492 @@
+#[doc = "Reader of register FA1R"]
+pub type R = crate::R<u32, super::FA1R>;
+#[doc = "Writer for register FA1R"]
+pub type W = crate::W<u32, super::FA1R>;
+#[doc = "Register FA1R `reset()`'s with value 0"]
+impl crate::ResetValue for super::FA1R {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `FACT0`"]
+pub type FACT0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT0`"]
+pub struct FACT0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT1`"]
+pub type FACT1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT1`"]
+pub struct FACT1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT2`"]
+pub type FACT2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT2`"]
+pub struct FACT2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT3`"]
+pub type FACT3_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT3`"]
+pub struct FACT3_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT3_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT4`"]
+pub type FACT4_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT4`"]
+pub struct FACT4_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT4_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT5`"]
+pub type FACT5_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT5`"]
+pub struct FACT5_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT5_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT6`"]
+pub type FACT6_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT6`"]
+pub struct FACT6_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT6_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT7`"]
+pub type FACT7_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT7`"]
+pub struct FACT7_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT7_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT8`"]
+pub type FACT8_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT8`"]
+pub struct FACT8_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT8_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT9`"]
+pub type FACT9_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT9`"]
+pub struct FACT9_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT9_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT10`"]
+pub type FACT10_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT10`"]
+pub struct FACT10_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT10_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT11`"]
+pub type FACT11_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT11`"]
+pub struct FACT11_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT11_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT12`"]
+pub type FACT12_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT12`"]
+pub struct FACT12_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT12_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Reader of field `FACT13`"]
+pub type FACT13_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FACT13`"]
+pub struct FACT13_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FACT13_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Filter active"]
+    #[inline(always)]
+    pub fn fact0(&self) -> FACT0_R {
+        FACT0_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - Filter active"]
+    #[inline(always)]
+    pub fn fact1(&self) -> FACT1_R {
+        FACT1_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Filter active"]
+    #[inline(always)]
+    pub fn fact2(&self) -> FACT2_R {
+        FACT2_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Filter active"]
+    #[inline(always)]
+    pub fn fact3(&self) -> FACT3_R {
+        FACT3_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Filter active"]
+    #[inline(always)]
+    pub fn fact4(&self) -> FACT4_R {
+        FACT4_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Filter active"]
+    #[inline(always)]
+    pub fn fact5(&self) -> FACT5_R {
+        FACT5_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Filter active"]
+    #[inline(always)]
+    pub fn fact6(&self) -> FACT6_R {
+        FACT6_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Filter active"]
+    #[inline(always)]
+    pub fn fact7(&self) -> FACT7_R {
+        FACT7_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Filter active"]
+    #[inline(always)]
+    pub fn fact8(&self) -> FACT8_R {
+        FACT8_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Filter active"]
+    #[inline(always)]
+    pub fn fact9(&self) -> FACT9_R {
+        FACT9_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - Filter active"]
+    #[inline(always)]
+    pub fn fact10(&self) -> FACT10_R {
+        FACT10_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - Filter active"]
+    #[inline(always)]
+    pub fn fact11(&self) -> FACT11_R {
+        FACT11_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - Filter active"]
+    #[inline(always)]
+    pub fn fact12(&self) -> FACT12_R {
+        FACT12_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - Filter active"]
+    #[inline(always)]
+    pub fn fact13(&self) -> FACT13_R {
+        FACT13_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Filter active"]
+    #[inline(always)]
+    pub fn fact0(&mut self) -> FACT0_W {
+        FACT0_W { w: self }
+    }
+    #[doc = "Bit 1 - Filter active"]
+    #[inline(always)]
+    pub fn fact1(&mut self) -> FACT1_W {
+        FACT1_W { w: self }
+    }
+    #[doc = "Bit 2 - Filter active"]
+    #[inline(always)]
+    pub fn fact2(&mut self) -> FACT2_W {
+        FACT2_W { w: self }
+    }
+    #[doc = "Bit 3 - Filter active"]
+    #[inline(always)]
+    pub fn fact3(&mut self) -> FACT3_W {
+        FACT3_W { w: self }
+    }
+    #[doc = "Bit 4 - Filter active"]
+    #[inline(always)]
+    pub fn fact4(&mut self) -> FACT4_W {
+        FACT4_W { w: self }
+    }
+    #[doc = "Bit 5 - Filter active"]
+    #[inline(always)]
+    pub fn fact5(&mut self) -> FACT5_W {
+        FACT5_W { w: self }
+    }
+    #[doc = "Bit 6 - Filter active"]
+    #[inline(always)]
+    pub fn fact6(&mut self) -> FACT6_W {
+        FACT6_W { w: self }
+    }
+    #[doc = "Bit 7 - Filter active"]
+    #[inline(always)]
+    pub fn fact7(&mut self) -> FACT7_W {
+        FACT7_W { w: self }
+    }
+    #[doc = "Bit 8 - Filter active"]
+    #[inline(always)]
+    pub fn fact8(&mut self) -> FACT8_W {
+        FACT8_W { w: self }
+    }
+    #[doc = "Bit 9 - Filter active"]
+    #[inline(always)]
+    pub fn fact9(&mut self) -> FACT9_W {
+        FACT9_W { w: self }
+    }
+    #[doc = "Bit 10 - Filter active"]
+    #[inline(always)]
+    pub fn fact10(&mut self) -> FACT10_W {
+        FACT10_W { w: self }
+    }
+    #[doc = "Bit 11 - Filter active"]
+    #[inline(always)]
+    pub fn fact11(&mut self) -> FACT11_W {
+        FACT11_W { w: self }
+    }
+    #[doc = "Bit 12 - Filter active"]
+    #[inline(always)]
+    pub fn fact12(&mut self) -> FACT12_W {
+        FACT12_W { w: self }
+    }
+    #[doc = "Bit 13 - Filter active"]
+    #[inline(always)]
+    pub fn fact13(&mut self) -> FACT13_W {
+        FACT13_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/fb.rs b/embassy-stm32/src/can/bx/pac/can/fb.rs
new file mode 100644
index 000000000..1b31e37c5
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/fb.rs
@@ -0,0 +1,22 @@
+#[doc = "Filter bank 0 register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr1](fr1) module"]
+pub type FR1 = crate::Reg<u32, _FR1>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _FR1;
+#[doc = "`read()` method returns [fr1::R](fr1::R) reader structure"]
+impl crate::Readable for FR1 {}
+#[doc = "`write(|w| ..)` method takes [fr1::W](fr1::W) writer structure"]
+impl crate::Writable for FR1 {}
+#[doc = "Filter bank 0 register 1"]
+pub mod fr1;
+#[doc = "Filter bank 0 register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr2](fr2) module"]
+pub type FR2 = crate::Reg<u32, _FR2>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _FR2;
+#[doc = "`read()` method returns [fr2::R](fr2::R) reader structure"]
+impl crate::Readable for FR2 {}
+#[doc = "`write(|w| ..)` method takes [fr2::W](fr2::W) writer structure"]
+impl crate::Writable for FR2 {}
+#[doc = "Filter bank 0 register 2"]
+pub mod fr2;
diff --git a/embassy-stm32/src/can/bx/pac/can/fb/fr1.rs b/embassy-stm32/src/can/bx/pac/can/fb/fr1.rs
new file mode 100644
index 000000000..b39d5e8fb
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/fb/fr1.rs
@@ -0,0 +1,40 @@
+#[doc = "Reader of register FR1"]
+pub type R = crate::R<u32, super::FR1>;
+#[doc = "Writer for register FR1"]
+pub type W = crate::W<u32, super::FR1>;
+#[doc = "Register FR1 `reset()`'s with value 0"]
+impl crate::ResetValue for super::FR1 {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `FB`"]
+pub type FB_R = crate::R<u32, u32>;
+#[doc = "Write proxy for field `FB`"]
+pub struct FB_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FB_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Filter bits"]
+    #[inline(always)]
+    pub fn fb(&self) -> FB_R {
+        FB_R::new((self.bits & 0xffff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Filter bits"]
+    #[inline(always)]
+    pub fn fb(&mut self) -> FB_W {
+        FB_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/fb/fr2.rs b/embassy-stm32/src/can/bx/pac/can/fb/fr2.rs
new file mode 100644
index 000000000..1f318894e
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/fb/fr2.rs
@@ -0,0 +1,40 @@
+#[doc = "Reader of register FR2"]
+pub type R = crate::R<u32, super::FR2>;
+#[doc = "Writer for register FR2"]
+pub type W = crate::W<u32, super::FR2>;
+#[doc = "Register FR2 `reset()`'s with value 0"]
+impl crate::ResetValue for super::FR2 {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `FB`"]
+pub type FB_R = crate::R<u32, u32>;
+#[doc = "Write proxy for field `FB`"]
+pub struct FB_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FB_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Filter bits"]
+    #[inline(always)]
+    pub fn fb(&self) -> FB_R {
+        FB_R::new((self.bits & 0xffff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Filter bits"]
+    #[inline(always)]
+    pub fn fb(&mut self) -> FB_W {
+        FB_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/ffa1r.rs b/embassy-stm32/src/can/bx/pac/can/ffa1r.rs
new file mode 100644
index 000000000..bc3ab0eb9
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/ffa1r.rs
@@ -0,0 +1,492 @@
+#[doc = "Reader of register FFA1R"]
+pub type R = crate::R<u32, super::FFA1R>;
+#[doc = "Writer for register FFA1R"]
+pub type W = crate::W<u32, super::FFA1R>;
+#[doc = "Register FFA1R `reset()`'s with value 0"]
+impl crate::ResetValue for super::FFA1R {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `FFA0`"]
+pub type FFA0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA0`"]
+pub struct FFA0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA1`"]
+pub type FFA1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA1`"]
+pub struct FFA1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA2`"]
+pub type FFA2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA2`"]
+pub struct FFA2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA3`"]
+pub type FFA3_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA3`"]
+pub struct FFA3_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA3_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA4`"]
+pub type FFA4_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA4`"]
+pub struct FFA4_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA4_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA5`"]
+pub type FFA5_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA5`"]
+pub struct FFA5_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA5_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA6`"]
+pub type FFA6_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA6`"]
+pub struct FFA6_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA6_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA7`"]
+pub type FFA7_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA7`"]
+pub struct FFA7_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA7_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA8`"]
+pub type FFA8_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA8`"]
+pub struct FFA8_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA8_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA9`"]
+pub type FFA9_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA9`"]
+pub struct FFA9_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA9_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA10`"]
+pub type FFA10_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA10`"]
+pub struct FFA10_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA10_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA11`"]
+pub type FFA11_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA11`"]
+pub struct FFA11_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA11_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA12`"]
+pub type FFA12_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA12`"]
+pub struct FFA12_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA12_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Reader of field `FFA13`"]
+pub type FFA13_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FFA13`"]
+pub struct FFA13_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFA13_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Filter FIFO assignment for filter 0"]
+    #[inline(always)]
+    pub fn ffa0(&self) -> FFA0_R {
+        FFA0_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - Filter FIFO assignment for filter 1"]
+    #[inline(always)]
+    pub fn ffa1(&self) -> FFA1_R {
+        FFA1_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Filter FIFO assignment for filter 2"]
+    #[inline(always)]
+    pub fn ffa2(&self) -> FFA2_R {
+        FFA2_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Filter FIFO assignment for filter 3"]
+    #[inline(always)]
+    pub fn ffa3(&self) -> FFA3_R {
+        FFA3_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Filter FIFO assignment for filter 4"]
+    #[inline(always)]
+    pub fn ffa4(&self) -> FFA4_R {
+        FFA4_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Filter FIFO assignment for filter 5"]
+    #[inline(always)]
+    pub fn ffa5(&self) -> FFA5_R {
+        FFA5_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Filter FIFO assignment for filter 6"]
+    #[inline(always)]
+    pub fn ffa6(&self) -> FFA6_R {
+        FFA6_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Filter FIFO assignment for filter 7"]
+    #[inline(always)]
+    pub fn ffa7(&self) -> FFA7_R {
+        FFA7_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Filter FIFO assignment for filter 8"]
+    #[inline(always)]
+    pub fn ffa8(&self) -> FFA8_R {
+        FFA8_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Filter FIFO assignment for filter 9"]
+    #[inline(always)]
+    pub fn ffa9(&self) -> FFA9_R {
+        FFA9_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - Filter FIFO assignment for filter 10"]
+    #[inline(always)]
+    pub fn ffa10(&self) -> FFA10_R {
+        FFA10_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - Filter FIFO assignment for filter 11"]
+    #[inline(always)]
+    pub fn ffa11(&self) -> FFA11_R {
+        FFA11_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - Filter FIFO assignment for filter 12"]
+    #[inline(always)]
+    pub fn ffa12(&self) -> FFA12_R {
+        FFA12_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - Filter FIFO assignment for filter 13"]
+    #[inline(always)]
+    pub fn ffa13(&self) -> FFA13_R {
+        FFA13_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Filter FIFO assignment for filter 0"]
+    #[inline(always)]
+    pub fn ffa0(&mut self) -> FFA0_W {
+        FFA0_W { w: self }
+    }
+    #[doc = "Bit 1 - Filter FIFO assignment for filter 1"]
+    #[inline(always)]
+    pub fn ffa1(&mut self) -> FFA1_W {
+        FFA1_W { w: self }
+    }
+    #[doc = "Bit 2 - Filter FIFO assignment for filter 2"]
+    #[inline(always)]
+    pub fn ffa2(&mut self) -> FFA2_W {
+        FFA2_W { w: self }
+    }
+    #[doc = "Bit 3 - Filter FIFO assignment for filter 3"]
+    #[inline(always)]
+    pub fn ffa3(&mut self) -> FFA3_W {
+        FFA3_W { w: self }
+    }
+    #[doc = "Bit 4 - Filter FIFO assignment for filter 4"]
+    #[inline(always)]
+    pub fn ffa4(&mut self) -> FFA4_W {
+        FFA4_W { w: self }
+    }
+    #[doc = "Bit 5 - Filter FIFO assignment for filter 5"]
+    #[inline(always)]
+    pub fn ffa5(&mut self) -> FFA5_W {
+        FFA5_W { w: self }
+    }
+    #[doc = "Bit 6 - Filter FIFO assignment for filter 6"]
+    #[inline(always)]
+    pub fn ffa6(&mut self) -> FFA6_W {
+        FFA6_W { w: self }
+    }
+    #[doc = "Bit 7 - Filter FIFO assignment for filter 7"]
+    #[inline(always)]
+    pub fn ffa7(&mut self) -> FFA7_W {
+        FFA7_W { w: self }
+    }
+    #[doc = "Bit 8 - Filter FIFO assignment for filter 8"]
+    #[inline(always)]
+    pub fn ffa8(&mut self) -> FFA8_W {
+        FFA8_W { w: self }
+    }
+    #[doc = "Bit 9 - Filter FIFO assignment for filter 9"]
+    #[inline(always)]
+    pub fn ffa9(&mut self) -> FFA9_W {
+        FFA9_W { w: self }
+    }
+    #[doc = "Bit 10 - Filter FIFO assignment for filter 10"]
+    #[inline(always)]
+    pub fn ffa10(&mut self) -> FFA10_W {
+        FFA10_W { w: self }
+    }
+    #[doc = "Bit 11 - Filter FIFO assignment for filter 11"]
+    #[inline(always)]
+    pub fn ffa11(&mut self) -> FFA11_W {
+        FFA11_W { w: self }
+    }
+    #[doc = "Bit 12 - Filter FIFO assignment for filter 12"]
+    #[inline(always)]
+    pub fn ffa12(&mut self) -> FFA12_W {
+        FFA12_W { w: self }
+    }
+    #[doc = "Bit 13 - Filter FIFO assignment for filter 13"]
+    #[inline(always)]
+    pub fn ffa13(&mut self) -> FFA13_W {
+        FFA13_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/fm1r.rs b/embassy-stm32/src/can/bx/pac/can/fm1r.rs
new file mode 100644
index 000000000..e0a8dc648
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/fm1r.rs
@@ -0,0 +1,492 @@
+#[doc = "Reader of register FM1R"]
+pub type R = crate::R<u32, super::FM1R>;
+#[doc = "Writer for register FM1R"]
+pub type W = crate::W<u32, super::FM1R>;
+#[doc = "Register FM1R `reset()`'s with value 0"]
+impl crate::ResetValue for super::FM1R {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `FBM0`"]
+pub type FBM0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM0`"]
+pub struct FBM0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM1`"]
+pub type FBM1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM1`"]
+pub struct FBM1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM2`"]
+pub type FBM2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM2`"]
+pub struct FBM2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM3`"]
+pub type FBM3_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM3`"]
+pub struct FBM3_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM3_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM4`"]
+pub type FBM4_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM4`"]
+pub struct FBM4_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM4_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM5`"]
+pub type FBM5_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM5`"]
+pub struct FBM5_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM5_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM6`"]
+pub type FBM6_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM6`"]
+pub struct FBM6_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM6_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM7`"]
+pub type FBM7_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM7`"]
+pub struct FBM7_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM7_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM8`"]
+pub type FBM8_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM8`"]
+pub struct FBM8_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM8_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM9`"]
+pub type FBM9_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM9`"]
+pub struct FBM9_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM9_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM10`"]
+pub type FBM10_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM10`"]
+pub struct FBM10_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM10_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM11`"]
+pub type FBM11_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM11`"]
+pub struct FBM11_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM11_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM12`"]
+pub type FBM12_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM12`"]
+pub struct FBM12_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM12_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Reader of field `FBM13`"]
+pub type FBM13_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FBM13`"]
+pub struct FBM13_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FBM13_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm0(&self) -> FBM0_R {
+        FBM0_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm1(&self) -> FBM1_R {
+        FBM1_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm2(&self) -> FBM2_R {
+        FBM2_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm3(&self) -> FBM3_R {
+        FBM3_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm4(&self) -> FBM4_R {
+        FBM4_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm5(&self) -> FBM5_R {
+        FBM5_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm6(&self) -> FBM6_R {
+        FBM6_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm7(&self) -> FBM7_R {
+        FBM7_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm8(&self) -> FBM8_R {
+        FBM8_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm9(&self) -> FBM9_R {
+        FBM9_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm10(&self) -> FBM10_R {
+        FBM10_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm11(&self) -> FBM11_R {
+        FBM11_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm12(&self) -> FBM12_R {
+        FBM12_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm13(&self) -> FBM13_R {
+        FBM13_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm0(&mut self) -> FBM0_W {
+        FBM0_W { w: self }
+    }
+    #[doc = "Bit 1 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm1(&mut self) -> FBM1_W {
+        FBM1_W { w: self }
+    }
+    #[doc = "Bit 2 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm2(&mut self) -> FBM2_W {
+        FBM2_W { w: self }
+    }
+    #[doc = "Bit 3 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm3(&mut self) -> FBM3_W {
+        FBM3_W { w: self }
+    }
+    #[doc = "Bit 4 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm4(&mut self) -> FBM4_W {
+        FBM4_W { w: self }
+    }
+    #[doc = "Bit 5 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm5(&mut self) -> FBM5_W {
+        FBM5_W { w: self }
+    }
+    #[doc = "Bit 6 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm6(&mut self) -> FBM6_W {
+        FBM6_W { w: self }
+    }
+    #[doc = "Bit 7 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm7(&mut self) -> FBM7_W {
+        FBM7_W { w: self }
+    }
+    #[doc = "Bit 8 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm8(&mut self) -> FBM8_W {
+        FBM8_W { w: self }
+    }
+    #[doc = "Bit 9 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm9(&mut self) -> FBM9_W {
+        FBM9_W { w: self }
+    }
+    #[doc = "Bit 10 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm10(&mut self) -> FBM10_W {
+        FBM10_W { w: self }
+    }
+    #[doc = "Bit 11 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm11(&mut self) -> FBM11_W {
+        FBM11_W { w: self }
+    }
+    #[doc = "Bit 12 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm12(&mut self) -> FBM12_W {
+        FBM12_W { w: self }
+    }
+    #[doc = "Bit 13 - Filter mode"]
+    #[inline(always)]
+    pub fn fbm13(&mut self) -> FBM13_W {
+        FBM13_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/fmr.rs b/embassy-stm32/src/can/bx/pac/can/fmr.rs
new file mode 100644
index 000000000..5701af452
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/fmr.rs
@@ -0,0 +1,74 @@
+#[doc = "Reader of register FMR"]
+pub type R = crate::R<u32, super::FMR>;
+#[doc = "Writer for register FMR"]
+pub type W = crate::W<u32, super::FMR>;
+#[doc = "Register FMR `reset()`'s with value 0"]
+impl crate::ResetValue for super::FMR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `CAN2SB`"]
+pub type CAN2SB_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `CAN2SB`"]
+pub struct CAN2SB_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CAN2SB_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x3f << 8)) | (((value as u32) & 0x3f) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `FINIT`"]
+pub type FINIT_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FINIT`"]
+pub struct FINIT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FINIT_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 8:13 - CAN2SB"]
+    #[inline(always)]
+    pub fn can2sb(&self) -> CAN2SB_R {
+        CAN2SB_R::new(((self.bits >> 8) & 0x3f) as u8)
+    }
+    #[doc = "Bit 0 - FINIT"]
+    #[inline(always)]
+    pub fn finit(&self) -> FINIT_R {
+        FINIT_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 8:13 - CAN2SB"]
+    #[inline(always)]
+    pub fn can2sb(&mut self) -> CAN2SB_W {
+        CAN2SB_W { w: self }
+    }
+    #[doc = "Bit 0 - FINIT"]
+    #[inline(always)]
+    pub fn finit(&mut self) -> FINIT_W {
+        FINIT_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/fs1r.rs b/embassy-stm32/src/can/bx/pac/can/fs1r.rs
new file mode 100644
index 000000000..7bff8197d
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/fs1r.rs
@@ -0,0 +1,492 @@
+#[doc = "Reader of register FS1R"]
+pub type R = crate::R<u32, super::FS1R>;
+#[doc = "Writer for register FS1R"]
+pub type W = crate::W<u32, super::FS1R>;
+#[doc = "Register FS1R `reset()`'s with value 0"]
+impl crate::ResetValue for super::FS1R {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `FSC0`"]
+pub type FSC0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC0`"]
+pub struct FSC0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC1`"]
+pub type FSC1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC1`"]
+pub struct FSC1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC2`"]
+pub type FSC2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC2`"]
+pub struct FSC2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC3`"]
+pub type FSC3_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC3`"]
+pub struct FSC3_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC3_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC4`"]
+pub type FSC4_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC4`"]
+pub struct FSC4_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC4_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC5`"]
+pub type FSC5_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC5`"]
+pub struct FSC5_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC5_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC6`"]
+pub type FSC6_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC6`"]
+pub struct FSC6_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC6_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC7`"]
+pub type FSC7_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC7`"]
+pub struct FSC7_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC7_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC8`"]
+pub type FSC8_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC8`"]
+pub struct FSC8_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC8_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC9`"]
+pub type FSC9_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC9`"]
+pub struct FSC9_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC9_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC10`"]
+pub type FSC10_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC10`"]
+pub struct FSC10_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC10_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC11`"]
+pub type FSC11_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC11`"]
+pub struct FSC11_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC11_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC12`"]
+pub type FSC12_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC12`"]
+pub struct FSC12_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC12_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Reader of field `FSC13`"]
+pub type FSC13_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `FSC13`"]
+pub struct FSC13_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FSC13_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc0(&self) -> FSC0_R {
+        FSC0_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc1(&self) -> FSC1_R {
+        FSC1_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc2(&self) -> FSC2_R {
+        FSC2_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc3(&self) -> FSC3_R {
+        FSC3_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc4(&self) -> FSC4_R {
+        FSC4_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc5(&self) -> FSC5_R {
+        FSC5_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc6(&self) -> FSC6_R {
+        FSC6_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc7(&self) -> FSC7_R {
+        FSC7_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc8(&self) -> FSC8_R {
+        FSC8_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc9(&self) -> FSC9_R {
+        FSC9_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc10(&self) -> FSC10_R {
+        FSC10_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc11(&self) -> FSC11_R {
+        FSC11_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc12(&self) -> FSC12_R {
+        FSC12_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc13(&self) -> FSC13_R {
+        FSC13_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc0(&mut self) -> FSC0_W {
+        FSC0_W { w: self }
+    }
+    #[doc = "Bit 1 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc1(&mut self) -> FSC1_W {
+        FSC1_W { w: self }
+    }
+    #[doc = "Bit 2 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc2(&mut self) -> FSC2_W {
+        FSC2_W { w: self }
+    }
+    #[doc = "Bit 3 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc3(&mut self) -> FSC3_W {
+        FSC3_W { w: self }
+    }
+    #[doc = "Bit 4 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc4(&mut self) -> FSC4_W {
+        FSC4_W { w: self }
+    }
+    #[doc = "Bit 5 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc5(&mut self) -> FSC5_W {
+        FSC5_W { w: self }
+    }
+    #[doc = "Bit 6 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc6(&mut self) -> FSC6_W {
+        FSC6_W { w: self }
+    }
+    #[doc = "Bit 7 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc7(&mut self) -> FSC7_W {
+        FSC7_W { w: self }
+    }
+    #[doc = "Bit 8 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc8(&mut self) -> FSC8_W {
+        FSC8_W { w: self }
+    }
+    #[doc = "Bit 9 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc9(&mut self) -> FSC9_W {
+        FSC9_W { w: self }
+    }
+    #[doc = "Bit 10 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc10(&mut self) -> FSC10_W {
+        FSC10_W { w: self }
+    }
+    #[doc = "Bit 11 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc11(&mut self) -> FSC11_W {
+        FSC11_W { w: self }
+    }
+    #[doc = "Bit 12 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc12(&mut self) -> FSC12_W {
+        FSC12_W { w: self }
+    }
+    #[doc = "Bit 13 - Filter scale configuration"]
+    #[inline(always)]
+    pub fn fsc13(&mut self) -> FSC13_W {
+        FSC13_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/ier.rs b/embassy-stm32/src/can/bx/pac/can/ier.rs
new file mode 100644
index 000000000..3c57331b7
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/ier.rs
@@ -0,0 +1,1218 @@
+#[doc = "Reader of register IER"]
+pub type R = crate::R<u32, super::IER>;
+#[doc = "Writer for register IER"]
+pub type W = crate::W<u32, super::IER>;
+#[doc = "Register IER `reset()`'s with value 0"]
+impl crate::ResetValue for super::IER {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "SLKIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SLKIE_A {
+    #[doc = "0: No interrupt when SLAKI bit is set"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when SLAKI bit is set"]
+    ENABLED = 1,
+}
+impl From<SLKIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: SLKIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `SLKIE`"]
+pub type SLKIE_R = crate::R<bool, SLKIE_A>;
+impl SLKIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SLKIE_A {
+        match self.bits {
+            false => SLKIE_A::DISABLED,
+            true => SLKIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == SLKIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == SLKIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `SLKIE`"]
+pub struct SLKIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SLKIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: SLKIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt when SLAKI bit is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(SLKIE_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when SLAKI bit is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(SLKIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
+        self.w
+    }
+}
+#[doc = "WKUIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WKUIE_A {
+    #[doc = "0: No interrupt when WKUI is set"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when WKUI bit is set"]
+    ENABLED = 1,
+}
+impl From<WKUIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: WKUIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `WKUIE`"]
+pub type WKUIE_R = crate::R<bool, WKUIE_A>;
+impl WKUIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WKUIE_A {
+        match self.bits {
+            false => WKUIE_A::DISABLED,
+            true => WKUIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == WKUIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == WKUIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `WKUIE`"]
+pub struct WKUIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WKUIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: WKUIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt when WKUI is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(WKUIE_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when WKUI bit is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(WKUIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "ERRIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERRIE_A {
+    #[doc = "0: No interrupt will be generated when an error condition is pending in the CAN_ESR"]
+    DISABLED = 0,
+    #[doc = "1: An interrupt will be generation when an error condition is pending in the CAN_ESR"]
+    ENABLED = 1,
+}
+impl From<ERRIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: ERRIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `ERRIE`"]
+pub type ERRIE_R = crate::R<bool, ERRIE_A>;
+impl ERRIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ERRIE_A {
+        match self.bits {
+            false => ERRIE_A::DISABLED,
+            true => ERRIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ERRIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ERRIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `ERRIE`"]
+pub struct ERRIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ERRIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: ERRIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt will be generated when an error condition is pending in the CAN_ESR"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ERRIE_A::DISABLED)
+    }
+    #[doc = "An interrupt will be generation when an error condition is pending in the CAN_ESR"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ERRIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
+        self.w
+    }
+}
+#[doc = "LECIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LECIE_A {
+    #[doc = "0: ERRI bit will not be set when the error code in LEC\\[2:0\\]
+is set by hardware on error detection"]
+    DISABLED = 0,
+    #[doc = "1: ERRI bit will be set when the error code in LEC\\[2:0\\]
+is set by hardware on error detection"]
+    ENABLED = 1,
+}
+impl From<LECIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: LECIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `LECIE`"]
+pub type LECIE_R = crate::R<bool, LECIE_A>;
+impl LECIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LECIE_A {
+        match self.bits {
+            false => LECIE_A::DISABLED,
+            true => LECIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LECIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LECIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `LECIE`"]
+pub struct LECIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LECIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: LECIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "ERRI bit will not be set when the error code in LEC\\[2:0\\]
+is set by hardware on error detection"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(LECIE_A::DISABLED)
+    }
+    #[doc = "ERRI bit will be set when the error code in LEC\\[2:0\\]
+is set by hardware on error detection"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(LECIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "BOFIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BOFIE_A {
+    #[doc = "0: ERRI bit will not be set when BOFF is set"]
+    DISABLED = 0,
+    #[doc = "1: ERRI bit will be set when BOFF is set"]
+    ENABLED = 1,
+}
+impl From<BOFIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: BOFIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `BOFIE`"]
+pub type BOFIE_R = crate::R<bool, BOFIE_A>;
+impl BOFIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> BOFIE_A {
+        match self.bits {
+            false => BOFIE_A::DISABLED,
+            true => BOFIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == BOFIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == BOFIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `BOFIE`"]
+pub struct BOFIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> BOFIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: BOFIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "ERRI bit will not be set when BOFF is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(BOFIE_A::DISABLED)
+    }
+    #[doc = "ERRI bit will be set when BOFF is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(BOFIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "EPVIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EPVIE_A {
+    #[doc = "0: ERRI bit will not be set when EPVF is set"]
+    DISABLED = 0,
+    #[doc = "1: ERRI bit will be set when EPVF is set"]
+    ENABLED = 1,
+}
+impl From<EPVIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: EPVIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `EPVIE`"]
+pub type EPVIE_R = crate::R<bool, EPVIE_A>;
+impl EPVIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EPVIE_A {
+        match self.bits {
+            false => EPVIE_A::DISABLED,
+            true => EPVIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EPVIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EPVIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `EPVIE`"]
+pub struct EPVIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> EPVIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: EPVIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "ERRI bit will not be set when EPVF is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EPVIE_A::DISABLED)
+    }
+    #[doc = "ERRI bit will be set when EPVF is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EPVIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "EWGIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EWGIE_A {
+    #[doc = "0: ERRI bit will not be set when EWGF is set"]
+    DISABLED = 0,
+    #[doc = "1: ERRI bit will be set when EWGF is set"]
+    ENABLED = 1,
+}
+impl From<EWGIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: EWGIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `EWGIE`"]
+pub type EWGIE_R = crate::R<bool, EWGIE_A>;
+impl EWGIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EWGIE_A {
+        match self.bits {
+            false => EWGIE_A::DISABLED,
+            true => EWGIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EWGIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EWGIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `EWGIE`"]
+pub struct EWGIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> EWGIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: EWGIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "ERRI bit will not be set when EWGF is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EWGIE_A::DISABLED)
+    }
+    #[doc = "ERRI bit will be set when EWGF is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EWGIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "FOVIE1\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FOVIE1_A {
+    #[doc = "0: No interrupt when FOVR is set"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generation when FOVR is set"]
+    ENABLED = 1,
+}
+impl From<FOVIE1_A> for bool {
+    #[inline(always)]
+    fn from(variant: FOVIE1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FOVIE1`"]
+pub type FOVIE1_R = crate::R<bool, FOVIE1_A>;
+impl FOVIE1_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FOVIE1_A {
+        match self.bits {
+            false => FOVIE1_A::DISABLED,
+            true => FOVIE1_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FOVIE1_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FOVIE1_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `FOVIE1`"]
+pub struct FOVIE1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FOVIE1_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FOVIE1_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt when FOVR is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(FOVIE1_A::DISABLED)
+    }
+    #[doc = "Interrupt generation when FOVR is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(FOVIE1_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "FFIE1\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FFIE1_A {
+    #[doc = "0: No interrupt when FULL bit is set"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when FULL bit is set"]
+    ENABLED = 1,
+}
+impl From<FFIE1_A> for bool {
+    #[inline(always)]
+    fn from(variant: FFIE1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FFIE1`"]
+pub type FFIE1_R = crate::R<bool, FFIE1_A>;
+impl FFIE1_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FFIE1_A {
+        match self.bits {
+            false => FFIE1_A::DISABLED,
+            true => FFIE1_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FFIE1_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FFIE1_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `FFIE1`"]
+pub struct FFIE1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFIE1_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FFIE1_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt when FULL bit is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(FFIE1_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when FULL bit is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(FFIE1_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "FMPIE1\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FMPIE1_A {
+    #[doc = "0: No interrupt generated when state of FMP\\[1:0\\]
+bits are not 00b"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when state of FMP\\[1:0\\]
+bits are not 00b"]
+    ENABLED = 1,
+}
+impl From<FMPIE1_A> for bool {
+    #[inline(always)]
+    fn from(variant: FMPIE1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FMPIE1`"]
+pub type FMPIE1_R = crate::R<bool, FMPIE1_A>;
+impl FMPIE1_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FMPIE1_A {
+        match self.bits {
+            false => FMPIE1_A::DISABLED,
+            true => FMPIE1_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FMPIE1_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FMPIE1_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `FMPIE1`"]
+pub struct FMPIE1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FMPIE1_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FMPIE1_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt generated when state of FMP\\[1:0\\]
+bits are not 00b"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(FMPIE1_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when state of FMP\\[1:0\\]
+bits are not 00b"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(FMPIE1_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "FOVIE0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FOVIE0_A {
+    #[doc = "0: No interrupt when FOVR bit is set"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when FOVR bit is set"]
+    ENABLED = 1,
+}
+impl From<FOVIE0_A> for bool {
+    #[inline(always)]
+    fn from(variant: FOVIE0_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FOVIE0`"]
+pub type FOVIE0_R = crate::R<bool, FOVIE0_A>;
+impl FOVIE0_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FOVIE0_A {
+        match self.bits {
+            false => FOVIE0_A::DISABLED,
+            true => FOVIE0_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FOVIE0_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FOVIE0_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `FOVIE0`"]
+pub struct FOVIE0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FOVIE0_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FOVIE0_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt when FOVR bit is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(FOVIE0_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when FOVR bit is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(FOVIE0_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "FFIE0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FFIE0_A {
+    #[doc = "0: No interrupt when FULL bit is set"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when FULL bit is set"]
+    ENABLED = 1,
+}
+impl From<FFIE0_A> for bool {
+    #[inline(always)]
+    fn from(variant: FFIE0_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FFIE0`"]
+pub type FFIE0_R = crate::R<bool, FFIE0_A>;
+impl FFIE0_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FFIE0_A {
+        match self.bits {
+            false => FFIE0_A::DISABLED,
+            true => FFIE0_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FFIE0_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FFIE0_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `FFIE0`"]
+pub struct FFIE0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FFIE0_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FFIE0_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt when FULL bit is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(FFIE0_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when FULL bit is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(FFIE0_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "FMPIE0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FMPIE0_A {
+    #[doc = "0: No interrupt generated when state of FMP\\[1:0\\]
+bits are not 00"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when state of FMP\\[1:0\\]
+bits are not 00b"]
+    ENABLED = 1,
+}
+impl From<FMPIE0_A> for bool {
+    #[inline(always)]
+    fn from(variant: FMPIE0_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FMPIE0`"]
+pub type FMPIE0_R = crate::R<bool, FMPIE0_A>;
+impl FMPIE0_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FMPIE0_A {
+        match self.bits {
+            false => FMPIE0_A::DISABLED,
+            true => FMPIE0_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FMPIE0_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FMPIE0_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `FMPIE0`"]
+pub struct FMPIE0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FMPIE0_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FMPIE0_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt generated when state of FMP\\[1:0\\]
+bits are not 00"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(FMPIE0_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when state of FMP\\[1:0\\]
+bits are not 00b"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(FMPIE0_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "TMEIE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TMEIE_A {
+    #[doc = "0: No interrupt when RQCPx bit is set"]
+    DISABLED = 0,
+    #[doc = "1: Interrupt generated when RQCPx bit is set"]
+    ENABLED = 1,
+}
+impl From<TMEIE_A> for bool {
+    #[inline(always)]
+    fn from(variant: TMEIE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `TMEIE`"]
+pub type TMEIE_R = crate::R<bool, TMEIE_A>;
+impl TMEIE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TMEIE_A {
+        match self.bits {
+            false => TMEIE_A::DISABLED,
+            true => TMEIE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == TMEIE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == TMEIE_A::ENABLED
+    }
+}
+#[doc = "Write proxy for field `TMEIE`"]
+pub struct TMEIE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TMEIE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: TMEIE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "No interrupt when RQCPx bit is set"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(TMEIE_A::DISABLED)
+    }
+    #[doc = "Interrupt generated when RQCPx bit is set"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(TMEIE_A::ENABLED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 17 - SLKIE"]
+    #[inline(always)]
+    pub fn slkie(&self) -> SLKIE_R {
+        SLKIE_R::new(((self.bits >> 17) & 0x01) != 0)
+    }
+    #[doc = "Bit 16 - WKUIE"]
+    #[inline(always)]
+    pub fn wkuie(&self) -> WKUIE_R {
+        WKUIE_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - ERRIE"]
+    #[inline(always)]
+    pub fn errie(&self) -> ERRIE_R {
+        ERRIE_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - LECIE"]
+    #[inline(always)]
+    pub fn lecie(&self) -> LECIE_R {
+        LECIE_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - BOFIE"]
+    #[inline(always)]
+    pub fn bofie(&self) -> BOFIE_R {
+        BOFIE_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - EPVIE"]
+    #[inline(always)]
+    pub fn epvie(&self) -> EPVIE_R {
+        EPVIE_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - EWGIE"]
+    #[inline(always)]
+    pub fn ewgie(&self) -> EWGIE_R {
+        EWGIE_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - FOVIE1"]
+    #[inline(always)]
+    pub fn fovie1(&self) -> FOVIE1_R {
+        FOVIE1_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - FFIE1"]
+    #[inline(always)]
+    pub fn ffie1(&self) -> FFIE1_R {
+        FFIE1_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - FMPIE1"]
+    #[inline(always)]
+    pub fn fmpie1(&self) -> FMPIE1_R {
+        FMPIE1_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - FOVIE0"]
+    #[inline(always)]
+    pub fn fovie0(&self) -> FOVIE0_R {
+        FOVIE0_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - FFIE0"]
+    #[inline(always)]
+    pub fn ffie0(&self) -> FFIE0_R {
+        FFIE0_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - FMPIE0"]
+    #[inline(always)]
+    pub fn fmpie0(&self) -> FMPIE0_R {
+        FMPIE0_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 0 - TMEIE"]
+    #[inline(always)]
+    pub fn tmeie(&self) -> TMEIE_R {
+        TMEIE_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 17 - SLKIE"]
+    #[inline(always)]
+    pub fn slkie(&mut self) -> SLKIE_W {
+        SLKIE_W { w: self }
+    }
+    #[doc = "Bit 16 - WKUIE"]
+    #[inline(always)]
+    pub fn wkuie(&mut self) -> WKUIE_W {
+        WKUIE_W { w: self }
+    }
+    #[doc = "Bit 15 - ERRIE"]
+    #[inline(always)]
+    pub fn errie(&mut self) -> ERRIE_W {
+        ERRIE_W { w: self }
+    }
+    #[doc = "Bit 11 - LECIE"]
+    #[inline(always)]
+    pub fn lecie(&mut self) -> LECIE_W {
+        LECIE_W { w: self }
+    }
+    #[doc = "Bit 10 - BOFIE"]
+    #[inline(always)]
+    pub fn bofie(&mut self) -> BOFIE_W {
+        BOFIE_W { w: self }
+    }
+    #[doc = "Bit 9 - EPVIE"]
+    #[inline(always)]
+    pub fn epvie(&mut self) -> EPVIE_W {
+        EPVIE_W { w: self }
+    }
+    #[doc = "Bit 8 - EWGIE"]
+    #[inline(always)]
+    pub fn ewgie(&mut self) -> EWGIE_W {
+        EWGIE_W { w: self }
+    }
+    #[doc = "Bit 6 - FOVIE1"]
+    #[inline(always)]
+    pub fn fovie1(&mut self) -> FOVIE1_W {
+        FOVIE1_W { w: self }
+    }
+    #[doc = "Bit 5 - FFIE1"]
+    #[inline(always)]
+    pub fn ffie1(&mut self) -> FFIE1_W {
+        FFIE1_W { w: self }
+    }
+    #[doc = "Bit 4 - FMPIE1"]
+    #[inline(always)]
+    pub fn fmpie1(&mut self) -> FMPIE1_W {
+        FMPIE1_W { w: self }
+    }
+    #[doc = "Bit 3 - FOVIE0"]
+    #[inline(always)]
+    pub fn fovie0(&mut self) -> FOVIE0_W {
+        FOVIE0_W { w: self }
+    }
+    #[doc = "Bit 2 - FFIE0"]
+    #[inline(always)]
+    pub fn ffie0(&mut self) -> FFIE0_W {
+        FFIE0_W { w: self }
+    }
+    #[doc = "Bit 1 - FMPIE0"]
+    #[inline(always)]
+    pub fn fmpie0(&mut self) -> FMPIE0_W {
+        FMPIE0_W { w: self }
+    }
+    #[doc = "Bit 0 - TMEIE"]
+    #[inline(always)]
+    pub fn tmeie(&mut self) -> TMEIE_W {
+        TMEIE_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/mcr.rs b/embassy-stm32/src/can/bx/pac/can/mcr.rs
new file mode 100644
index 000000000..5e47c0901
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/mcr.rs
@@ -0,0 +1,356 @@
+#[doc = "Reader of register MCR"]
+pub type R = crate::R<u32, super::MCR>;
+#[doc = "Writer for register MCR"]
+pub type W = crate::W<u32, super::MCR>;
+#[doc = "Register MCR `reset()`'s with value 0"]
+impl crate::ResetValue for super::MCR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `DBF`"]
+pub type DBF_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `DBF`"]
+pub struct DBF_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DBF_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "Reader of field `RESET`"]
+pub type RESET_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `RESET`"]
+pub struct RESET_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RESET_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
+        self.w
+    }
+}
+#[doc = "Reader of field `TTCM`"]
+pub type TTCM_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TTCM`"]
+pub struct TTCM_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TTCM_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Reader of field `ABOM`"]
+pub type ABOM_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ABOM`"]
+pub struct ABOM_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ABOM_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Reader of field `AWUM`"]
+pub type AWUM_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `AWUM`"]
+pub struct AWUM_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> AWUM_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Reader of field `NART`"]
+pub type NART_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `NART`"]
+pub struct NART_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NART_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Reader of field `RFLM`"]
+pub type RFLM_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `RFLM`"]
+pub struct RFLM_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RFLM_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `TXFP`"]
+pub type TXFP_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TXFP`"]
+pub struct TXFP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXFP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Reader of field `SLEEP`"]
+pub type SLEEP_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `SLEEP`"]
+pub struct SLEEP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SLEEP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Reader of field `INRQ`"]
+pub type INRQ_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `INRQ`"]
+pub struct INRQ_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> INRQ_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 16 - DBF"]
+    #[inline(always)]
+    pub fn dbf(&self) -> DBF_R {
+        DBF_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - RESET"]
+    #[inline(always)]
+    pub fn reset(&self) -> RESET_R {
+        RESET_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - TTCM"]
+    #[inline(always)]
+    pub fn ttcm(&self) -> TTCM_R {
+        TTCM_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - ABOM"]
+    #[inline(always)]
+    pub fn abom(&self) -> ABOM_R {
+        ABOM_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - AWUM"]
+    #[inline(always)]
+    pub fn awum(&self) -> AWUM_R {
+        AWUM_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - NART"]
+    #[inline(always)]
+    pub fn nart(&self) -> NART_R {
+        NART_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - RFLM"]
+    #[inline(always)]
+    pub fn rflm(&self) -> RFLM_R {
+        RFLM_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - TXFP"]
+    #[inline(always)]
+    pub fn txfp(&self) -> TXFP_R {
+        TXFP_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - SLEEP"]
+    #[inline(always)]
+    pub fn sleep(&self) -> SLEEP_R {
+        SLEEP_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 0 - INRQ"]
+    #[inline(always)]
+    pub fn inrq(&self) -> INRQ_R {
+        INRQ_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 16 - DBF"]
+    #[inline(always)]
+    pub fn dbf(&mut self) -> DBF_W {
+        DBF_W { w: self }
+    }
+    #[doc = "Bit 15 - RESET"]
+    #[inline(always)]
+    pub fn reset(&mut self) -> RESET_W {
+        RESET_W { w: self }
+    }
+    #[doc = "Bit 7 - TTCM"]
+    #[inline(always)]
+    pub fn ttcm(&mut self) -> TTCM_W {
+        TTCM_W { w: self }
+    }
+    #[doc = "Bit 6 - ABOM"]
+    #[inline(always)]
+    pub fn abom(&mut self) -> ABOM_W {
+        ABOM_W { w: self }
+    }
+    #[doc = "Bit 5 - AWUM"]
+    #[inline(always)]
+    pub fn awum(&mut self) -> AWUM_W {
+        AWUM_W { w: self }
+    }
+    #[doc = "Bit 4 - NART"]
+    #[inline(always)]
+    pub fn nart(&mut self) -> NART_W {
+        NART_W { w: self }
+    }
+    #[doc = "Bit 3 - RFLM"]
+    #[inline(always)]
+    pub fn rflm(&mut self) -> RFLM_W {
+        RFLM_W { w: self }
+    }
+    #[doc = "Bit 2 - TXFP"]
+    #[inline(always)]
+    pub fn txfp(&mut self) -> TXFP_W {
+        TXFP_W { w: self }
+    }
+    #[doc = "Bit 1 - SLEEP"]
+    #[inline(always)]
+    pub fn sleep(&mut self) -> SLEEP_W {
+        SLEEP_W { w: self }
+    }
+    #[doc = "Bit 0 - INRQ"]
+    #[inline(always)]
+    pub fn inrq(&mut self) -> INRQ_W {
+        INRQ_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/msr.rs b/embassy-stm32/src/can/bx/pac/can/msr.rs
new file mode 100644
index 000000000..18e21c844
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/msr.rs
@@ -0,0 +1,160 @@
+#[doc = "Reader of register MSR"]
+pub type R = crate::R<u32, super::MSR>;
+#[doc = "Writer for register MSR"]
+pub type W = crate::W<u32, super::MSR>;
+#[doc = "Register MSR `reset()`'s with value 0"]
+impl crate::ResetValue for super::MSR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `RX`"]
+pub type RX_R = crate::R<bool, bool>;
+#[doc = "Reader of field `SAMP`"]
+pub type SAMP_R = crate::R<bool, bool>;
+#[doc = "Reader of field `RXM`"]
+pub type RXM_R = crate::R<bool, bool>;
+#[doc = "Reader of field `TXM`"]
+pub type TXM_R = crate::R<bool, bool>;
+#[doc = "Reader of field `SLAKI`"]
+pub type SLAKI_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `SLAKI`"]
+pub struct SLAKI_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SLAKI_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Reader of field `WKUI`"]
+pub type WKUI_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `WKUI`"]
+pub struct WKUI_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WKUI_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `ERRI`"]
+pub type ERRI_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ERRI`"]
+pub struct ERRI_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ERRI_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Reader of field `SLAK`"]
+pub type SLAK_R = crate::R<bool, bool>;
+#[doc = "Reader of field `INAK`"]
+pub type INAK_R = crate::R<bool, bool>;
+impl R {
+    #[doc = "Bit 11 - RX"]
+    #[inline(always)]
+    pub fn rx(&self) -> RX_R {
+        RX_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - SAMP"]
+    #[inline(always)]
+    pub fn samp(&self) -> SAMP_R {
+        SAMP_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - RXM"]
+    #[inline(always)]
+    pub fn rxm(&self) -> RXM_R {
+        RXM_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - TXM"]
+    #[inline(always)]
+    pub fn txm(&self) -> TXM_R {
+        TXM_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - SLAKI"]
+    #[inline(always)]
+    pub fn slaki(&self) -> SLAKI_R {
+        SLAKI_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - WKUI"]
+    #[inline(always)]
+    pub fn wkui(&self) -> WKUI_R {
+        WKUI_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - ERRI"]
+    #[inline(always)]
+    pub fn erri(&self) -> ERRI_R {
+        ERRI_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - SLAK"]
+    #[inline(always)]
+    pub fn slak(&self) -> SLAK_R {
+        SLAK_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 0 - INAK"]
+    #[inline(always)]
+    pub fn inak(&self) -> INAK_R {
+        INAK_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 4 - SLAKI"]
+    #[inline(always)]
+    pub fn slaki(&mut self) -> SLAKI_W {
+        SLAKI_W { w: self }
+    }
+    #[doc = "Bit 3 - WKUI"]
+    #[inline(always)]
+    pub fn wkui(&mut self) -> WKUI_W {
+        WKUI_W { w: self }
+    }
+    #[doc = "Bit 2 - ERRI"]
+    #[inline(always)]
+    pub fn erri(&mut self) -> ERRI_W {
+        ERRI_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/rfr.rs b/embassy-stm32/src/can/bx/pac/can/rfr.rs
new file mode 100644
index 000000000..6f5a960d1
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/rfr.rs
@@ -0,0 +1,281 @@
+#[doc = "Reader of register RF%sR"]
+pub type R = crate::R<u32, super::RFR>;
+#[doc = "Writer for register RF%sR"]
+pub type W = crate::W<u32, super::RFR>;
+#[doc = "Register RF%sR `reset()`'s with value 0"]
+impl crate::ResetValue for super::RFR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "RFOM0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RFOM_A {
+    #[doc = "1: Set by software to release the output mailbox of the FIFO"]
+    RELEASE = 1,
+}
+impl From<RFOM_A> for bool {
+    #[inline(always)]
+    fn from(variant: RFOM_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `RFOM`"]
+pub type RFOM_R = crate::R<bool, RFOM_A>;
+impl RFOM_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> crate::Variant<bool, RFOM_A> {
+        use crate::Variant::*;
+        match self.bits {
+            true => Val(RFOM_A::RELEASE),
+            i => Res(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `RELEASE`"]
+    #[inline(always)]
+    pub fn is_release(&self) -> bool {
+        *self == RFOM_A::RELEASE
+    }
+}
+#[doc = "Write proxy for field `RFOM`"]
+pub struct RFOM_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RFOM_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: RFOM_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "Set by software to release the output mailbox of the FIFO"]
+    #[inline(always)]
+    pub fn release(self) -> &'a mut W {
+        self.variant(RFOM_A::RELEASE)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "FOVR0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FOVR_A {
+    #[doc = "0: No FIFO x overrun"]
+    NOOVERRUN = 0,
+    #[doc = "1: FIFO x overrun"]
+    OVERRUN = 1,
+}
+impl From<FOVR_A> for bool {
+    #[inline(always)]
+    fn from(variant: FOVR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FOVR`"]
+pub type FOVR_R = crate::R<bool, FOVR_A>;
+impl FOVR_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FOVR_A {
+        match self.bits {
+            false => FOVR_A::NOOVERRUN,
+            true => FOVR_A::OVERRUN,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOOVERRUN`"]
+    #[inline(always)]
+    pub fn is_no_overrun(&self) -> bool {
+        *self == FOVR_A::NOOVERRUN
+    }
+    #[doc = "Checks if the value of the field is `OVERRUN`"]
+    #[inline(always)]
+    pub fn is_overrun(&self) -> bool {
+        *self == FOVR_A::OVERRUN
+    }
+}
+#[doc = "FOVR0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FOVR_AW {
+    #[doc = "1: Clear flag"]
+    CLEAR = 1,
+}
+impl From<FOVR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: FOVR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Write proxy for field `FOVR`"]
+pub struct FOVR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FOVR_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FOVR_AW) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "Clear flag"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(FOVR_AW::CLEAR)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "FULL0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FULL_A {
+    #[doc = "0: FIFO x is not full"]
+    NOTFULL = 0,
+    #[doc = "1: FIFO x is full"]
+    FULL = 1,
+}
+impl From<FULL_A> for bool {
+    #[inline(always)]
+    fn from(variant: FULL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `FULL`"]
+pub type FULL_R = crate::R<bool, FULL_A>;
+impl FULL_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FULL_A {
+        match self.bits {
+            false => FULL_A::NOTFULL,
+            true => FULL_A::FULL,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOTFULL`"]
+    #[inline(always)]
+    pub fn is_not_full(&self) -> bool {
+        *self == FULL_A::NOTFULL
+    }
+    #[doc = "Checks if the value of the field is `FULL`"]
+    #[inline(always)]
+    pub fn is_full(&self) -> bool {
+        *self == FULL_A::FULL
+    }
+}
+#[doc = "FULL0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FULL_AW {
+    #[doc = "1: Clear flag"]
+    CLEAR = 1,
+}
+impl From<FULL_AW> for bool {
+    #[inline(always)]
+    fn from(variant: FULL_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Write proxy for field `FULL`"]
+pub struct FULL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FULL_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FULL_AW) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "Clear flag"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(FULL_AW::CLEAR)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `FMP`"]
+pub type FMP_R = crate::R<u8, u8>;
+impl R {
+    #[doc = "Bit 5 - RFOM0"]
+    #[inline(always)]
+    pub fn rfom(&self) -> RFOM_R {
+        RFOM_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - FOVR0"]
+    #[inline(always)]
+    pub fn fovr(&self) -> FOVR_R {
+        FOVR_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - FULL0"]
+    #[inline(always)]
+    pub fn full(&self) -> FULL_R {
+        FULL_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bits 0:1 - FMP0"]
+    #[inline(always)]
+    pub fn fmp(&self) -> FMP_R {
+        FMP_R::new((self.bits & 0x03) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 5 - RFOM0"]
+    #[inline(always)]
+    pub fn rfom(&mut self) -> RFOM_W {
+        RFOM_W { w: self }
+    }
+    #[doc = "Bit 4 - FOVR0"]
+    #[inline(always)]
+    pub fn fovr(&mut self) -> FOVR_W {
+        FOVR_W { w: self }
+    }
+    #[doc = "Bit 3 - FULL0"]
+    #[inline(always)]
+    pub fn full(&mut self) -> FULL_W {
+        FULL_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/rx.rs b/embassy-stm32/src/can/bx/pac/can/rx.rs
new file mode 100644
index 000000000..dba344e7c
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/rx.rs
@@ -0,0 +1,36 @@
+#[doc = "CAN_RI0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rir](rir) module"]
+pub type RIR = crate::Reg<u32, _RIR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _RIR;
+#[doc = "`read()` method returns [rir::R](rir::R) reader structure"]
+impl crate::Readable for RIR {}
+#[doc = "CAN_RI0R"]
+pub mod rir;
+#[doc = "CAN_RDT0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdtr](rdtr) module"]
+pub type RDTR = crate::Reg<u32, _RDTR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _RDTR;
+#[doc = "`read()` method returns [rdtr::R](rdtr::R) reader structure"]
+impl crate::Readable for RDTR {}
+#[doc = "CAN_RDT0R"]
+pub mod rdtr;
+#[doc = "CAN_RDL0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdlr](rdlr) module"]
+pub type RDLR = crate::Reg<u32, _RDLR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _RDLR;
+#[doc = "`read()` method returns [rdlr::R](rdlr::R) reader structure"]
+impl crate::Readable for RDLR {}
+#[doc = "CAN_RDL0R"]
+pub mod rdlr;
+#[doc = "CAN_RDH0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdhr](rdhr) module"]
+pub type RDHR = crate::Reg<u32, _RDHR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _RDHR;
+#[doc = "`read()` method returns [rdhr::R](rdhr::R) reader structure"]
+impl crate::Readable for RDHR {}
+#[doc = "CAN_RDH0R"]
+pub mod rdhr;
diff --git a/embassy-stm32/src/can/bx/pac/can/rx/rdhr.rs b/embassy-stm32/src/can/bx/pac/can/rx/rdhr.rs
new file mode 100644
index 000000000..a0e6a52d0
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/rx/rdhr.rs
@@ -0,0 +1,32 @@
+#[doc = "Reader of register RDHR"]
+pub type R = crate::R<u32, super::RDHR>;
+#[doc = "Reader of field `DATA7`"]
+pub type DATA7_R = crate::R<u8, u8>;
+#[doc = "Reader of field `DATA6`"]
+pub type DATA6_R = crate::R<u8, u8>;
+#[doc = "Reader of field `DATA5`"]
+pub type DATA5_R = crate::R<u8, u8>;
+#[doc = "Reader of field `DATA4`"]
+pub type DATA4_R = crate::R<u8, u8>;
+impl R {
+    #[doc = "Bits 24:31 - DATA7"]
+    #[inline(always)]
+    pub fn data7(&self) -> DATA7_R {
+        DATA7_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - DATA6"]
+    #[inline(always)]
+    pub fn data6(&self) -> DATA6_R {
+        DATA6_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - DATA5"]
+    #[inline(always)]
+    pub fn data5(&self) -> DATA5_R {
+        DATA5_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 0:7 - DATA4"]
+    #[inline(always)]
+    pub fn data4(&self) -> DATA4_R {
+        DATA4_R::new((self.bits & 0xff) as u8)
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/rx/rdlr.rs b/embassy-stm32/src/can/bx/pac/can/rx/rdlr.rs
new file mode 100644
index 000000000..e61746669
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/rx/rdlr.rs
@@ -0,0 +1,32 @@
+#[doc = "Reader of register RDLR"]
+pub type R = crate::R<u32, super::RDLR>;
+#[doc = "Reader of field `DATA3`"]
+pub type DATA3_R = crate::R<u8, u8>;
+#[doc = "Reader of field `DATA2`"]
+pub type DATA2_R = crate::R<u8, u8>;
+#[doc = "Reader of field `DATA1`"]
+pub type DATA1_R = crate::R<u8, u8>;
+#[doc = "Reader of field `DATA0`"]
+pub type DATA0_R = crate::R<u8, u8>;
+impl R {
+    #[doc = "Bits 24:31 - DATA3"]
+    #[inline(always)]
+    pub fn data3(&self) -> DATA3_R {
+        DATA3_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - DATA2"]
+    #[inline(always)]
+    pub fn data2(&self) -> DATA2_R {
+        DATA2_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - DATA1"]
+    #[inline(always)]
+    pub fn data1(&self) -> DATA1_R {
+        DATA1_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 0:7 - DATA0"]
+    #[inline(always)]
+    pub fn data0(&self) -> DATA0_R {
+        DATA0_R::new((self.bits & 0xff) as u8)
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/rx/rdtr.rs b/embassy-stm32/src/can/bx/pac/can/rx/rdtr.rs
new file mode 100644
index 000000000..6778a7b4a
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/rx/rdtr.rs
@@ -0,0 +1,25 @@
+#[doc = "Reader of register RDTR"]
+pub type R = crate::R<u32, super::RDTR>;
+#[doc = "Reader of field `TIME`"]
+pub type TIME_R = crate::R<u16, u16>;
+#[doc = "Reader of field `FMI`"]
+pub type FMI_R = crate::R<u8, u8>;
+#[doc = "Reader of field `DLC`"]
+pub type DLC_R = crate::R<u8, u8>;
+impl R {
+    #[doc = "Bits 16:31 - TIME"]
+    #[inline(always)]
+    pub fn time(&self) -> TIME_R {
+        TIME_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+    #[doc = "Bits 8:15 - FMI"]
+    #[inline(always)]
+    pub fn fmi(&self) -> FMI_R {
+        FMI_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 0:3 - DLC"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DLC_R {
+        DLC_R::new((self.bits & 0x0f) as u8)
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/rx/rir.rs b/embassy-stm32/src/can/bx/pac/can/rx/rir.rs
new file mode 100644
index 000000000..c0e4248f4
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/rx/rir.rs
@@ -0,0 +1,100 @@
+#[doc = "Reader of register RIR"]
+pub type R = crate::R<u32, super::RIR>;
+#[doc = "Reader of field `STID`"]
+pub type STID_R = crate::R<u16, u16>;
+#[doc = "Reader of field `EXID`"]
+pub type EXID_R = crate::R<u32, u32>;
+#[doc = "IDE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IDE_A {
+    #[doc = "0: Standard identifier"]
+    STANDARD = 0,
+    #[doc = "1: Extended identifier"]
+    EXTENDED = 1,
+}
+impl From<IDE_A> for bool {
+    #[inline(always)]
+    fn from(variant: IDE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `IDE`"]
+pub type IDE_R = crate::R<bool, IDE_A>;
+impl IDE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IDE_A {
+        match self.bits {
+            false => IDE_A::STANDARD,
+            true => IDE_A::EXTENDED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `STANDARD`"]
+    #[inline(always)]
+    pub fn is_standard(&self) -> bool {
+        *self == IDE_A::STANDARD
+    }
+    #[doc = "Checks if the value of the field is `EXTENDED`"]
+    #[inline(always)]
+    pub fn is_extended(&self) -> bool {
+        *self == IDE_A::EXTENDED
+    }
+}
+#[doc = "RTR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTR_A {
+    #[doc = "0: Data frame"]
+    DATA = 0,
+    #[doc = "1: Remote frame"]
+    REMOTE = 1,
+}
+impl From<RTR_A> for bool {
+    #[inline(always)]
+    fn from(variant: RTR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `RTR`"]
+pub type RTR_R = crate::R<bool, RTR_A>;
+impl RTR_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RTR_A {
+        match self.bits {
+            false => RTR_A::DATA,
+            true => RTR_A::REMOTE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DATA`"]
+    #[inline(always)]
+    pub fn is_data(&self) -> bool {
+        *self == RTR_A::DATA
+    }
+    #[doc = "Checks if the value of the field is `REMOTE`"]
+    #[inline(always)]
+    pub fn is_remote(&self) -> bool {
+        *self == RTR_A::REMOTE
+    }
+}
+impl R {
+    #[doc = "Bits 21:31 - STID"]
+    #[inline(always)]
+    pub fn stid(&self) -> STID_R {
+        STID_R::new(((self.bits >> 21) & 0x07ff) as u16)
+    }
+    #[doc = "Bits 3:20 - EXID"]
+    #[inline(always)]
+    pub fn exid(&self) -> EXID_R {
+        EXID_R::new(((self.bits >> 3) & 0x0003_ffff) as u32)
+    }
+    #[doc = "Bit 2 - IDE"]
+    #[inline(always)]
+    pub fn ide(&self) -> IDE_R {
+        IDE_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - RTR"]
+    #[inline(always)]
+    pub fn rtr(&self) -> RTR_R {
+        RTR_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/tsr.rs b/embassy-stm32/src/can/bx/pac/can/tsr.rs
new file mode 100644
index 000000000..2527b36a5
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/tsr.rs
@@ -0,0 +1,575 @@
+#[doc = "Reader of register TSR"]
+pub type R = crate::R<u32, super::TSR>;
+#[doc = "Writer for register TSR"]
+pub type W = crate::W<u32, super::TSR>;
+#[doc = "Register TSR `reset()`'s with value 0"]
+impl crate::ResetValue for super::TSR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `LOW2`"]
+pub type LOW2_R = crate::R<bool, bool>;
+#[doc = "Reader of field `LOW1`"]
+pub type LOW1_R = crate::R<bool, bool>;
+#[doc = "Reader of field `LOW0`"]
+pub type LOW0_R = crate::R<bool, bool>;
+#[doc = "Reader of field `TME2`"]
+pub type TME2_R = crate::R<bool, bool>;
+#[doc = "Reader of field `TME1`"]
+pub type TME1_R = crate::R<bool, bool>;
+#[doc = "Reader of field `TME0`"]
+pub type TME0_R = crate::R<bool, bool>;
+#[doc = "Reader of field `CODE`"]
+pub type CODE_R = crate::R<u8, u8>;
+#[doc = "Reader of field `ABRQ2`"]
+pub type ABRQ2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ABRQ2`"]
+pub struct ABRQ2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ABRQ2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
+        self.w
+    }
+}
+#[doc = "Reader of field `TERR2`"]
+pub type TERR2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TERR2`"]
+pub struct TERR2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TERR2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
+        self.w
+    }
+}
+#[doc = "Reader of field `ALST2`"]
+pub type ALST2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ALST2`"]
+pub struct ALST2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ALST2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
+        self.w
+    }
+}
+#[doc = "Reader of field `TXOK2`"]
+pub type TXOK2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TXOK2`"]
+pub struct TXOK2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXOK2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
+        self.w
+    }
+}
+#[doc = "Reader of field `RQCP2`"]
+pub type RQCP2_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `RQCP2`"]
+pub struct RQCP2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RQCP2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "Reader of field `ABRQ1`"]
+pub type ABRQ1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ABRQ1`"]
+pub struct ABRQ1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ABRQ1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
+        self.w
+    }
+}
+#[doc = "Reader of field `TERR1`"]
+pub type TERR1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TERR1`"]
+pub struct TERR1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TERR1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Reader of field `ALST1`"]
+pub type ALST1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ALST1`"]
+pub struct ALST1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ALST1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Reader of field `TXOK1`"]
+pub type TXOK1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TXOK1`"]
+pub struct TXOK1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXOK1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Reader of field `RQCP1`"]
+pub type RQCP1_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `RQCP1`"]
+pub struct RQCP1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RQCP1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `ABRQ0`"]
+pub type ABRQ0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ABRQ0`"]
+pub struct ABRQ0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ABRQ0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Reader of field `TERR0`"]
+pub type TERR0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TERR0`"]
+pub struct TERR0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TERR0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Reader of field `ALST0`"]
+pub type ALST0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `ALST0`"]
+pub struct ALST0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ALST0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Reader of field `TXOK0`"]
+pub type TXOK0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TXOK0`"]
+pub struct TXOK0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXOK0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Reader of field `RQCP0`"]
+pub type RQCP0_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `RQCP0`"]
+pub struct RQCP0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RQCP0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 31 - Lowest priority flag for mailbox 2"]
+    #[inline(always)]
+    pub fn low2(&self) -> LOW2_R {
+        LOW2_R::new(((self.bits >> 31) & 0x01) != 0)
+    }
+    #[doc = "Bit 30 - Lowest priority flag for mailbox 1"]
+    #[inline(always)]
+    pub fn low1(&self) -> LOW1_R {
+        LOW1_R::new(((self.bits >> 30) & 0x01) != 0)
+    }
+    #[doc = "Bit 29 - Lowest priority flag for mailbox 0"]
+    #[inline(always)]
+    pub fn low0(&self) -> LOW0_R {
+        LOW0_R::new(((self.bits >> 29) & 0x01) != 0)
+    }
+    #[doc = "Bit 28 - Lowest priority flag for mailbox 2"]
+    #[inline(always)]
+    pub fn tme2(&self) -> TME2_R {
+        TME2_R::new(((self.bits >> 28) & 0x01) != 0)
+    }
+    #[doc = "Bit 27 - Lowest priority flag for mailbox 1"]
+    #[inline(always)]
+    pub fn tme1(&self) -> TME1_R {
+        TME1_R::new(((self.bits >> 27) & 0x01) != 0)
+    }
+    #[doc = "Bit 26 - Lowest priority flag for mailbox 0"]
+    #[inline(always)]
+    pub fn tme0(&self) -> TME0_R {
+        TME0_R::new(((self.bits >> 26) & 0x01) != 0)
+    }
+    #[doc = "Bits 24:25 - CODE"]
+    #[inline(always)]
+    pub fn code(&self) -> CODE_R {
+        CODE_R::new(((self.bits >> 24) & 0x03) as u8)
+    }
+    #[doc = "Bit 23 - ABRQ2"]
+    #[inline(always)]
+    pub fn abrq2(&self) -> ABRQ2_R {
+        ABRQ2_R::new(((self.bits >> 23) & 0x01) != 0)
+    }
+    #[doc = "Bit 19 - TERR2"]
+    #[inline(always)]
+    pub fn terr2(&self) -> TERR2_R {
+        TERR2_R::new(((self.bits >> 19) & 0x01) != 0)
+    }
+    #[doc = "Bit 18 - ALST2"]
+    #[inline(always)]
+    pub fn alst2(&self) -> ALST2_R {
+        ALST2_R::new(((self.bits >> 18) & 0x01) != 0)
+    }
+    #[doc = "Bit 17 - TXOK2"]
+    #[inline(always)]
+    pub fn txok2(&self) -> TXOK2_R {
+        TXOK2_R::new(((self.bits >> 17) & 0x01) != 0)
+    }
+    #[doc = "Bit 16 - RQCP2"]
+    #[inline(always)]
+    pub fn rqcp2(&self) -> RQCP2_R {
+        RQCP2_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - ABRQ1"]
+    #[inline(always)]
+    pub fn abrq1(&self) -> ABRQ1_R {
+        ABRQ1_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - TERR1"]
+    #[inline(always)]
+    pub fn terr1(&self) -> TERR1_R {
+        TERR1_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - ALST1"]
+    #[inline(always)]
+    pub fn alst1(&self) -> ALST1_R {
+        ALST1_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - TXOK1"]
+    #[inline(always)]
+    pub fn txok1(&self) -> TXOK1_R {
+        TXOK1_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - RQCP1"]
+    #[inline(always)]
+    pub fn rqcp1(&self) -> RQCP1_R {
+        RQCP1_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - ABRQ0"]
+    #[inline(always)]
+    pub fn abrq0(&self) -> ABRQ0_R {
+        ABRQ0_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - TERR0"]
+    #[inline(always)]
+    pub fn terr0(&self) -> TERR0_R {
+        TERR0_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - ALST0"]
+    #[inline(always)]
+    pub fn alst0(&self) -> ALST0_R {
+        ALST0_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - TXOK0"]
+    #[inline(always)]
+    pub fn txok0(&self) -> TXOK0_R {
+        TXOK0_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 0 - RQCP0"]
+    #[inline(always)]
+    pub fn rqcp0(&self) -> RQCP0_R {
+        RQCP0_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 23 - ABRQ2"]
+    #[inline(always)]
+    pub fn abrq2(&mut self) -> ABRQ2_W {
+        ABRQ2_W { w: self }
+    }
+    #[doc = "Bit 19 - TERR2"]
+    #[inline(always)]
+    pub fn terr2(&mut self) -> TERR2_W {
+        TERR2_W { w: self }
+    }
+    #[doc = "Bit 18 - ALST2"]
+    #[inline(always)]
+    pub fn alst2(&mut self) -> ALST2_W {
+        ALST2_W { w: self }
+    }
+    #[doc = "Bit 17 - TXOK2"]
+    #[inline(always)]
+    pub fn txok2(&mut self) -> TXOK2_W {
+        TXOK2_W { w: self }
+    }
+    #[doc = "Bit 16 - RQCP2"]
+    #[inline(always)]
+    pub fn rqcp2(&mut self) -> RQCP2_W {
+        RQCP2_W { w: self }
+    }
+    #[doc = "Bit 15 - ABRQ1"]
+    #[inline(always)]
+    pub fn abrq1(&mut self) -> ABRQ1_W {
+        ABRQ1_W { w: self }
+    }
+    #[doc = "Bit 11 - TERR1"]
+    #[inline(always)]
+    pub fn terr1(&mut self) -> TERR1_W {
+        TERR1_W { w: self }
+    }
+    #[doc = "Bit 10 - ALST1"]
+    #[inline(always)]
+    pub fn alst1(&mut self) -> ALST1_W {
+        ALST1_W { w: self }
+    }
+    #[doc = "Bit 9 - TXOK1"]
+    #[inline(always)]
+    pub fn txok1(&mut self) -> TXOK1_W {
+        TXOK1_W { w: self }
+    }
+    #[doc = "Bit 8 - RQCP1"]
+    #[inline(always)]
+    pub fn rqcp1(&mut self) -> RQCP1_W {
+        RQCP1_W { w: self }
+    }
+    #[doc = "Bit 7 - ABRQ0"]
+    #[inline(always)]
+    pub fn abrq0(&mut self) -> ABRQ0_W {
+        ABRQ0_W { w: self }
+    }
+    #[doc = "Bit 3 - TERR0"]
+    #[inline(always)]
+    pub fn terr0(&mut self) -> TERR0_W {
+        TERR0_W { w: self }
+    }
+    #[doc = "Bit 2 - ALST0"]
+    #[inline(always)]
+    pub fn alst0(&mut self) -> ALST0_W {
+        ALST0_W { w: self }
+    }
+    #[doc = "Bit 1 - TXOK0"]
+    #[inline(always)]
+    pub fn txok0(&mut self) -> TXOK0_W {
+        TXOK0_W { w: self }
+    }
+    #[doc = "Bit 0 - RQCP0"]
+    #[inline(always)]
+    pub fn rqcp0(&mut self) -> RQCP0_W {
+        RQCP0_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/tx.rs b/embassy-stm32/src/can/bx/pac/can/tx.rs
new file mode 100644
index 000000000..7b926bd14
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/tx.rs
@@ -0,0 +1,44 @@
+#[doc = "CAN_TI0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tir](tir) module"]
+pub type TIR = crate::Reg<u32, _TIR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _TIR;
+#[doc = "`read()` method returns [tir::R](tir::R) reader structure"]
+impl crate::Readable for TIR {}
+#[doc = "`write(|w| ..)` method takes [tir::W](tir::W) writer structure"]
+impl crate::Writable for TIR {}
+#[doc = "CAN_TI0R"]
+pub mod tir;
+#[doc = "CAN_TDT0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdtr](tdtr) module"]
+pub type TDTR = crate::Reg<u32, _TDTR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _TDTR;
+#[doc = "`read()` method returns [tdtr::R](tdtr::R) reader structure"]
+impl crate::Readable for TDTR {}
+#[doc = "`write(|w| ..)` method takes [tdtr::W](tdtr::W) writer structure"]
+impl crate::Writable for TDTR {}
+#[doc = "CAN_TDT0R"]
+pub mod tdtr;
+#[doc = "CAN_TDL0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdlr](tdlr) module"]
+pub type TDLR = crate::Reg<u32, _TDLR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _TDLR;
+#[doc = "`read()` method returns [tdlr::R](tdlr::R) reader structure"]
+impl crate::Readable for TDLR {}
+#[doc = "`write(|w| ..)` method takes [tdlr::W](tdlr::W) writer structure"]
+impl crate::Writable for TDLR {}
+#[doc = "CAN_TDL0R"]
+pub mod tdlr;
+#[doc = "CAN_TDH0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdhr](tdhr) module"]
+pub type TDHR = crate::Reg<u32, _TDHR>;
+#[allow(missing_docs)]
+#[doc(hidden)]
+pub struct _TDHR;
+#[doc = "`read()` method returns [tdhr::R](tdhr::R) reader structure"]
+impl crate::Readable for TDHR {}
+#[doc = "`write(|w| ..)` method takes [tdhr::W](tdhr::W) writer structure"]
+impl crate::Writable for TDHR {}
+#[doc = "CAN_TDH0R"]
+pub mod tdhr;
diff --git a/embassy-stm32/src/can/bx/pac/can/tx/tdhr.rs b/embassy-stm32/src/can/bx/pac/can/tx/tdhr.rs
new file mode 100644
index 000000000..240fa94f0
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/tx/tdhr.rs
@@ -0,0 +1,112 @@
+#[doc = "Reader of register TDHR"]
+pub type R = crate::R<u32, super::TDHR>;
+#[doc = "Writer for register TDHR"]
+pub type W = crate::W<u32, super::TDHR>;
+#[doc = "Register TDHR `reset()`'s with value 0"]
+impl crate::ResetValue for super::TDHR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `DATA7`"]
+pub type DATA7_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA7`"]
+pub struct DATA7_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA7_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
+        self.w
+    }
+}
+#[doc = "Reader of field `DATA6`"]
+pub type DATA6_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA6`"]
+pub struct DATA6_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA6_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
+        self.w
+    }
+}
+#[doc = "Reader of field `DATA5`"]
+pub type DATA5_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA5`"]
+pub struct DATA5_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA5_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `DATA4`"]
+pub type DATA4_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA4`"]
+pub struct DATA4_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA4_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 24:31 - DATA7"]
+    #[inline(always)]
+    pub fn data7(&self) -> DATA7_R {
+        DATA7_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - DATA6"]
+    #[inline(always)]
+    pub fn data6(&self) -> DATA6_R {
+        DATA6_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - DATA5"]
+    #[inline(always)]
+    pub fn data5(&self) -> DATA5_R {
+        DATA5_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 0:7 - DATA4"]
+    #[inline(always)]
+    pub fn data4(&self) -> DATA4_R {
+        DATA4_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 24:31 - DATA7"]
+    #[inline(always)]
+    pub fn data7(&mut self) -> DATA7_W {
+        DATA7_W { w: self }
+    }
+    #[doc = "Bits 16:23 - DATA6"]
+    #[inline(always)]
+    pub fn data6(&mut self) -> DATA6_W {
+        DATA6_W { w: self }
+    }
+    #[doc = "Bits 8:15 - DATA5"]
+    #[inline(always)]
+    pub fn data5(&mut self) -> DATA5_W {
+        DATA5_W { w: self }
+    }
+    #[doc = "Bits 0:7 - DATA4"]
+    #[inline(always)]
+    pub fn data4(&mut self) -> DATA4_W {
+        DATA4_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/tx/tdlr.rs b/embassy-stm32/src/can/bx/pac/can/tx/tdlr.rs
new file mode 100644
index 000000000..c4c855d46
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/tx/tdlr.rs
@@ -0,0 +1,112 @@
+#[doc = "Reader of register TDLR"]
+pub type R = crate::R<u32, super::TDLR>;
+#[doc = "Writer for register TDLR"]
+pub type W = crate::W<u32, super::TDLR>;
+#[doc = "Register TDLR `reset()`'s with value 0"]
+impl crate::ResetValue for super::TDLR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `DATA3`"]
+pub type DATA3_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA3`"]
+pub struct DATA3_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA3_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
+        self.w
+    }
+}
+#[doc = "Reader of field `DATA2`"]
+pub type DATA2_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA2`"]
+pub struct DATA2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA2_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
+        self.w
+    }
+}
+#[doc = "Reader of field `DATA1`"]
+pub type DATA1_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA1`"]
+pub struct DATA1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA1_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `DATA0`"]
+pub type DATA0_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DATA0`"]
+pub struct DATA0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DATA0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 24:31 - DATA3"]
+    #[inline(always)]
+    pub fn data3(&self) -> DATA3_R {
+        DATA3_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - DATA2"]
+    #[inline(always)]
+    pub fn data2(&self) -> DATA2_R {
+        DATA2_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - DATA1"]
+    #[inline(always)]
+    pub fn data1(&self) -> DATA1_R {
+        DATA1_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 0:7 - DATA0"]
+    #[inline(always)]
+    pub fn data0(&self) -> DATA0_R {
+        DATA0_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 24:31 - DATA3"]
+    #[inline(always)]
+    pub fn data3(&mut self) -> DATA3_W {
+        DATA3_W { w: self }
+    }
+    #[doc = "Bits 16:23 - DATA2"]
+    #[inline(always)]
+    pub fn data2(&mut self) -> DATA2_W {
+        DATA2_W { w: self }
+    }
+    #[doc = "Bits 8:15 - DATA1"]
+    #[inline(always)]
+    pub fn data1(&mut self) -> DATA1_W {
+        DATA1_W { w: self }
+    }
+    #[doc = "Bits 0:7 - DATA0"]
+    #[inline(always)]
+    pub fn data0(&mut self) -> DATA0_W {
+        DATA0_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/tx/tdtr.rs b/embassy-stm32/src/can/bx/pac/can/tx/tdtr.rs
new file mode 100644
index 000000000..310bca497
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/tx/tdtr.rs
@@ -0,0 +1,98 @@
+#[doc = "Reader of register TDTR"]
+pub type R = crate::R<u32, super::TDTR>;
+#[doc = "Writer for register TDTR"]
+pub type W = crate::W<u32, super::TDTR>;
+#[doc = "Register TDTR `reset()`'s with value 0"]
+impl crate::ResetValue for super::TDTR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `TIME`"]
+pub type TIME_R = crate::R<u16, u16>;
+#[doc = "Write proxy for field `TIME`"]
+pub struct TIME_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TIME_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
+        self.w
+    }
+}
+#[doc = "Reader of field `TGT`"]
+pub type TGT_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TGT`"]
+pub struct TGT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TGT_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Reader of field `DLC`"]
+pub type DLC_R = crate::R<u8, u8>;
+#[doc = "Write proxy for field `DLC`"]
+pub struct DLC_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DLC_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 16:31 - TIME"]
+    #[inline(always)]
+    pub fn time(&self) -> TIME_R {
+        TIME_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+    #[doc = "Bit 8 - TGT"]
+    #[inline(always)]
+    pub fn tgt(&self) -> TGT_R {
+        TGT_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bits 0:3 - DLC"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DLC_R {
+        DLC_R::new((self.bits & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 16:31 - TIME"]
+    #[inline(always)]
+    pub fn time(&mut self) -> TIME_W {
+        TIME_W { w: self }
+    }
+    #[doc = "Bit 8 - TGT"]
+    #[inline(always)]
+    pub fn tgt(&mut self) -> TGT_W {
+        TGT_W { w: self }
+    }
+    #[doc = "Bits 0:3 - DLC"]
+    #[inline(always)]
+    pub fn dlc(&mut self) -> DLC_W {
+        DLC_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/can/tx/tir.rs b/embassy-stm32/src/can/bx/pac/can/tx/tir.rs
new file mode 100644
index 000000000..12bc3d1f3
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/can/tx/tir.rs
@@ -0,0 +1,268 @@
+#[doc = "Reader of register TIR"]
+pub type R = crate::R<u32, super::TIR>;
+#[doc = "Writer for register TIR"]
+pub type W = crate::W<u32, super::TIR>;
+#[doc = "Register TIR `reset()`'s with value 0"]
+impl crate::ResetValue for super::TIR {
+    type Type = u32;
+    #[inline(always)]
+    fn reset_value() -> Self::Type {
+        0
+    }
+}
+#[doc = "Reader of field `STID`"]
+pub type STID_R = crate::R<u16, u16>;
+#[doc = "Write proxy for field `STID`"]
+pub struct STID_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> STID_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07ff << 21)) | (((value as u32) & 0x07ff) << 21);
+        self.w
+    }
+}
+#[doc = "Reader of field `EXID`"]
+pub type EXID_R = crate::R<u32, u32>;
+#[doc = "Write proxy for field `EXID`"]
+pub struct EXID_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> EXID_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x0003_ffff << 3)) | (((value as u32) & 0x0003_ffff) << 3);
+        self.w
+    }
+}
+#[doc = "IDE\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IDE_A {
+    #[doc = "0: Standard identifier"]
+    STANDARD = 0,
+    #[doc = "1: Extended identifier"]
+    EXTENDED = 1,
+}
+impl From<IDE_A> for bool {
+    #[inline(always)]
+    fn from(variant: IDE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `IDE`"]
+pub type IDE_R = crate::R<bool, IDE_A>;
+impl IDE_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IDE_A {
+        match self.bits {
+            false => IDE_A::STANDARD,
+            true => IDE_A::EXTENDED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `STANDARD`"]
+    #[inline(always)]
+    pub fn is_standard(&self) -> bool {
+        *self == IDE_A::STANDARD
+    }
+    #[doc = "Checks if the value of the field is `EXTENDED`"]
+    #[inline(always)]
+    pub fn is_extended(&self) -> bool {
+        *self == IDE_A::EXTENDED
+    }
+}
+#[doc = "Write proxy for field `IDE`"]
+pub struct IDE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IDE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: IDE_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "Standard identifier"]
+    #[inline(always)]
+    pub fn standard(self) -> &'a mut W {
+        self.variant(IDE_A::STANDARD)
+    }
+    #[doc = "Extended identifier"]
+    #[inline(always)]
+    pub fn extended(self) -> &'a mut W {
+        self.variant(IDE_A::EXTENDED)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "RTR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTR_A {
+    #[doc = "0: Data frame"]
+    DATA = 0,
+    #[doc = "1: Remote frame"]
+    REMOTE = 1,
+}
+impl From<RTR_A> for bool {
+    #[inline(always)]
+    fn from(variant: RTR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Reader of field `RTR`"]
+pub type RTR_R = crate::R<bool, RTR_A>;
+impl RTR_R {
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RTR_A {
+        match self.bits {
+            false => RTR_A::DATA,
+            true => RTR_A::REMOTE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DATA`"]
+    #[inline(always)]
+    pub fn is_data(&self) -> bool {
+        *self == RTR_A::DATA
+    }
+    #[doc = "Checks if the value of the field is `REMOTE`"]
+    #[inline(always)]
+    pub fn is_remote(&self) -> bool {
+        *self == RTR_A::REMOTE
+    }
+}
+#[doc = "Write proxy for field `RTR`"]
+pub struct RTR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RTR_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: RTR_A) -> &'a mut W {
+        {
+            self.bit(variant.into())
+        }
+    }
+    #[doc = "Data frame"]
+    #[inline(always)]
+    pub fn data(self) -> &'a mut W {
+        self.variant(RTR_A::DATA)
+    }
+    #[doc = "Remote frame"]
+    #[inline(always)]
+    pub fn remote(self) -> &'a mut W {
+        self.variant(RTR_A::REMOTE)
+    }
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Reader of field `TXRQ`"]
+pub type TXRQ_R = crate::R<bool, bool>;
+#[doc = "Write proxy for field `TXRQ`"]
+pub struct TXRQ_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXRQ_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 21:31 - STID"]
+    #[inline(always)]
+    pub fn stid(&self) -> STID_R {
+        STID_R::new(((self.bits >> 21) & 0x07ff) as u16)
+    }
+    #[doc = "Bits 3:20 - EXID"]
+    #[inline(always)]
+    pub fn exid(&self) -> EXID_R {
+        EXID_R::new(((self.bits >> 3) & 0x0003_ffff) as u32)
+    }
+    #[doc = "Bit 2 - IDE"]
+    #[inline(always)]
+    pub fn ide(&self) -> IDE_R {
+        IDE_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - RTR"]
+    #[inline(always)]
+    pub fn rtr(&self) -> RTR_R {
+        RTR_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 0 - TXRQ"]
+    #[inline(always)]
+    pub fn txrq(&self) -> TXRQ_R {
+        TXRQ_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 21:31 - STID"]
+    #[inline(always)]
+    pub fn stid(&mut self) -> STID_W {
+        STID_W { w: self }
+    }
+    #[doc = "Bits 3:20 - EXID"]
+    #[inline(always)]
+    pub fn exid(&mut self) -> EXID_W {
+        EXID_W { w: self }
+    }
+    #[doc = "Bit 2 - IDE"]
+    #[inline(always)]
+    pub fn ide(&mut self) -> IDE_W {
+        IDE_W { w: self }
+    }
+    #[doc = "Bit 1 - RTR"]
+    #[inline(always)]
+    pub fn rtr(&mut self) -> RTR_W {
+        RTR_W { w: self }
+    }
+    #[doc = "Bit 0 - TXRQ"]
+    #[inline(always)]
+    pub fn txrq(&mut self) -> TXRQ_W {
+        TXRQ_W { w: self }
+    }
+}
diff --git a/embassy-stm32/src/can/bx/pac/generic.rs b/embassy-stm32/src/can/bx/pac/generic.rs
new file mode 100644
index 000000000..749e7e204
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/generic.rs
@@ -0,0 +1,256 @@
+use core::marker;
+
+///This trait shows that register has `read` method
+///
+///Registers marked with `Writable` can be also `modify`'ed
+pub trait Readable {}
+
+///This trait shows that register has `write`, `write_with_zero` and `reset` method
+///
+///Registers marked with `Readable` can be also `modify`'ed
+pub trait Writable {}
+
+///Reset value of the register
+///
+///This value is initial value for `write` method.
+///It can be also directly writed to register by `reset` method.
+pub trait ResetValue {
+    ///Register size
+    type Type;
+    ///Reset value of the register
+    fn reset_value() -> Self::Type;
+}
+
+///This structure provides volatile access to register
+pub struct Reg<U, REG> {
+    register: vcell::VolatileCell<U>,
+    _marker: marker::PhantomData<REG>,
+}
+
+unsafe impl<U: Send, REG> Send for Reg<U, REG> {}
+
+impl<U, REG> Reg<U, REG>
+where
+    Self: Readable,
+    U: Copy,
+{
+    ///Reads the contents of `Readable` register
+    ///
+    ///You can read the contents of a register in such way:
+    ///```ignore
+    ///let bits = periph.reg.read().bits();
+    ///```
+    ///or get the content of a particular field of a register.
+    ///```ignore
+    ///let reader = periph.reg.read();
+    ///let bits = reader.field1().bits();
+    ///let flag = reader.field2().bit_is_set();
+    ///```
+    #[inline(always)]
+    pub fn read(&self) -> R<U, Self> {
+        R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        }
+    }
+}
+
+impl<U, REG> Reg<U, REG>
+where
+    Self: ResetValue<Type = U> + Writable,
+    U: Copy,
+{
+    ///Writes the reset value to `Writable` register
+    ///
+    ///Resets the register to its initial state
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(Self::reset_value())
+    }
+}
+
+impl<U, REG> Reg<U, REG>
+where
+    Self: ResetValue<Type = U> + Writable,
+    U: Copy,
+{
+    ///Writes bits to `Writable` register
+    ///
+    ///You can write raw bits into a register:
+    ///```ignore
+    ///periph.reg.write(|w| unsafe { w.bits(rawbits) });
+    ///```
+    ///or write only the fields you need:
+    ///```ignore
+    ///periph.reg.write(|w| w
+    ///    .field1().bits(newfield1bits)
+    ///    .field2().set_bit()
+    ///    .field3().variant(VARIANT)
+    ///);
+    ///```
+    ///Other fields will have reset value.
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<U, Self>) -> &mut W<U, Self>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: Self::reset_value(),
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+
+impl<U, REG> Reg<U, REG>
+where
+    Self: Writable,
+    U: Copy + Default,
+{
+    ///Writes Zero to `Writable` register
+    ///
+    ///Similar to `write`, but unused bits will contain 0.
+    #[inline(always)]
+    pub fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<U, Self>) -> &mut W<U, Self>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: U::default(),
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+
+impl<U, REG> Reg<U, REG>
+where
+    Self: Readable + Writable,
+    U: Copy,
+{
+    ///Modifies the contents of the register
+    ///
+    ///E.g. to do a read-modify-write sequence to change parts of a register:
+    ///```ignore
+    ///periph.reg.modify(|r, w| unsafe { w.bits(
+    ///   r.bits() | 3
+    ///) });
+    ///```
+    ///or
+    ///```ignore
+    ///periph.reg.modify(|_, w| w
+    ///    .field1().bits(newfield1bits)
+    ///    .field2().set_bit()
+    ///    .field3().variant(VARIANT)
+    ///);
+    ///```
+    ///Other fields will have value they had before call `modify`.
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R<U, Self>, &'w mut W<U, Self>) -> &'w mut W<U, Self>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &R {
+                    bits,
+                    _reg: marker::PhantomData,
+                },
+                &mut W {
+                    bits,
+                    _reg: marker::PhantomData,
+                },
+            )
+            .bits,
+        );
+    }
+}
+
+///Register/field reader
+///
+///Result of the [`read`](Reg::read) method of a register.
+///Also it can be used in the [`modify`](Reg::read) method
+pub struct R<U, T> {
+    pub(crate) bits: U,
+    _reg: marker::PhantomData<T>,
+}
+
+impl<U, T> R<U, T>
+where
+    U: Copy,
+{
+    ///Create new instance of reader
+    #[inline(always)]
+    pub(crate) fn new(bits: U) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+    ///Read raw bits from register/field
+    #[inline(always)]
+    pub fn bits(&self) -> U {
+        self.bits
+    }
+}
+
+impl<U, T, FI> PartialEq<FI> for R<U, T>
+where
+    U: PartialEq,
+    FI: Copy + Into<U>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+
+impl<FI> R<bool, FI> {
+    ///Value of the field as raw bits
+    #[inline(always)]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    ///Returns `true` if the bit is clear (0)
+    #[inline(always)]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    ///Returns `true` if the bit is set (1)
+    #[inline(always)]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+
+///Register writer
+///
+///Used as an argument to the closures in the [`write`](Reg::write) and [`modify`](Reg::modify) methods of the register
+pub struct W<U, REG> {
+    ///Writable bits
+    pub(crate) bits: U,
+    _reg: marker::PhantomData<REG>,
+}
+
+impl<U, REG> W<U, REG> {
+    ///Writes raw bits to the register
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: U) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+
+///Used if enumerated values cover not the whole range
+#[derive(Clone, Copy, PartialEq)]
+pub enum Variant<U, T> {
+    ///Expected variant
+    Val(T),
+    ///Raw bits
+    Res(U),
+}
diff --git a/embassy-stm32/src/can/bx/pac/mod.rs b/embassy-stm32/src/can/bx/pac/mod.rs
new file mode 100644
index 000000000..4360c2c73
--- /dev/null
+++ b/embassy-stm32/src/can/bx/pac/mod.rs
@@ -0,0 +1,9 @@
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![allow(unused)]
+use core::marker::PhantomData;
+use core::ops::Deref;
+
+#[doc = "Controller area network"]
+pub mod can;
+pub mod generic;