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-rw-r--r--embassy-embedded-hal/src/shared_bus/asynch/spi.rs126
1 files changed, 12 insertions, 114 deletions
diff --git a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
index b5549a6cd..030392183 100644
--- a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
+++ b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
@@ -56,62 +56,6 @@ where
56 type Error = SpiDeviceError<BUS::Error, CS::Error>; 56 type Error = SpiDeviceError<BUS::Error, CS::Error>;
57} 57}
58 58
59impl<M, BUS, CS> spi::SpiDeviceRead for SpiDevice<'_, M, BUS, CS>
60where
61 M: RawMutex,
62 BUS: spi::SpiBusRead,
63 CS: OutputPin,
64{
65 async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
66 let mut bus = self.bus.lock().await;
67 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
68
69 let op_res: Result<(), BUS::Error> = try {
70 for buf in operations {
71 bus.read(buf).await?;
72 }
73 };
74
75 // On failure, it's important to still flush and deassert CS.
76 let flush_res = bus.flush().await;
77 let cs_res = self.cs.set_high();
78
79 let op_res = op_res.map_err(SpiDeviceError::Spi)?;
80 flush_res.map_err(SpiDeviceError::Spi)?;
81 cs_res.map_err(SpiDeviceError::Cs)?;
82
83 Ok(op_res)
84 }
85}
86
87impl<M, BUS, CS> spi::SpiDeviceWrite for SpiDevice<'_, M, BUS, CS>
88where
89 M: RawMutex,
90 BUS: spi::SpiBusWrite,
91 CS: OutputPin,
92{
93 async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
94 let mut bus = self.bus.lock().await;
95 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
96
97 let op_res: Result<(), BUS::Error> = try {
98 for buf in operations {
99 bus.write(buf).await?;
100 }
101 };
102
103 // On failure, it's important to still flush and deassert CS.
104 let flush_res = bus.flush().await;
105 let cs_res = self.cs.set_high();
106
107 let op_res = op_res.map_err(SpiDeviceError::Spi)?;
108 flush_res.map_err(SpiDeviceError::Spi)?;
109 cs_res.map_err(SpiDeviceError::Cs)?;
110
111 Ok(op_res)
112 }
113}
114
115impl<M, BUS, CS> spi::SpiDevice for SpiDevice<'_, M, BUS, CS> 59impl<M, BUS, CS> spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
116where 60where
117 M: RawMutex, 61 M: RawMutex,
@@ -129,6 +73,12 @@ where
129 Operation::Write(buf) => bus.write(buf).await?, 73 Operation::Write(buf) => bus.write(buf).await?,
130 Operation::Transfer(read, write) => bus.transfer(read, write).await?, 74 Operation::Transfer(read, write) => bus.transfer(read, write).await?,
131 Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?, 75 Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?,
76 #[cfg(not(feature = "time"))]
77 Operation::DelayUs(_) => return Err(SpiDeviceError::DelayUsNotSupported),
78 #[cfg(feature = "time")]
79 Operation::DelayUs(us) => {
80 embassy_time::Timer::after(embassy_time::Duration::from_micros(*us as _)).await
81 }
132 } 82 }
133 } 83 }
134 }; 84 };
@@ -172,64 +122,6 @@ where
172 type Error = SpiDeviceError<BUS::Error, CS::Error>; 122 type Error = SpiDeviceError<BUS::Error, CS::Error>;
173} 123}
174 124
175impl<M, BUS, CS> spi::SpiDeviceWrite for SpiDeviceWithConfig<'_, M, BUS, CS>
176where
177 M: RawMutex,
178 BUS: spi::SpiBusWrite + SetConfig,
179 CS: OutputPin,
180{
181 async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
182 let mut bus = self.bus.lock().await;
183 bus.set_config(&self.config);
184 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
185
186 let op_res: Result<(), BUS::Error> = try {
187 for buf in operations {
188 bus.write(buf).await?;
189 }
190 };
191
192 // On failure, it's important to still flush and deassert CS.
193 let flush_res = bus.flush().await;
194 let cs_res = self.cs.set_high();
195
196 let op_res = op_res.map_err(SpiDeviceError::Spi)?;
197 flush_res.map_err(SpiDeviceError::Spi)?;
198 cs_res.map_err(SpiDeviceError::Cs)?;
199
200 Ok(op_res)
201 }
202}
203
204impl<M, BUS, CS> spi::SpiDeviceRead for SpiDeviceWithConfig<'_, M, BUS, CS>
205where
206 M: RawMutex,
207 BUS: spi::SpiBusRead + SetConfig,
208 CS: OutputPin,
209{
210 async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
211 let mut bus = self.bus.lock().await;
212 bus.set_config(&self.config);
213 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
214
215 let op_res: Result<(), BUS::Error> = try {
216 for buf in operations {
217 bus.read(buf).await?;
218 }
219 };
220
221 // On failure, it's important to still flush and deassert CS.
222 let flush_res = bus.flush().await;
223 let cs_res = self.cs.set_high();
224
225 let op_res = op_res.map_err(SpiDeviceError::Spi)?;
226 flush_res.map_err(SpiDeviceError::Spi)?;
227 cs_res.map_err(SpiDeviceError::Cs)?;
228
229 Ok(op_res)
230 }
231}
232
233impl<M, BUS, CS> spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS> 125impl<M, BUS, CS> spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
234where 126where
235 M: RawMutex, 127 M: RawMutex,
@@ -248,6 +140,12 @@ where
248 Operation::Write(buf) => bus.write(buf).await?, 140 Operation::Write(buf) => bus.write(buf).await?,
249 Operation::Transfer(read, write) => bus.transfer(read, write).await?, 141 Operation::Transfer(read, write) => bus.transfer(read, write).await?,
250 Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?, 142 Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?,
143 #[cfg(not(feature = "time"))]
144 Operation::DelayUs(_) => return Err(SpiDeviceError::DelayUsNotSupported),
145 #[cfg(feature = "time")]
146 Operation::DelayUs(us) => {
147 embassy_time::Timer::after(embassy_time::Duration::from_micros(*us as _)).await
148 }
251 } 149 }
252 } 150 }
253 }; 151 };
generated by cgit (git 2.34.1) at 2026-04-05 18:55:58 +0000