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-rw-r--r--embassy-executor/src/arch/riscv32.rs18
1 files changed, 13 insertions, 5 deletions
diff --git a/embassy-executor/src/arch/riscv32.rs b/embassy-executor/src/arch/riscv32.rs
index 76eb8b114..2a4b006da 100644
--- a/embassy-executor/src/arch/riscv32.rs
+++ b/embassy-executor/src/arch/riscv32.rs
@@ -55,11 +55,19 @@ impl Executor {
55 unsafe { 55 unsafe {
56 self.inner.poll(); 56 self.inner.poll();
57 // we do not care about race conditions between the load and store operations, interrupts 57 // we do not care about race conditions between the load and store operations, interrupts
58 // will only set this value to true. 58 //will only set this value to true.
59 // if there is work to do, loop back to polling 59 critical_section::with(|_| {
60 if !SIGNAL_WORK_THREAD_MODE.fetch_and(false, Ordering::SeqCst) { 60 // if there is work to do, loop back to polling
61 core::arch::asm!("wfi"); 61 // TODO can we relax this?
62 } 62 if SIGNAL_WORK_THREAD_MODE.load(Ordering::SeqCst) {
63 SIGNAL_WORK_THREAD_MODE.store(false, Ordering::SeqCst);
64 }
65 // if not, wait for interrupt
66 else {
67 core::arch::asm!("wfi");
68 }
69 });
70 // if an interrupt occurred while waiting, it will be serviced here
63 } 71 }
64 } 72 }
65 } 73 }