diff options
Diffstat (limited to 'embassy-imxrt/src/clocks.rs')
| -rw-r--r-- | embassy-imxrt/src/clocks.rs | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/embassy-imxrt/src/clocks.rs b/embassy-imxrt/src/clocks.rs index 1d36fb142..5be5f3925 100644 --- a/embassy-imxrt/src/clocks.rs +++ b/embassy-imxrt/src/clocks.rs | |||
| @@ -1561,7 +1561,8 @@ pub(crate) unsafe fn init(config: ClockConfig) -> Result<(), ClockError> { | |||
| 1561 | 1561 | ||
| 1562 | ///Trait to expose perph clocks | 1562 | ///Trait to expose perph clocks |
| 1563 | trait SealedSysconPeripheral { | 1563 | trait SealedSysconPeripheral { |
| 1564 | fn enable_and_reset_perph_clock(); | 1564 | fn enable_perph_clock(); |
| 1565 | fn reset_perph(); | ||
| 1565 | fn disable_perph_clock(); | 1566 | fn disable_perph_clock(); |
| 1566 | } | 1567 | } |
| 1567 | 1568 | ||
| @@ -1574,7 +1575,18 @@ pub trait SysconPeripheral: SealedSysconPeripheral + 'static {} | |||
| 1574 | /// | 1575 | /// |
| 1575 | /// Peripheral must not be in use. | 1576 | /// Peripheral must not be in use. |
| 1576 | pub fn enable_and_reset<T: SysconPeripheral>() { | 1577 | pub fn enable_and_reset<T: SysconPeripheral>() { |
| 1577 | T::enable_and_reset_perph_clock(); | 1578 | T::enable_perph_clock(); |
| 1579 | T::reset_perph(); | ||
| 1580 | } | ||
| 1581 | |||
| 1582 | /// Enables peripheral `T`. | ||
| 1583 | pub fn enable<T: SysconPeripheral>() { | ||
| 1584 | T::enable_perph_clock(); | ||
| 1585 | } | ||
| 1586 | |||
| 1587 | /// Reset peripheral `T`. | ||
| 1588 | pub fn reset<T: SysconPeripheral>() { | ||
| 1589 | T::reset_perph(); | ||
| 1578 | } | 1590 | } |
| 1579 | 1591 | ||
| 1580 | /// Disables peripheral `T`. | 1592 | /// Disables peripheral `T`. |
| @@ -1588,15 +1600,21 @@ pub fn disable<T: SysconPeripheral>() { | |||
| 1588 | macro_rules! impl_perph_clk { | 1600 | macro_rules! impl_perph_clk { |
| 1589 | ($peripheral:ident, $clkctl:ident, $clkreg:ident, $rstctl:ident, $rstreg:ident, $bit:expr) => { | 1601 | ($peripheral:ident, $clkctl:ident, $clkreg:ident, $rstctl:ident, $rstreg:ident, $bit:expr) => { |
| 1590 | impl SealedSysconPeripheral for crate::peripherals::$peripheral { | 1602 | impl SealedSysconPeripheral for crate::peripherals::$peripheral { |
| 1591 | fn enable_and_reset_perph_clock() { | 1603 | fn enable_perph_clock() { |
| 1592 | // SAFETY: unsafe needed to take pointers to Rstctl1 and Clkctl1 | 1604 | // SAFETY: unsafe needed to take pointers to Rstctl1 and Clkctl1 |
| 1593 | let cc1 = unsafe { pac::$clkctl::steal() }; | 1605 | let cc1 = unsafe { pac::$clkctl::steal() }; |
| 1594 | let rc1 = unsafe { pac::$rstctl::steal() }; | ||
| 1595 | 1606 | ||
| 1596 | paste! { | 1607 | paste! { |
| 1597 | // SAFETY: unsafe due to the use of bits() | 1608 | // SAFETY: unsafe due to the use of bits() |
| 1598 | cc1.[<$clkreg _set>]().write(|w| unsafe { w.bits(1 << $bit) }); | 1609 | cc1.[<$clkreg _set>]().write(|w| unsafe { w.bits(1 << $bit) }); |
| 1610 | } | ||
| 1611 | } | ||
| 1599 | 1612 | ||
| 1613 | fn reset_perph() { | ||
| 1614 | // SAFETY: unsafe needed to take pointers to Rstctl1 and Clkctl1 | ||
| 1615 | let rc1 = unsafe { pac::$rstctl::steal() }; | ||
| 1616 | |||
| 1617 | paste! { | ||
| 1600 | // SAFETY: unsafe due to the use of bits() | 1618 | // SAFETY: unsafe due to the use of bits() |
| 1601 | rc1.[<$rstreg _clr>]().write(|w| unsafe { w.bits(1 << $bit) }); | 1619 | rc1.[<$rstreg _clr>]().write(|w| unsafe { w.bits(1 << $bit) }); |
| 1602 | } | 1620 | } |
| @@ -1605,13 +1623,9 @@ macro_rules! impl_perph_clk { | |||
| 1605 | fn disable_perph_clock() { | 1623 | fn disable_perph_clock() { |
| 1606 | // SAFETY: unsafe needed to take pointers to Rstctl1 and Clkctl1 | 1624 | // SAFETY: unsafe needed to take pointers to Rstctl1 and Clkctl1 |
| 1607 | let cc1 = unsafe { pac::$clkctl::steal() }; | 1625 | let cc1 = unsafe { pac::$clkctl::steal() }; |
| 1608 | let rc1 = unsafe { pac::$rstctl::steal() }; | ||
| 1609 | 1626 | ||
| 1610 | paste! { | 1627 | paste! { |
| 1611 | // SAFETY: unsafe due to the use of bits() | 1628 | // SAFETY: unsafe due to the use of bits() |
| 1612 | rc1.[<$rstreg _set>]().write(|w| unsafe { w.bits(1 << $bit) }); | ||
| 1613 | |||
| 1614 | // SAFETY: unsafe due to the use of bits() | ||
| 1615 | cc1.[<$clkreg _clr>]().write(|w| unsafe { w.bits(1 << $bit) }); | 1629 | cc1.[<$clkreg _clr>]().write(|w| unsafe { w.bits(1 << $bit) }); |
| 1616 | } | 1630 | } |
| 1617 | } | 1631 | } |
