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-rw-r--r--embassy-imxrt/src/dma.rs8
-rw-r--r--embassy-imxrt/src/flexcomm/uart.rs4
2 files changed, 7 insertions, 5 deletions
diff --git a/embassy-imxrt/src/dma.rs b/embassy-imxrt/src/dma.rs
index e71a27e0e..eaa09870d 100644
--- a/embassy-imxrt/src/dma.rs
+++ b/embassy-imxrt/src/dma.rs
@@ -16,6 +16,8 @@ use crate::peripherals::DMA0;
16use crate::sealed::Sealed; 16use crate::sealed::Sealed;
17use crate::{BitIter, interrupt, pac, peripherals}; 17use crate::{BitIter, interrupt, pac, peripherals};
18 18
19pub(crate) const MAX_CHUNK_SIZE: usize = 1024;
20
19#[cfg(feature = "rt")] 21#[cfg(feature = "rt")]
20#[interrupt] 22#[interrupt]
21fn DMA0() { 23fn DMA0() {
@@ -69,7 +71,7 @@ pub(crate) unsafe fn init() {
69/// 71///
70/// SAFETY: Slice must point to a valid location reachable by DMA. 72/// SAFETY: Slice must point to a valid location reachable by DMA.
71pub unsafe fn read<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const W, to: *mut [W]) -> Transfer<'a, C> { 73pub unsafe fn read<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const W, to: *mut [W]) -> Transfer<'a, C> {
72 let count = ((to.len() / W::size() as usize) - 1) as isize; 74 let count = (to.len().div_ceil(W::size() as usize) - 1) as isize;
73 75
74 copy_inner( 76 copy_inner(
75 ch, 77 ch,
@@ -87,7 +89,7 @@ pub unsafe fn read<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const W, to:
87/// 89///
88/// SAFETY: Slice must point to a valid location reachable by DMA. 90/// SAFETY: Slice must point to a valid location reachable by DMA.
89pub unsafe fn write<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const [W], to: *mut W) -> Transfer<'a, C> { 91pub unsafe fn write<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const [W], to: *mut W) -> Transfer<'a, C> {
90 let count = ((from.len() / W::size() as usize) - 1) as isize; 92 let count = (from.len().div_ceil(W::size() as usize) - 1) as isize;
91 93
92 copy_inner( 94 copy_inner(
93 ch, 95 ch,
@@ -109,7 +111,7 @@ pub unsafe fn copy<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: &[W], to: &mu
109 let to_len = to.len(); 111 let to_len = to.len();
110 assert_eq!(from_len, to_len); 112 assert_eq!(from_len, to_len);
111 113
112 let count = ((from_len / W::size() as usize) - 1) as isize; 114 let count = (from_len.div_ceil(W::size() as usize) - 1) as isize;
113 115
114 copy_inner( 116 copy_inner(
115 ch, 117 ch,
diff --git a/embassy-imxrt/src/flexcomm/uart.rs b/embassy-imxrt/src/flexcomm/uart.rs
index 2b759ba84..d13b32e93 100644
--- a/embassy-imxrt/src/flexcomm/uart.rs
+++ b/embassy-imxrt/src/flexcomm/uart.rs
@@ -598,7 +598,7 @@ impl<'a> UartTx<'a, Async> {
598 regs.fifocfg().modify(|_, w| w.dmatx().disabled()); 598 regs.fifocfg().modify(|_, w| w.dmatx().disabled());
599 }); 599 });
600 600
601 for chunk in buf.chunks(1024) { 601 for chunk in buf.chunks(dma::MAX_CHUNK_SIZE) {
602 regs.fifocfg().modify(|_, w| w.dmatx().enabled()); 602 regs.fifocfg().modify(|_, w| w.dmatx().enabled());
603 603
604 let ch = self.tx_dma.as_mut().unwrap().reborrow(); 604 let ch = self.tx_dma.as_mut().unwrap().reborrow();
@@ -726,7 +726,7 @@ impl<'a> UartRx<'a, Async> {
726 regs.fifocfg().modify(|_, w| w.dmarx().disabled()); 726 regs.fifocfg().modify(|_, w| w.dmarx().disabled());
727 }); 727 });
728 728
729 for chunk in buf.chunks_mut(1024) { 729 for chunk in buf.chunks_mut(dma::MAX_CHUNK_SIZE) {
730 regs.fifocfg().modify(|_, w| w.dmarx().enabled()); 730 regs.fifocfg().modify(|_, w| w.dmarx().enabled());
731 731
732 let ch = self.rx_dma.as_mut().unwrap().reborrow(); 732 let ch = self.rx_dma.as_mut().unwrap().reborrow();