diff options
Diffstat (limited to 'embassy-mcxa/ram.ld')
| -rw-r--r-- | embassy-mcxa/ram.ld | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/embassy-mcxa/ram.ld b/embassy-mcxa/ram.ld new file mode 100644 index 000000000..816ab6819 --- /dev/null +++ b/embassy-mcxa/ram.ld | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | /* Simple RAM execution linker script for MCXA276 */ | ||
| 2 | MEMORY | ||
| 3 | { | ||
| 4 | RAM : ORIGIN = 0x20000000, LENGTH = 128K | ||
| 5 | } | ||
| 6 | |||
| 7 | /* Pull in device default interrupt symbol aliases (e.g., CMC = DefaultHandler) */ | ||
| 8 | INCLUDE device.x | ||
| 9 | |||
| 10 | |||
| 11 | /* Provide core exception weak aliases if not supplied by cortex-m-rt's link.x */ | ||
| 12 | PROVIDE(NonMaskableInt = DefaultHandler); | ||
| 13 | PROVIDE(HardFault = DefaultHandler); | ||
| 14 | PROVIDE(MemoryManagement = DefaultHandler); | ||
| 15 | PROVIDE(BusFault = DefaultHandler); | ||
| 16 | PROVIDE(UsageFault = DefaultHandler); | ||
| 17 | PROVIDE(SecureFault = DefaultHandler); | ||
| 18 | PROVIDE(SVCall = DefaultHandler); | ||
| 19 | PROVIDE(DebugMonitor = DefaultHandler); | ||
| 20 | PROVIDE(PendSV = DefaultHandler); | ||
| 21 | PROVIDE(SysTick = DefaultHandler); | ||
| 22 | |||
| 23 | /* In RAM-run we have no FLASH sidata; copy from sdata */ | ||
| 24 | __sidata = __sdata; | ||
| 25 | |||
| 26 | /* Ensure the PAC interrupt table is kept */ | ||
| 27 | EXTERN(__INTERRUPTS); | ||
| 28 | |||
| 29 | |||
| 30 | /* Pull in defmt's linker script to generate the defmt table that host decoders expect */ | ||
| 31 | INCLUDE defmt.x | ||
| 32 | |||
| 33 | ENTRY(Reset) | ||
| 34 | EXTERN(VECTOR_TABLE) | ||
| 35 | EXTERN(Reset) | ||
| 36 | EXTERN(main) | ||
| 37 | |||
| 38 | /* Define _stack_start at end of RAM BEFORE it's used in vector table */ | ||
| 39 | _stack_start = ORIGIN(RAM) + LENGTH(RAM); | ||
| 40 | |||
| 41 | SECTIONS | ||
| 42 | { | ||
| 43 | .vector_table ORIGIN(RAM) : | ||
| 44 | { | ||
| 45 | /* Slot 0: Initial stack pointer - use our explicitly set _stack_start */ | ||
| 46 | LONG(_stack_start); | ||
| 47 | /* Slot 1: Reset vector - address of Reset function with Thumb bit set */ | ||
| 48 | LONG(Reset | 1); | ||
| 49 | /* Cortex-M33 core exceptions (slots 2-14) */ | ||
| 50 | KEEP(*(.vector_table.exceptions)); | ||
| 51 | /* Peripheral interrupt vectors provided by PAC (slots 16+) */ | ||
| 52 | KEEP(*(.vector_table.interrupts)); | ||
| 53 | } > RAM | ||
| 54 | |||
| 55 | .text : | ||
| 56 | { | ||
| 57 | KEEP(*(.text.Reset)); | ||
| 58 | KEEP(*(.text.main)); | ||
| 59 | *(.text .text.*); | ||
| 60 | } > RAM | ||
| 61 | |||
| 62 | /* Keep defmt table and fragments so host decoders can find metadata */ | ||
| 63 | .defmt : | ||
| 64 | { | ||
| 65 | KEEP(*(.defmt)); | ||
| 66 | KEEP(*(.defmt.*)); | ||
| 67 | } > RAM | ||
| 68 | |||
| 69 | .rodata : | ||
| 70 | { | ||
| 71 | *(.rodata .rodata.*); | ||
| 72 | } > RAM | ||
| 73 | |||
| 74 | .data : | ||
| 75 | { | ||
| 76 | . = ALIGN(4); | ||
| 77 | __sdata = .; | ||
| 78 | *(.data .data.*); | ||
| 79 | . = ALIGN(4); | ||
| 80 | __edata = .; | ||
| 81 | } > RAM | ||
| 82 | |||
| 83 | /* Ensure RTT control block with "SEGGER RTT" signature is loaded to RAM */ | ||
| 84 | .rtt : | ||
| 85 | { | ||
| 86 | KEEP(*(.rtt)); | ||
| 87 | } > RAM | ||
| 88 | |||
| 89 | /* Place uninitialized buffers (like defmt-rtt) in RAM; load is fine for RAM-run */ | ||
| 90 | .uninit : | ||
| 91 | { | ||
| 92 | *(.uninit .uninit.*); | ||
| 93 | } > RAM | ||
| 94 | |||
| 95 | .bss : | ||
| 96 | { | ||
| 97 | . = ALIGN(4); | ||
| 98 | __sbss = .; | ||
| 99 | *(.bss .bss.*); | ||
| 100 | . = ALIGN(4); | ||
| 101 | __ebss = .; | ||
| 102 | } > RAM | ||
| 103 | |||
| 104 | /* Discard exception unwinding info */ | ||
| 105 | /DISCARD/ : | ||
| 106 | { | ||
| 107 | *(.ARM.exidx .ARM.exidx.*); | ||
| 108 | } | ||
| 109 | } | ||
