1 files changed, 119 insertions, 3 deletions

diff --git a/embassy-mcxa/src/interrupt.rs b/embassy-mcxa/src/interrupt.rs
index c960af7a2..7eabc6495 100644
--- a/embassy-mcxa/src/interrupt.rs
+++ b/embassy-mcxa/src/interrupt.rs
@@ -9,7 +9,10 @@
 mod generated {
     #[rustfmt::skip]
     embassy_hal_internal::interrupt_mod!(
+        ADC0,
         ADC1,
+        ADC2,
+        ADC3,
         DMA_CH0,
         DMA_CH1,
         DMA_CH2,
@@ -279,11 +282,48 @@ impl InterruptExt for Rtc {
         cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC)
     }
 }
+pub struct Adc0;
+pub const ADC0: Adc0 = Adc0;
 
-pub struct Adc;
-pub const ADC1: Adc = Adc;
+impl InterruptExt for Adc0 {
+    /// Clear any pending ADC0 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::ADC0);
+    }
+
+    /// Set NVIC priority for ADC0.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::ADC0, u8::from(priority));
+        }
+    }
 
-impl InterruptExt for Adc {
+    /// Enable ADC0 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::ADC0);
+    }
+
+    /// Disable ADC0 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::ADC0);
+    }
+
+    /// Check if ADC0 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC0)
+    }
+}
+
+pub struct Adc1;
+pub const ADC1: Adc1 = Adc1;
+
+impl InterruptExt for Adc1 {
     /// Clear any pending ADC1 in NVIC.
     #[inline]
     fn unpend(&self) {
@@ -318,6 +358,82 @@ impl InterruptExt for Adc {
     }
 }
 
+pub struct Adc2;
+pub const ADC2: Adc2 = Adc2;
+
+impl InterruptExt for Adc2 {
+    /// Clear any pending ADC2 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::ADC2);
+    }
+
+    /// Set NVIC priority for ADC2.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::ADC2, u8::from(priority));
+        }
+    }
+
+    /// Enable ADC2 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::ADC2);
+    }
+
+    /// Disable ADC2 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::ADC2);
+    }
+
+    /// Check if ADC2 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC2)
+    }
+}
+
+pub struct Adc3;
+pub const ADC3: Adc3 = Adc3;
+
+impl InterruptExt for Adc3 {
+    /// Clear any pending ADC3 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::ADC3);
+    }
+
+    /// Set NVIC priority for ADC3.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::ADC3, u8::from(priority));
+        }
+    }
+
+    /// Enable ADC3 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::ADC3);
+    }
+
+    /// Disable ADC3 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::ADC3);
+    }
+
+    /// Check if ADC3 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC3)
+    }
+}
+
 pub struct Gpio0;
 pub const GPIO0: Gpio0 = Gpio0;