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path: root/embassy-mcxa/src/reset_reason.rs
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Diffstat (limited to 'embassy-mcxa/src/reset_reason.rs')
-rw-r--r--embassy-mcxa/src/reset_reason.rs80
1 files changed, 39 insertions, 41 deletions
diff --git a/embassy-mcxa/src/reset_reason.rs b/embassy-mcxa/src/reset_reason.rs
index 1f5a0ec1f..f9a9ce096 100644
--- a/embassy-mcxa/src/reset_reason.rs
+++ b/embassy-mcxa/src/reset_reason.rs
@@ -7,47 +7,45 @@
7/// Reads the most recent reset reason from the Core Mode Controller 7/// Reads the most recent reset reason from the Core Mode Controller
8/// (CMC). 8/// (CMC).
9pub fn reset_reason() -> ResetReason { 9pub fn reset_reason() -> ResetReason {
10 critical_section::with(|_| { 10 let regs = unsafe { &*crate::pac::Cmc::steal() };
11 let regs = unsafe { &*crate::pac::Cmc::steal() }; 11
12 12 let srs = regs.srs().read();
13 let srs = regs.srs().read(); 13
14 14 if srs.wakeup().is_enabled() {
15 if srs.wakeup().is_enabled() { 15 ResetReason::WakeUp
16 ResetReason::WakeUp 16 } else if srs.por().bit_is_set() {
17 } else if srs.por().bit_is_set() { 17 ResetReason::Por
18 ResetReason::Por 18 } else if srs.vd().bit_is_set() {
19 } else if srs.vd().bit_is_set() { 19 ResetReason::VoltageDetect
20 ResetReason::VoltageDetect 20 } else if srs.warm().bit_is_set() {
21 } else if srs.warm().bit_is_set() { 21 ResetReason::Warm
22 ResetReason::Warm 22 } else if srs.fatal().bit_is_set() {
23 } else if srs.fatal().bit_is_set() { 23 ResetReason::Fatal
24 ResetReason::Fatal 24 } else if srs.pin().bit_is_set() {
25 } else if srs.pin().bit_is_set() { 25 ResetReason::Pin
26 ResetReason::Pin 26 } else if srs.dap().bit_is_set() {
27 } else if srs.dap().bit_is_set() { 27 ResetReason::Dap
28 ResetReason::Dap 28 } else if srs.rstack().bit_is_set() {
29 } else if srs.rstack().bit_is_set() { 29 ResetReason::ResetAckTimeout
30 ResetReason::ResetAckTimeout 30 } else if srs.lpack().bit_is_set() {
31 } else if srs.lpack().bit_is_set() { 31 ResetReason::LowPowerAckTimeout
32 ResetReason::LowPowerAckTimeout 32 } else if srs.scg().bit_is_set() {
33 } else if srs.scg().bit_is_set() { 33 ResetReason::SystemClockGeneration
34 ResetReason::SystemClockGeneration 34 } else if srs.wwdt0().bit_is_set() {
35 } else if srs.wwdt0().bit_is_set() { 35 ResetReason::Wwdt0
36 ResetReason::Wwdt0 36 } else if srs.sw().bit_is_set() {
37 } else if srs.sw().bit_is_set() { 37 ResetReason::Software
38 ResetReason::Software 38 } else if srs.lockup().bit_is_set() {
39 } else if srs.lockup().bit_is_set() { 39 ResetReason::Lockup
40 ResetReason::Lockup 40 } else if srs.cdog0().bit_is_set() {
41 } else if srs.cdog0().bit_is_set() { 41 ResetReason::Cdog0
42 ResetReason::Cdog0 42 } else if srs.cdog1().bit_is_set() {
43 } else if srs.cdog1().bit_is_set() { 43 ResetReason::Cdog1
44 ResetReason::Cdog1 44 } else if srs.jtag().bit_is_set() {
45 } else if srs.jtag().bit_is_set() { 45 ResetReason::Jtag
46 ResetReason::Jtag 46 } else {
47 } else { 47 ResetReason::Tamper
48 ResetReason::Tamper 48 }
49 }
50 })
51} 49}
52 50
53/// Indicates the type and source of the most recent reset. 51/// Indicates the type and source of the most recent reset.