10 files changed, 766 insertions, 296 deletions

diff --git a/embassy-mcxa/src/adc.rs b/embassy-mcxa/src/adc.rs
index 7475299ba..f88bb6b37 100644
--- a/embassy-mcxa/src/adc.rs
+++ b/embassy-mcxa/src/adc.rs
@@ -1,42 +1,23 @@
 //! ADC driver
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::future::Future;
+use core::marker::PhantomData;
 
 use embassy_hal_internal::{Peri, PeripheralType};
+use maitake_sync::WaitCell;
+use paste::paste;
 
 use crate::clocks::periph_helpers::{AdcClockSel, AdcConfig, Div4};
-use crate::clocks::{Gate, PoweredClock, enable_and_reset};
+use crate::clocks::{ClockError, Gate, PoweredClock, enable_and_reset};
+use crate::gpio::{GpioPin, SealedPin};
+use crate::interrupt::typelevel::{Handler, Interrupt};
 use crate::pac;
 use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres};
 use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts};
-use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode};
+use crate::pac::adc1::cmdl1::Mode;
 use crate::pac::adc1::ctrl::CalAvgs;
 use crate::pac::adc1::tctrl::{Tcmd, Tpri};
 
-type Regs = pac::adc1::RegisterBlock;
-
-static INTERRUPT_TRIGGERED: AtomicBool = AtomicBool::new(false);
-// Token-based instance pattern like embassy-imxrt
-pub trait Instance: Gate<MrccPeriphConfig = AdcConfig> + PeripheralType {
-    fn ptr() -> *const Regs;
-}
-
-/// Token for ADC1
-pub type Adc1 = crate::peripherals::ADC1;
-impl Instance for crate::peripherals::ADC1 {
-    #[inline(always)]
-    fn ptr() -> *const Regs {
-        pac::Adc1::ptr()
-    }
-}
-
-// Also implement Instance for the Peri wrapper type
-// impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> {
-//     #[inline(always)]
-//     fn ptr() -> *const Regs {
-//         pac::Adc1::ptr()
-//     }
-// }
-
+/// Trigger priority policy for ADC conversions.
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 #[repr(u8)]
 pub enum TriggerPriorityPolicy {
@@ -52,20 +33,36 @@ pub enum TriggerPriorityPolicy {
     TriggerPriorityExceptionDisabled = 16,
 }
 
+/// Configuration for the LPADC peripheral.
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub struct LpadcConfig {
+    /// Control system transition to Stop and Wait power modes while ADC is converting.
+    /// When enabled in Doze mode, immediate entries to Wait or Stop are allowed.
+    /// When disabled, the ADC will wait for the current averaging iteration/FIFO storage to complete before acknowledging stop or wait mode entry.
     pub enable_in_doze_mode: bool,
+    /// Auto-Calibration Averages.
     pub conversion_average_mode: CalAvgs,
+    /// ADC analog circuits are pre-enabled and ready to execute conversions without startup delays(at the cost of higher DC current consumption).
     pub enable_analog_preliminary: bool,
+    /// Power-up delay value (in ADC clock cycles)
     pub power_up_delay: u8,
+    /// Reference voltage source selection
     pub reference_voltage_source: Refsel,
+    /// Power configuration selection.
     pub power_level_mode: Pwrsel,
+    /// Trigger priority policy for handling multiple triggers
     pub trigger_priority_policy: TriggerPriorityPolicy,
+    /// Enables the ADC pausing function. When enabled, a programmable delay is inserted during command execution sequencing between LOOP iterations,
+    /// between commands in a sequence, and between conversions when command is executing in "Compare Until True" configuration.
     pub enable_conv_pause: bool,
+    /// Controls the duration of pausing during command execution sequencing. The pause delay is a count of (convPauseDelay*4) ADCK cycles.
+    /// Only available when ADC pausing function is enabled. The available value range is in 9-bit.
     pub conv_pause_delay: u16,
-    pub fifo_watermark: u8,
+    /// Power configuration (normal/deep sleep behavior)
     pub power: PoweredClock,
+    /// ADC clock source selection
     pub source: AdcClockSel,
+    /// Clock divider for ADC clock
     pub div: Div4,
 }
 
@@ -81,7 +78,6 @@ impl Default for LpadcConfig {
             trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
             enable_conv_pause: false,
             conv_pause_delay: 0,
-            fifo_watermark: 0,
             power: PoweredClock::NormalEnabledDeepSleepDisabled,
             source: AdcClockSel::FroLfDiv,
             div: Div4::no_div(),
@@ -89,10 +85,11 @@ impl Default for LpadcConfig {
     }
 }
 
+/// Configuration for a conversion command.
+///
+/// Defines the parameters for a single ADC conversion operation.
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub struct ConvCommandConfig {
-    pub sample_channel_mode: Ctype,
-    pub channel_number: Adch,
     pub chained_next_command_number: Next,
     pub enable_auto_channel_increment: bool,
     pub loop_count: u8,
@@ -105,6 +102,26 @@ pub struct ConvCommandConfig {
     pub enable_wait_trigger: bool,
 }
 
+impl Default for ConvCommandConfig {
+    fn default() -> Self {
+        ConvCommandConfig {
+            chained_next_command_number: Next::NoNextCmdTerminateOnFinish,
+            enable_auto_channel_increment: false,
+            loop_count: 0,
+            hardware_average_mode: Avgs::NoAverage,
+            sample_time_mode: Sts::Sample3p5,
+            hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult,
+            hardware_compare_value_high: 0,
+            hardware_compare_value_low: 0,
+            conversion_resolution_mode: Mode::Data12Bits,
+            enable_wait_trigger: false,
+        }
+    }
+}
+
+/// Configuration for a conversion trigger.
+///
+/// Defines how a trigger initiates ADC conversions.
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub struct ConvTriggerConfig {
     pub target_command_id: Tcmd,
@@ -113,32 +130,298 @@ pub struct ConvTriggerConfig {
     pub enable_hardware_trigger: bool,
 }
 
+impl Default for ConvTriggerConfig {
+    fn default() -> Self {
+        ConvTriggerConfig {
+            target_command_id: Tcmd::NotValid,
+            delay_power: 0,
+            priority: Tpri::HighestPriority,
+            enable_hardware_trigger: false,
+        }
+    }
+}
+
+/// Shorthand for `Result<T>`.
+pub type Result<T> = core::result::Result<T, Error>;
+
+/// ADC Error types
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// FIFO is empty, no conversion result available
+    FifoEmpty,
+    /// Invalid configuration
+    InvalidConfig,
+    /// Clock configuration error.
+    ClockSetup(ClockError),
+}
+
+/// Result of an ADC conversion.
+///
+/// Contains the conversion value and metadata about the conversion.
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub struct ConvResult {
-    pub command_id_source: u32,
-    pub loop_count_index: u32,
-    pub trigger_id_source: u32,
+    pub command_id_source: u8,
+    pub loop_count_index: u8,
+    pub trigger_id_source: u8,
     pub conv_value: u16,
 }
 
-pub struct Adc<'a, I: Instance> {
-    _inst: core::marker::PhantomData<&'a mut I>,
+/// ADC interrupt handler.
+pub struct InterruptHandler<I: Instance> {
+    _phantom: PhantomData<I>,
+}
+
+/// ADC driver instance.
+pub struct Adc<'a, M: ModeAdc> {
+    _inst: PhantomData<&'a mut ()>,
+    mode: M,
+
+    // The channel index of the pin used to create our ADC instance
+    channel_idx: u8,
+
+    // The register block of the ADC instance
+    info: &'static pac::adc0::RegisterBlock,
+}
+
+impl<'a> Adc<'a, Blocking> {
+    /// Create a new blocking instance of the ADC driver.
+    /// # Arguments
+    /// * `_inst` - ADC peripheral instance
+    /// * `pin` - GPIO pin to use for ADC
+    /// * `config` - ADC configuration
+    pub fn new_blocking<I: Instance>(
+        _inst: Peri<'a, I>,
+        pin: Peri<'a, impl AdcPin<I>>,
+        config: LpadcConfig,
+    ) -> Result<Self> {
+        Self::new_inner(_inst, pin, config, Blocking)
+    }
+
+    /// Enable ADC interrupts.
+    ///
+    /// Enables the interrupt sources specified in the bitmask.
+    ///
+    /// # Arguments
+    /// * `mask` - Bitmask of interrupt sources to enable
+    pub fn enable_interrupt(&mut self, mask: u32) {
+        self.info.ie().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
+    }
+
+    /// Disable ADC interrupts.
+    ///
+    /// Disables the interrupt sources specified in the bitmask.
+    ///
+    /// # Arguments
+    /// * `mask` - Bitmask of interrupt sources to disable
+    pub fn disable_interrupt(&mut self, mask: u32) {
+        self.info.ie().modify(|r, w| unsafe { w.bits(r.bits() & !mask) });
+    }
+
+    pub fn set_fifo_watermark(&mut self, watermark: u8) -> Result<()> {
+        if watermark > 0b111 {
+            return Err(Error::InvalidConfig);
+        }
+        self.info.fctrl0().modify(|_r, w| unsafe { w.fwmark().bits(watermark) });
+        Ok(())
+    }
+
+    /// Trigger ADC conversion(s) via software.
+    ///
+    /// Initiates conversion(s) for the trigger(s) specified in the bitmask.
+    /// Each bit in the mask corresponds to a trigger ID (bit 0 = trigger 0, etc.).
+    ///
+    /// # Arguments
+    /// * `trigger_id_mask` - Bitmask of trigger IDs to activate (bit N = trigger N)
+    ///
+    /// # Returns
+    /// * `Ok(())` if the triger mask was valid
+    /// * `Err(Error::InvalidConfig)` if the mask was greater than `0b1111`
+    pub fn do_software_trigger(&self, trigger_id_mask: u8) -> Result<()> {
+        if trigger_id_mask > 0b1111 {
+            return Err(Error::InvalidConfig);
+        }
+        self.info.swtrig().write(|w| unsafe { w.bits(trigger_id_mask as u32) });
+        Ok(())
+    }
+
+    /// Set conversion command configuration.
+    ///
+    /// Configures a conversion command slot with the specified parameters.
+    /// Commands define how conversions are performed (channel, resolution, etc.).
+    ///
+    /// # Arguments
+    /// * `index` - Command index (Must be in range 1..=7)
+    /// * `config` - Command configuration
+    ///
+    /// # Returns
+    /// * `Ok(())` if the command was configured successfully
+    /// * `Err(Error::InvalidConfig)` if the index is out of range
+    pub fn set_conv_command_config(&self, index: usize, config: &ConvCommandConfig) -> Result<()> {
+        self.set_conv_command_config_inner(index, config)
+    }
+
+    /// Set conversion trigger configuration.
+    ///
+    /// Configures a trigger to initiate conversions. Triggers can be
+    /// activated by software or hardware signals.
+    ///
+    /// # Arguments
+    /// * `trigger_id` - Trigger index (0..=3)
+    /// * `config` - Trigger configuration
+    pub fn set_conv_trigger_config(&self, trigger_id: usize, config: &ConvTriggerConfig) -> Result<()> {
+        self.set_conv_trigger_config_inner(trigger_id, config)
+    }
+
+    /// Reset the FIFO buffer.
+    ///
+    /// Clears all pending conversion results from the FIFO.
+    pub fn do_reset_fifo(&self) {
+        self.info.ctrl().modify(|_, w| w.rstfifo0().trigger_reset());
+    }
+
+    /// Get conversion result from FIFO.
+    ///
+    /// Reads and returns the next conversion result from the FIFO.
+    /// Returns `None` if the FIFO is empty.
+    ///
+    /// # Returns
+    /// - `Some(ConvResult)` if a result is available
+    /// - `Err(Error::FifoEmpty)` if the FIFO is empty
+    pub fn get_conv_result(&self) -> Result<ConvResult> {
+        self.get_conv_result_inner()
+    }
 }
 
-impl<'a, I: Instance> Adc<'a, I> {
-    /// initialize ADC
-    pub fn new(_inst: Peri<'a, I>, config: LpadcConfig) -> Self {
-        let adc = unsafe { &*I::ptr() };
+impl<'a> Adc<'a, Async> {
+    /// Initialize ADC with interrupt support.
+    ///
+    /// # Arguments
+    /// * `_inst` - ADC peripheral instance
+    /// * `pin` - GPIO pin to use for ADC
+    /// * `_irq` - Interrupt binding for this ADC instance
+    /// * `config` - ADC configuration
+    pub fn new_async<I: Instance>(
+        _inst: Peri<'a, I>,
+        pin: Peri<'a, impl AdcPin<I>>,
+        _irq: impl crate::interrupt::typelevel::Binding<I::Interrupt, InterruptHandler<I>> + 'a,
+        config: LpadcConfig,
+    ) -> Result<Self> {
+        let adc = Self::new_inner(_inst, pin, config, Async { waiter: I::wait_cell() })?;
+
+        I::Interrupt::unpend();
+        unsafe { I::Interrupt::enable() };
+
+        let cfg = ConvCommandConfig {
+            chained_next_command_number: Next::NoNextCmdTerminateOnFinish,
+            enable_auto_channel_increment: false,
+            loop_count: 0,
+            hardware_average_mode: Avgs::NoAverage,
+            sample_time_mode: Sts::Sample3p5,
+            hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult,
+            hardware_compare_value_high: 0,
+            hardware_compare_value_low: 0,
+            conversion_resolution_mode: Mode::Data16Bits,
+            enable_wait_trigger: false,
+        };
+
+        // We always use command 1, so this cannot fail
+        _ = adc.set_conv_command_config_inner(1, &cfg);
+
+        let cfg = ConvTriggerConfig {
+            target_command_id: Tcmd::ExecuteCmd1,
+            delay_power: 0,
+            priority: Tpri::HighestPriority,
+            enable_hardware_trigger: false,
+        };
+
+        // We always use trigger 0, so this cannot fail
+        _ = adc.set_conv_trigger_config_inner(0, &cfg);
+
+        // We always set the watermark to 0 (trigger when 1 is available)
+        I::ptr().fctrl0().modify(|_r, w| unsafe { w.fwmark().bits(0) });
+
+        Ok(adc)
+    }
+
+    /// Set the number of averages
+    pub fn set_averages(&mut self, avgs: Avgs) {
+        // TODO: we should probably return a result or wait for idle?
+        // "A write to a CMD buffer while that CMD buffer is controlling the ADC operation may cause unpredictable behavior."
+        self.info.cmdh1().modify(|_r, w| w.avgs().variant(avgs));
+    }
 
-        let _clock_freq = unsafe {
+    /// Set the sample time
+    pub fn set_sample_time(&mut self, st: Sts) {
+        // TODO: we should probably return a result or wait for idle?
+        // "A write to a CMD buffer while that CMD buffer is controlling the ADC operation may cause unpredictable behavior."
+        self.info.cmdh1().modify(|_r, w| w.sts().variant(st));
+    }
+
+    pub fn set_resolution(&mut self, mode: Mode) {
+        // TODO: we should probably return a result or wait for idle?
+        // "A write to a CMD buffer while that CMD buffer is controlling the ADC operation may cause unpredictable behavior."
+        self.info.cmdl1().modify(|_r, w| w.mode().variant(mode));
+    }
+
+    fn wait_idle(&mut self) -> impl Future<Output = core::result::Result<(), maitake_sync::Closed>> + use<'_> {
+        self.mode
+            .waiter
+            .wait_for(|| self.info.ie().read().fwmie0().bit_is_clear())
+    }
+
+    /// Read ADC value asynchronously.
+    ///
+    /// Performs a single ADC conversion and returns the result when the ADC interrupt is triggered.
+    ///
+    /// The function:
+    /// 1. Enables the FIFO watermark interrupt
+    /// 2. Triggers a software conversion on trigger 0
+    /// 3. Waits for the conversion to complete
+    /// 4. Returns the conversion result
+    ///
+    /// # Returns
+    /// 16-bit ADC conversion value
+    pub async fn read(&mut self) -> Result<u16> {
+        // If we cancelled a previous read, we might still be busy, wait
+        // until the interrupt is cleared (done by the interrupt)
+        _ = self.wait_idle().await;
+
+        // Clear the fifo
+        self.info.ctrl().modify(|_, w| w.rstfifo0().trigger_reset());
+
+        // Trigger a new conversion
+        self.info.ie().modify(|_r, w| w.fwmie0().set_bit());
+        self.info.swtrig().write(|w| w.swt0().set_bit());
+
+        // Wait for completion
+        _ = self.wait_idle().await;
+
+        self.get_conv_result_inner().map(|r| r.conv_value)
+    }
+}
+
+impl<'a, M: ModeAdc> Adc<'a, M> {
+    /// Internal initialization function shared by `new_async` and `new_blocking`.
+    fn new_inner<I: Instance, P: AdcPin<I>>(
+        _inst: Peri<'a, I>,
+        pin: Peri<'a, P>,
+        config: LpadcConfig,
+        mode: M,
+    ) -> Result<Self> {
+        let adc = I::ptr();
+
+        _ = unsafe {
             enable_and_reset::<I>(&AdcConfig {
                 power: config.power,
                 source: config.source,
                 div: config.div,
             })
-            .expect("Adc Init should not fail")
+            .map_err(Error::ClockSetup)?
         };
 
+        pin.mux();
+
         /* Reset the module. */
         adc.ctrl().modify(|_, w| w.rst().held_in_reset());
         adc.ctrl().modify(|_, w| w.rst().released_from_reset());
@@ -149,22 +432,14 @@ impl<'a, I: Instance> Adc<'a, I> {
         adc.ctrl().modify(|_, w| w.adcen().disabled());
 
         /* Configure the module generally. */
-        if config.enable_in_doze_mode {
-            adc.ctrl().modify(|_, w| w.dozen().enabled());
-        } else {
-            adc.ctrl().modify(|_, w| w.dozen().disabled());
-        }
+        adc.ctrl().modify(|_, w| w.dozen().bit(config.enable_in_doze_mode));
 
         /* Set calibration average mode. */
         adc.ctrl()
             .modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode));
 
         adc.cfg().write(|w| unsafe {
-            let w = if config.enable_analog_preliminary {
-                w.pwren().pre_enabled()
-            } else {
-                w
-            };
+            w.pwren().bit(config.enable_analog_preliminary);
 
             w.pudly()
                 .bits(config.power_up_delay)
@@ -214,32 +489,38 @@ impl<'a, I: Instance> Adc<'a, I> {
             adc.pause().write(|w| unsafe { w.bits(0) });
         }
 
-        adc.fctrl0()
-            .write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) });
+        adc.fctrl0().write(|w| unsafe { w.fwmark().bits(0) });
 
         // Enable ADC
         adc.ctrl().modify(|_, w| w.adcen().enabled());
 
-        Self {
-            _inst: core::marker::PhantomData,
-        }
-    }
-
-    pub fn deinit(&self) {
-        let adc = unsafe { &*I::ptr() };
-        adc.ctrl().modify(|_, w| w.adcen().disabled());
+        Ok(Self {
+            _inst: PhantomData,
+            mode,
+            channel_idx: P::CHANNEL,
+            info: adc,
+        })
     }
 
+    /// Perform offset calibration.
+    /// Waits for calibration to complete before returning.
     pub fn do_offset_calibration(&self) {
-        let adc = unsafe { &*I::ptr() };
         // Enable calibration mode
-        adc.ctrl()
+        self.info
+            .ctrl()
             .modify(|_, w| w.calofs().offset_calibration_request_pending());
 
         // Wait for calibration to complete (polling status register)
-        while adc.stat().read().cal_rdy().is_not_set() {}
+        while self.info.stat().read().cal_rdy().is_not_set() {}
     }
 
+    /// Calculate gain conversion result from gain adjustment factor.
+    ///
+    /// # Arguments
+    /// * `gain_adjustment` - Gain adjustment factor
+    ///
+    /// # Returns
+    /// Gain calibration register value
     pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32 {
         let mut gcra_array = [0u32; 17];
         let mut gcalr: u32 = 0;
@@ -258,102 +539,80 @@ impl<'a, I: Instance> Adc<'a, I> {
         gcalr
     }
 
+    /// Perform automatic gain calibration.
     pub fn do_auto_calibration(&self) {
-        let adc = unsafe { &*I::ptr() };
-        adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending());
+        self.info
+            .ctrl()
+            .modify(|_, w| w.cal_req().calibration_request_pending());
 
-        while adc.gcc0().read().rdy().is_gain_cal_not_valid() {}
+        while self.info.gcc0().read().rdy().is_gain_cal_not_valid() {}
 
-        let mut gcca = adc.gcc0().read().gain_cal().bits() as u32;
-        if gcca & ((0xFFFF + 1) >> 1) != 0 {
+        let mut gcca = self.info.gcc0().read().gain_cal().bits() as u32;
+        if gcca & 0x8000 != 0 {
             gcca |= !0xFFFF;
         }
 
         let gcra = 131072.0 / (131072.0 - gcca as f32);
 
         // Write to GCR0
-        adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) });
+        self.info
+            .gcr0()
+            .write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) });
 
-        adc.gcr0().modify(|_, w| w.rdy().set_bit());
+        self.info.gcr0().modify(|_, w| w.rdy().set_bit());
 
         // Wait for calibration to complete (polling status register)
-        while adc.stat().read().cal_rdy().is_not_set() {}
+        while self.info.stat().read().cal_rdy().is_not_set() {}
     }
 
-    pub fn do_software_trigger(&self, trigger_id_mask: u32) {
-        let adc = unsafe { &*I::ptr() };
-        adc.swtrig().write(|w| unsafe { w.bits(trigger_id_mask) });
-    }
+    fn set_conv_command_config_inner(&self, index: usize, config: &ConvCommandConfig) -> Result<()> {
+        let (cmdl, cmdh) = match index {
+            1 => (self.info.cmdl1(), self.info.cmdh1()),
+            2 => (self.info.cmdl2(), self.info.cmdh2()),
+            3 => (self.info.cmdl3(), self.info.cmdh3()),
+            4 => (self.info.cmdl4(), self.info.cmdh4()),
+            5 => (self.info.cmdl5(), self.info.cmdh5()),
+            6 => (self.info.cmdl6(), self.info.cmdh6()),
+            7 => (self.info.cmdl7(), self.info.cmdh7()),
+            _ => return Err(Error::InvalidConfig),
+        };
 
-    pub fn get_default_conv_command_config(&self) -> ConvCommandConfig {
-        ConvCommandConfig {
-            sample_channel_mode: Ctype::SingleEndedASideChannel,
-            channel_number: Adch::SelectCh0,
-            chained_next_command_number: Next::NoNextCmdTerminateOnFinish,
-            enable_auto_channel_increment: false,
-            loop_count: 0,
-            hardware_average_mode: Avgs::NoAverage,
-            sample_time_mode: Sts::Sample3p5,
-            hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult,
-            hardware_compare_value_high: 0,
-            hardware_compare_value_low: 0,
-            conversion_resolution_mode: Mode::Data12Bits,
-            enable_wait_trigger: false,
-        }
-    }
+        cmdl.write(|w| {
+            unsafe {
+                w.adch().bits(self.channel_idx);
+            }
+            w.mode().variant(config.conversion_resolution_mode)
+        });
 
-    //TBD Need to add cmdlx and cmdhx with x {2..7}
-    pub fn set_conv_command_config(&self, index: u32, config: &ConvCommandConfig) {
-        let adc = unsafe { &*I::ptr() };
-
-        match index {
-            1 => {
-                adc.cmdl1().write(|w| {
-                    w.adch()
-                        .variant(config.channel_number)
-                        .mode()
-                        .variant(config.conversion_resolution_mode)
-                });
-                adc.cmdh1().write(|w| unsafe {
-                    w.next()
-                        .variant(config.chained_next_command_number)
-                        .loop_()
-                        .bits(config.loop_count)
-                        .avgs()
-                        .variant(config.hardware_average_mode)
-                        .sts()
-                        .variant(config.sample_time_mode)
-                        .cmpen()
-                        .variant(config.hardware_compare_mode);
-                    if config.enable_wait_trigger {
-                        w.wait_trig().enabled();
-                    }
-                    if config.enable_auto_channel_increment {
-                        w.lwi().enabled();
-                    }
-                    w
-                });
+        cmdh.write(|w| {
+            w.next().variant(config.chained_next_command_number);
+            unsafe {
+                w.loop_().bits(config.loop_count);
             }
-            _ => panic!("Invalid command index: must be between 1 and 7"),
-        }
+            w.avgs().variant(config.hardware_average_mode);
+            w.sts().variant(config.sample_time_mode);
+            w.cmpen().variant(config.hardware_compare_mode);
+            w.wait_trig().bit(config.enable_wait_trigger);
+            w.lwi().bit(config.enable_auto_channel_increment);
+            w
+        });
+
+        Ok(())
     }
 
-    pub fn get_default_conv_trigger_config(&self) -> ConvTriggerConfig {
-        ConvTriggerConfig {
-            target_command_id: Tcmd::NotValid,
-            delay_power: 0,
-            priority: Tpri::HighestPriority,
-            enable_hardware_trigger: false,
+    fn set_conv_trigger_config_inner(&self, trigger_id: usize, config: &ConvTriggerConfig) -> Result<()> {
+        // 0..4 are valid
+        if trigger_id >= 4 {
+            return Err(Error::InvalidConfig);
         }
-    }
 
-    pub fn set_conv_trigger_config(&self, trigger_id: usize, config: &ConvTriggerConfig) {
-        let adc = unsafe { &*I::ptr() };
-        let tctrl = &adc.tctrl(trigger_id);
+        let tctrl = &self.info.tctrl(trigger_id);
 
-        tctrl.write(|w| unsafe {
-            let w = w.tcmd().variant(config.target_command_id);
-            let w = w.tdly().bits(config.delay_power);
+        tctrl.write(|w| {
+            w.tcmd().variant(config.target_command_id);
+            unsafe {
+                w.tdly().bits(config.delay_power);
+            }
             w.tpri().variant(config.priority);
             if config.enable_hardware_trigger {
                 w.hten().enabled()
@@ -361,49 +620,230 @@ impl<'a, I: Instance> Adc<'a, I> {
                 w
             }
         });
-    }
 
-    pub fn do_reset_fifo(&self) {
-        let adc = unsafe { &*I::ptr() };
-        adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset());
+        Ok(())
     }
 
-    pub fn enable_interrupt(&self, mask: u32) {
-        let adc = unsafe { &*I::ptr() };
-        adc.ie().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
-        INTERRUPT_TRIGGERED.store(false, Ordering::SeqCst);
-    }
+    /// Get conversion result from FIFO.
+    ///
+    /// Reads and returns the next conversion result from the FIFO.
+    /// Returns `None` if the FIFO is empty.
+    ///
+    /// # Returns
+    /// - `Some(ConvResult)` if a result is available
+    /// - `Err(Error::FifoEmpty)` if the FIFO is empty
+    fn get_conv_result_inner(&self) -> Result<ConvResult> {
+        let fifo = self.info.resfifo0().read();
+        if !fifo.valid().is_valid() {
+            return Err(Error::FifoEmpty);
+        }
 
-    pub fn is_interrupt_triggered(&self) -> bool {
-        INTERRUPT_TRIGGERED.load(Ordering::Relaxed)
+        Ok(ConvResult {
+            command_id_source: fifo.cmdsrc().bits(),
+            loop_count_index: fifo.loopcnt().bits(),
+            trigger_id_source: fifo.tsrc().bits(),
+            conv_value: fifo.d().bits(),
+        })
     }
 }
 
-pub fn get_conv_result() -> Option<ConvResult> {
-    let adc = unsafe { &*pac::Adc1::ptr() };
-    let fifo = adc.resfifo0().read().bits();
-    const VALID_MASK: u32 = 1 << 31;
-    if fifo & VALID_MASK == 0 {
-        return None;
+impl<T: Instance> Handler<T::Interrupt> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        T::ptr().ie().modify(|_r, w| w.fwmie0().clear_bit());
+        T::wait_cell().wake();
     }
+}
 
-    Some(ConvResult {
-        command_id_source: (fifo >> 24) & 0x0F,
-        loop_count_index: (fifo >> 20) & 0x0F,
-        trigger_id_source: (fifo >> 16) & 0x0F,
-        conv_value: (fifo & 0xFFFF) as u16,
-    })
+mod sealed {
+    /// Seal a trait
+    pub trait Sealed {}
 }
 
-pub fn on_interrupt() {
-    if get_conv_result().is_some() {
-        INTERRUPT_TRIGGERED.store(true, Ordering::SeqCst);
-    }
+impl<I: GpioPin> sealed::Sealed for I {}
+
+trait SealedInstance {
+    fn ptr() -> &'static pac::adc0::RegisterBlock;
+    fn wait_cell() -> &'static WaitCell;
 }
 
-pub struct AdcHandler;
-impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::ADC1> for AdcHandler {
-    unsafe fn on_interrupt() {
-        on_interrupt();
-    }
+/// ADC Instance
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + Gate<MrccPeriphConfig = AdcConfig> {
+    /// Interrupt for this ADC instance.
+    type Interrupt: Interrupt;
 }
+
+macro_rules! impl_instance {
+    ($($n:expr),*) => {
+        $(
+            paste!{
+                impl SealedInstance for crate::peripherals::[<ADC $n>] {
+                    fn ptr() -> &'static pac::adc0::RegisterBlock {
+                        unsafe { &*pac::[<Adc $n>]::ptr() }
+                    }
+
+                    fn wait_cell() -> &'static WaitCell {
+                        static WAIT_CELL: WaitCell = WaitCell::new();
+                        &WAIT_CELL
+                    }
+
+                }
+
+                impl Instance for crate::peripherals::[<ADC $n>] {
+                    type Interrupt = crate::interrupt::typelevel::[<ADC $n>];
+                }
+            }
+        )*
+    };
+}
+
+impl_instance!(0, 1, 2, 3);
+
+pub trait AdcPin<Instance>: GpioPin + sealed::Sealed + PeripheralType {
+    const CHANNEL: u8;
+
+    /// Set the given pin to the correct muxing state
+    fn mux(&self);
+}
+
+/// Driver mode.
+#[allow(private_bounds)]
+pub trait ModeAdc: sealed::Sealed {}
+
+/// Blocking mode.
+pub struct Blocking;
+impl sealed::Sealed for Blocking {}
+impl ModeAdc for Blocking {}
+
+/// Async mode.
+pub struct Async {
+    waiter: &'static WaitCell,
+}
+impl sealed::Sealed for Async {}
+impl ModeAdc for Async {}
+
+macro_rules! impl_pin {
+    ($pin:ident, $peri:ident, $func:ident, $channel:literal) => {
+        impl AdcPin<crate::peripherals::$peri> for crate::peripherals::$pin {
+            const CHANNEL: u8 = $channel;
+
+            fn mux(&self) {
+                self.set_pull(crate::gpio::Pull::Disabled);
+                self.set_slew_rate(crate::gpio::SlewRate::Fast.into());
+                self.set_drive_strength(crate::gpio::DriveStrength::Normal.into());
+                self.set_function(crate::pac::port0::pcr0::Mux::$func);
+            }
+        }
+    };
+}
+
+impl_pin!(P2_0, ADC0, Mux0, 0);
+impl_pin!(P2_4, ADC0, Mux0, 1);
+impl_pin!(P2_15, ADC0, Mux0, 2);
+impl_pin!(P2_3, ADC0, Mux0, 3);
+impl_pin!(P2_2, ADC0, Mux0, 4);
+impl_pin!(P2_12, ADC0, Mux0, 5);
+impl_pin!(P2_16, ADC0, Mux0, 6);
+impl_pin!(P2_7, ADC0, Mux0, 7);
+impl_pin!(P0_18, ADC0, Mux0, 8);
+impl_pin!(P0_19, ADC0, Mux0, 9);
+impl_pin!(P0_20, ADC0, Mux0, 10);
+impl_pin!(P0_21, ADC0, Mux0, 11);
+impl_pin!(P0_22, ADC0, Mux0, 12);
+impl_pin!(P0_23, ADC0, Mux0, 13);
+impl_pin!(P0_3, ADC0, Mux0, 14);
+impl_pin!(P0_6, ADC0, Mux0, 15);
+impl_pin!(P1_0, ADC0, Mux0, 16);
+impl_pin!(P1_1, ADC0, Mux0, 17);
+impl_pin!(P1_2, ADC0, Mux0, 18);
+impl_pin!(P1_3, ADC0, Mux0, 19);
+impl_pin!(P1_4, ADC0, Mux0, 20);
+impl_pin!(P1_5, ADC0, Mux0, 21);
+impl_pin!(P1_6, ADC0, Mux0, 22);
+impl_pin!(P1_7, ADC0, Mux0, 23);
+
+// ???
+// impl_pin!(P1_10, ADC0, Mux0, 255);
+
+impl_pin!(P2_1, ADC1, Mux0, 0);
+impl_pin!(P2_5, ADC1, Mux0, 1);
+impl_pin!(P2_19, ADC1, Mux0, 2);
+impl_pin!(P2_6, ADC1, Mux0, 3);
+impl_pin!(P2_3, ADC1, Mux0, 4);
+impl_pin!(P2_13, ADC1, Mux0, 5);
+impl_pin!(P2_17, ADC1, Mux0, 6);
+impl_pin!(P2_7, ADC1, Mux0, 7);
+impl_pin!(P1_10, ADC1, Mux0, 8);
+impl_pin!(P1_11, ADC1, Mux0, 9);
+impl_pin!(P1_12, ADC1, Mux0, 10);
+impl_pin!(P1_13, ADC1, Mux0, 11);
+impl_pin!(P1_14, ADC1, Mux0, 12);
+impl_pin!(P1_15, ADC1, Mux0, 13);
+// ???
+// impl_pin!(P1_16, ADC1, Mux0, 255);
+// impl_pin!(P1_17, ADC1, Mux0, 255);
+// impl_pin!(P1_18, ADC1, Mux0, 255);
+// impl_pin!(P1_19, ADC1, Mux0, 255);
+// ???
+impl_pin!(P3_31, ADC1, Mux0, 20);
+impl_pin!(P3_30, ADC1, Mux0, 21);
+impl_pin!(P3_29, ADC1, Mux0, 22);
+
+impl_pin!(P2_4, ADC2, Mux0, 0);
+impl_pin!(P2_10, ADC2, Mux0, 1);
+impl_pin!(P4_4, ADC2, Mux0, 2);
+// impl_pin!(P2_24, ADC2, Mux0, 255); ???
+impl_pin!(P2_16, ADC2, Mux0, 4);
+impl_pin!(P2_12, ADC2, Mux0, 5);
+impl_pin!(P2_20, ADC2, Mux0, 6);
+impl_pin!(P2_7, ADC2, Mux0, 7);
+impl_pin!(P0_2, ADC2, Mux0, 8);
+// ???
+// impl_pin!(P0_4, ADC2, Mux0, 255);
+// impl_pin!(P0_5, ADC2, Mux0, 255);
+// impl_pin!(P0_6, ADC2, Mux0, 255);
+// impl_pin!(P0_7, ADC2, Mux0, 255);
+// impl_pin!(P0_12, ADC2, Mux0, 255);
+// impl_pin!(P0_13, ADC2, Mux0, 255);
+// ???
+impl_pin!(P0_14, ADC2, Mux0, 14);
+impl_pin!(P0_15, ADC2, Mux0, 15);
+// ???
+// impl_pin!(P4_0, ADC2, Mux0, 255);
+// impl_pin!(P4_1, ADC2, Mux0, 255);
+// ???
+impl_pin!(P4_2, ADC2, Mux0, 18);
+impl_pin!(P4_3, ADC2, Mux0, 19);
+//impl_pin!(P4_4, ADC2, Mux0, 20); // Conflit with ADC2_A3 and ADC2_A20 using the same pin
+impl_pin!(P4_5, ADC2, Mux0, 21);
+impl_pin!(P4_6, ADC2, Mux0, 22);
+impl_pin!(P4_7, ADC2, Mux0, 23);
+
+impl_pin!(P2_5, ADC3, Mux0, 0);
+impl_pin!(P2_11, ADC3, Mux0, 1);
+impl_pin!(P2_23, ADC3, Mux0, 2);
+// impl_pin!(P2_25, ADC3, Mux0, 255); // ???
+impl_pin!(P2_17, ADC3, Mux0, 4);
+impl_pin!(P2_13, ADC3, Mux0, 5);
+impl_pin!(P2_21, ADC3, Mux0, 6);
+impl_pin!(P2_7, ADC3, Mux0, 7);
+// ???
+// impl_pin!(P3_2, ADC3, Mux0, 255);
+// impl_pin!(P3_3, ADC3, Mux0, 255);
+// impl_pin!(P3_4, ADC3, Mux0, 255);
+// impl_pin!(P3_5, ADC3, Mux0, 255);
+// ???
+impl_pin!(P3_6, ADC3, Mux0, 12);
+impl_pin!(P3_7, ADC3, Mux0, 13);
+impl_pin!(P3_12, ADC3, Mux0, 14);
+impl_pin!(P3_13, ADC3, Mux0, 15);
+impl_pin!(P3_14, ADC3, Mux0, 16);
+impl_pin!(P3_15, ADC3, Mux0, 17);
+impl_pin!(P3_20, ADC3, Mux0, 18);
+impl_pin!(P3_21, ADC3, Mux0, 19);
+impl_pin!(P3_22, ADC3, Mux0, 20);
+// ???
+// impl_pin!(P3_23, ADC3, Mux0, 255);
+// impl_pin!(P3_24, ADC3, Mux0, 255);
+// impl_pin!(P3_25, ADC3, Mux0, 255);
+// ???
diff --git a/embassy-mcxa/src/clocks/mod.rs b/embassy-mcxa/src/clocks/mod.rs
index 9288f5dc1..b96d9612a 100644
--- a/embassy-mcxa/src/clocks/mod.rs
+++ b/embassy-mcxa/src/clocks/mod.rs
@@ -945,7 +945,10 @@ pub(crate) mod gate {
     impl_cc_gate!(LPUART3, mrcc_glb_cc0, mrcc_glb_rst0, lpuart3, LpuartConfig);
     impl_cc_gate!(LPUART4, mrcc_glb_cc0, mrcc_glb_rst0, lpuart4, LpuartConfig);
     impl_cc_gate!(LPUART5, mrcc_glb_cc1, mrcc_glb_rst1, lpuart5, LpuartConfig);
+    impl_cc_gate!(ADC0, mrcc_glb_cc1, mrcc_glb_rst1, adc0, AdcConfig);
     impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig);
+    impl_cc_gate!(ADC2, mrcc_glb_cc1, mrcc_glb_rst1, adc2, AdcConfig);
+    impl_cc_gate!(ADC3, mrcc_glb_cc1, mrcc_glb_rst1, adc3, AdcConfig);
 
     // DMA0 peripheral - uses NoConfig since it has no selectable clock source
     impl_cc_gate!(DMA0, mrcc_glb_cc0, mrcc_glb_rst0, dma0, NoConfig);
diff --git a/embassy-mcxa/src/clocks/periph_helpers.rs b/embassy-mcxa/src/clocks/periph_helpers.rs
index fed5e558e..f2f51c60c 100644
--- a/embassy-mcxa/src/clocks/periph_helpers.rs
+++ b/embassy-mcxa/src/clocks/periph_helpers.rs
@@ -427,6 +427,7 @@ impl SPConfHelper for OsTimerConfig {
 
 /// Selectable clocks for the ADC peripheral
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum AdcClockSel {
     /// Divided `fro_lf`/`clk_12m`/FRO12M source
     FroLfDiv,
diff --git a/embassy-mcxa/src/i2c/controller.rs b/embassy-mcxa/src/i2c/controller.rs
index c27d508b0..62789f85f 100644
--- a/embassy-mcxa/src/i2c/controller.rs
+++ b/embassy-mcxa/src/i2c/controller.rs
@@ -8,9 +8,9 @@ use embassy_hal_internal::drop::OnDrop;
 use mcxa_pac::lpi2c0::mtdr::Cmd;
 
 use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin};
-use crate::AnyPin;
 use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig};
 use crate::clocks::{PoweredClock, enable_and_reset};
+use crate::gpio::AnyPin;
 use crate::interrupt::typelevel::Interrupt;
 
 /// Bus speed (nominal SCL, no clock stretching)
diff --git a/embassy-mcxa/src/interrupt.rs b/embassy-mcxa/src/interrupt.rs
index be2704454..b662f7ee0 100644
--- a/embassy-mcxa/src/interrupt.rs
+++ b/embassy-mcxa/src/interrupt.rs
@@ -9,7 +9,10 @@
 mod generated {
     #[rustfmt::skip]
     embassy_hal_internal::interrupt_mod!(
+        ADC0,
         ADC1,
+        ADC2,
+        ADC3,
         DMA_CH0,
         DMA_CH1,
         DMA_CH2,
@@ -281,44 +284,6 @@ impl InterruptExt for Rtc {
     }
 }
 
-pub struct Adc;
-pub const ADC1: Adc = Adc;
-
-impl InterruptExt for Adc {
-    /// Clear any pending ADC1 in NVIC.
-    #[inline]
-    fn unpend(&self) {
-        cortex_m::peripheral::NVIC::unpend(Interrupt::ADC1);
-    }
-
-    /// Set NVIC priority for ADC1.
-    #[inline]
-    fn set_priority(&self, priority: Priority) {
-        unsafe {
-            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
-            nvic.set_priority(Interrupt::ADC1, u8::from(priority));
-        }
-    }
-
-    /// Enable ADC1 in NVIC.
-    #[inline]
-    unsafe fn enable(&self) {
-        cortex_m::peripheral::NVIC::unmask(Interrupt::ADC1);
-    }
-
-    /// Disable ADC1 in NVIC.
-    #[inline]
-    unsafe fn disable(&self) {
-        cortex_m::peripheral::NVIC::mask(Interrupt::ADC1);
-    }
-
-    /// Check if ADC1 is pending in NVIC.
-    #[inline]
-    fn is_pending(&self) -> bool {
-        cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC1)
-    }
-}
-
 pub struct Gpio0;
 pub const GPIO0: Gpio0 = Gpio0;
 
diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs
index 12c2708de..6383353db 100644
--- a/embassy-mcxa/src/lib.rs
+++ b/embassy-mcxa/src/lib.rs
@@ -8,7 +8,6 @@
 pub mod clocks; // still provide clock helpers
 pub mod dma;
 pub mod gpio;
-pub mod pins; // pin mux helpers
 
 pub mod adc;
 pub mod clkout;
@@ -18,15 +17,19 @@ pub mod i2c;
 pub mod interrupt;
 pub mod lpuart;
 pub mod ostimer;
+pub mod reset_reason;
 pub mod rtc;
 pub mod trng;
 
+use crate::interrupt::InterruptExt;
 pub use crate::pac::NVIC_PRIO_BITS;
 
 #[rustfmt::skip]
 embassy_hal_internal::peripherals!(
     ADC0,
     ADC1,
+    ADC2,
+    ADC3,
 
     AOI0,
     AOI1,
@@ -337,9 +340,6 @@ embassy_hal_internal::peripherals!(
 // Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it.
 
 // Re-export interrupt traits and types
-pub use adc::Adc1 as Adc1Token;
-pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output};
-pub use interrupt::InterruptExt;
 #[cfg(feature = "unstable-pac")]
 pub use mcxa_pac as pac;
 #[cfg(not(feature = "unstable-pac"))]
@@ -355,8 +355,6 @@ pub fn init(cfg: crate::config::Config) -> Peripherals {
     // Apply user-configured priority early; enabling is left to examples/apps
     crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority);
     // Apply user-configured priority early; enabling is left to examples/apps
-    crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority);
-    // Apply user-configured priority early; enabling is left to examples/apps
     crate::interrupt::GPIO0.set_priority(cfg.gpio_interrupt_priority);
     // Apply user-configured priority early; enabling is left to examples/apps
     crate::interrupt::GPIO1.set_priority(cfg.gpio_interrupt_priority);
diff --git a/embassy-mcxa/src/lpuart/mod.rs b/embassy-mcxa/src/lpuart/mod.rs
index e59ce8140..bce3986b5 100644
--- a/embassy-mcxa/src/lpuart/mod.rs
+++ b/embassy-mcxa/src/lpuart/mod.rs
@@ -6,12 +6,12 @@ use paste::paste;
 
 use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig};
 use crate::clocks::{ClockError, Gate, PoweredClock, enable_and_reset};
-use crate::gpio::SealedPin;
+use crate::gpio::{AnyPin, SealedPin};
 use crate::pac::lpuart0::baud::Sbns as StopBits;
 use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity};
 use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource};
 use crate::pac::lpuart0::stat::Msbf as MsbFirst;
-use crate::{AnyPin, interrupt, pac};
+use crate::{interrupt, pac};
 
 pub mod buffered;
 
diff --git a/embassy-mcxa/src/pins.rs b/embassy-mcxa/src/pins.rs
deleted file mode 100644
index 9adbe64c8..000000000
--- a/embassy-mcxa/src/pins.rs
+++ /dev/null
@@ -1,33 +0,0 @@
-//! Pin configuration helpers (separate from peripheral drivers).
-use crate::pac;
-
-/// Configure pins for ADC usage.
-///
-/// # Safety
-///
-/// Must be called after PORT clocks are enabled.
-pub unsafe fn configure_adc_pins() {
-    // P1_10 = ADC1_A8
-    let port1 = &*pac::Port1::ptr();
-    port1.pcr10().write(|w| {
-        w.ps()
-            .ps0()
-            .pe()
-            .pe0()
-            .sre()
-            .sre0()
-            .ode()
-            .ode0()
-            .dse()
-            .dse0()
-            .mux()
-            .mux0()
-            .ibe()
-            .ibe0()
-            .inv()
-            .inv0()
-            .lk()
-            .lk0()
-    });
-    core::arch::asm!("dsb sy; isb sy");
-}
diff --git a/embassy-mcxa/src/reset_reason.rs b/embassy-mcxa/src/reset_reason.rs
new file mode 100644
index 000000000..f9a9ce096
--- /dev/null
+++ b/embassy-mcxa/src/reset_reason.rs
@@ -0,0 +1,106 @@
+//! Reset reason
+//!
+//! MCXA families keep the most recent reset reason in the SRS
+//! register of the CMC block. This lets users understand why the MCU
+//! has reset and take appropriate corrective actions if required.
+
+/// Reads the most recent reset reason from the Core Mode Controller
+/// (CMC).
+pub fn reset_reason() -> ResetReason {
+    let regs = unsafe { &*crate::pac::Cmc::steal() };
+
+    let srs = regs.srs().read();
+
+    if srs.wakeup().is_enabled() {
+        ResetReason::WakeUp
+    } else if srs.por().bit_is_set() {
+        ResetReason::Por
+    } else if srs.vd().bit_is_set() {
+        ResetReason::VoltageDetect
+    } else if srs.warm().bit_is_set() {
+        ResetReason::Warm
+    } else if srs.fatal().bit_is_set() {
+        ResetReason::Fatal
+    } else if srs.pin().bit_is_set() {
+        ResetReason::Pin
+    } else if srs.dap().bit_is_set() {
+        ResetReason::Dap
+    } else if srs.rstack().bit_is_set() {
+        ResetReason::ResetAckTimeout
+    } else if srs.lpack().bit_is_set() {
+        ResetReason::LowPowerAckTimeout
+    } else if srs.scg().bit_is_set() {
+        ResetReason::SystemClockGeneration
+    } else if srs.wwdt0().bit_is_set() {
+        ResetReason::Wwdt0
+    } else if srs.sw().bit_is_set() {
+        ResetReason::Software
+    } else if srs.lockup().bit_is_set() {
+        ResetReason::Lockup
+    } else if srs.cdog0().bit_is_set() {
+        ResetReason::Cdog0
+    } else if srs.cdog1().bit_is_set() {
+        ResetReason::Cdog1
+    } else if srs.jtag().bit_is_set() {
+        ResetReason::Jtag
+    } else {
+        ResetReason::Tamper
+    }
+}
+
+/// Indicates the type and source of the most recent reset.
+#[derive(Clone, Copy, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum ResetReason {
+    /// Tamper reset.
+    Tamper,
+
+    /// JTAG System Reset request.
+    Jtag,
+
+    /// Code Watchdog 0 reset.
+    Cdog0,
+
+    /// Code Watchdog 1 reset.
+    Cdog1,
+
+    /// Lockup reset.
+    Lockup,
+
+    /// Software reset.
+    Software,
+
+    /// Windowed Watchdog 0 reset.
+    Wwdt0,
+
+    /// System clock generation reset.
+    SystemClockGeneration,
+
+    /// Low Power Acknowledge Timeout reset.
+    LowPowerAckTimeout,
+
+    /// Reset Timeout.
+    ResetAckTimeout,
+
+    /// Debug Access Port reset.
+    Dap,
+
+    /// External assertion of RESET_b pin.
+    Pin,
+
+    /// Fatal reset.
+    Fatal,
+
+    /// Warm reset.
+    Warm,
+
+    /// Voltage detect reset.
+    VoltageDetect,
+
+    /// Power-on reset.
+    Por,
+
+    /// Wake-up reset.
+    WakeUp,
+}
diff --git a/embassy-mcxa/src/rtc.rs b/embassy-mcxa/src/rtc.rs
index f975d9c9f..c5474d34a 100644
--- a/embassy-mcxa/src/rtc.rs
+++ b/embassy-mcxa/src/rtc.rs
@@ -9,8 +9,6 @@ use crate::interrupt::typelevel::{Handler, Interrupt};
 use crate::pac;
 use crate::pac::rtc0::cr::Um;
 
-type Regs = pac::rtc0::RegisterBlock;
-
 /// Global wait cell for alarm notifications
 static WAKER: WaitCell = WaitCell::new();
 
@@ -22,7 +20,7 @@ pub struct InterruptHandler<I: Instance> {
 /// Trait for RTC peripheral instances
 pub trait Instance: PeripheralType {
     type Interrupt: Interrupt;
-    fn ptr() -> *const Regs;
+    fn ptr() -> &'static pac::rtc0::RegisterBlock;
 }
 
 /// Token for RTC0
@@ -30,8 +28,8 @@ pub type Rtc0 = crate::peripherals::RTC0;
 impl Instance for crate::peripherals::RTC0 {
     type Interrupt = crate::interrupt::typelevel::RTC;
     #[inline(always)]
-    fn ptr() -> *const Regs {
-        pac::Rtc0::ptr()
+    fn ptr() -> &'static pac::rtc0::RegisterBlock {
+        unsafe { &*pac::Rtc0::ptr() }
     }
 }
 
@@ -204,18 +202,19 @@ pub fn get_default_config() -> RtcConfig {
     }
 }
 /// Minimal RTC handle for a specific instance I (store the zero-sized token like embassy)
-pub struct Rtc<'a, I: Instance> {
-    _inst: core::marker::PhantomData<&'a mut I>,
+pub struct Rtc<'a> {
+    _inst: core::marker::PhantomData<&'a mut ()>,
+    info: &'static pac::rtc0::RegisterBlock,
 }
 
-impl<'a, I: Instance> Rtc<'a, I> {
+impl<'a> Rtc<'a> {
     /// Create a new instance of the real time clock.
-    pub fn new(
+    pub fn new<I: Instance>(
         _inst: Peri<'a, I>,
         _irq: impl crate::interrupt::typelevel::Binding<I::Interrupt, InterruptHandler<I>> + 'a,
         config: RtcConfig,
     ) -> Self {
-        let rtc = unsafe { &*I::ptr() };
+        let info = I::ptr();
 
         // The RTC is NOT gated by the MRCC, but we DO need to make sure the 16k clock
         // on the vsys domain is active
@@ -227,13 +226,13 @@ impl<'a, I: Instance> Rtc<'a, I> {
         }
 
         // RTC reset
-        rtc.cr().modify(|_, w| w.swr().set_bit());
-        rtc.cr().modify(|_, w| w.swr().clear_bit());
-        rtc.tsr().write(|w| unsafe { w.bits(1) });
+        info.cr().modify(|_, w| w.swr().set_bit());
+        info.cr().modify(|_, w| w.swr().clear_bit());
+        info.tsr().write(|w| unsafe { w.bits(1) });
 
-        rtc.cr().modify(|_, w| w.um().variant(config.update_mode));
+        info.cr().modify(|_, w| w.um().variant(config.update_mode));
 
-        rtc.tcr().modify(|_, w| unsafe {
+        info.tcr().modify(|_, w| unsafe {
             w.cir()
                 .bits(config.compensation_interval)
                 .tcr()
@@ -246,6 +245,7 @@ impl<'a, I: Instance> Rtc<'a, I> {
 
         Self {
             _inst: core::marker::PhantomData,
+            info,
         }
     }
 
@@ -259,9 +259,8 @@ impl<'a, I: Instance> Rtc<'a, I> {
     ///
     /// The datetime is converted to Unix timestamp and written to the time seconds register.
     pub fn set_datetime(&self, datetime: RtcDateTime) {
-        let rtc = unsafe { &*I::ptr() };
         let seconds = convert_datetime_to_seconds(&datetime);
-        rtc.tsr().write(|w| unsafe { w.bits(seconds) });
+        self.info.tsr().write(|w| unsafe { w.bits(seconds) });
     }
 
     /// Get the current date and time
@@ -274,8 +273,7 @@ impl<'a, I: Instance> Rtc<'a, I> {
     ///
     /// Reads the current Unix timestamp from the time seconds register and converts it.
     pub fn get_datetime(&self) -> RtcDateTime {
-        let rtc = unsafe { &*I::ptr() };
-        let seconds = rtc.tsr().read().bits();
+        let seconds = self.info.tsr().read().bits();
         convert_seconds_to_datetime(seconds)
     }
 
@@ -295,19 +293,18 @@ impl<'a, I: Instance> Rtc<'a, I> {
     /// - Uses timeouts to prevent infinite loops
     /// - Enables the alarm interrupt after setting
     pub fn set_alarm(&self, alarm: RtcDateTime) {
-        let rtc = unsafe { &*I::ptr() };
         let seconds = convert_datetime_to_seconds(&alarm);
 
-        rtc.tar().write(|w| unsafe { w.bits(0) });
+        self.info.tar().write(|w| unsafe { w.bits(0) });
         let mut timeout = 10000;
-        while rtc.tar().read().bits() != 0 && timeout > 0 {
+        while self.info.tar().read().bits() != 0 && timeout > 0 {
             timeout -= 1;
         }
 
-        rtc.tar().write(|w| unsafe { w.bits(seconds) });
+        self.info.tar().write(|w| unsafe { w.bits(seconds) });
 
         let mut timeout = 10000;
-        while rtc.tar().read().bits() != seconds && timeout > 0 {
+        while self.info.tar().read().bits() != seconds && timeout > 0 {
             timeout -= 1;
         }
 
@@ -324,8 +321,7 @@ impl<'a, I: Instance> Rtc<'a, I> {
     ///
     /// Reads the alarm timestamp from the time alarm register and converts it.
     pub fn get_alarm(&self) -> RtcDateTime {
-        let rtc = unsafe { &*I::ptr() };
-        let alarm_seconds = rtc.tar().read().bits();
+        let alarm_seconds = self.info.tar().read().bits();
         convert_seconds_to_datetime(alarm_seconds)
     }
 
@@ -335,8 +331,7 @@ impl<'a, I: Instance> Rtc<'a, I> {
     ///
     /// Sets the Time Counter Enable (TCE) bit in the status register.
     pub fn start(&self) {
-        let rtc = unsafe { &*I::ptr() };
-        rtc.sr().modify(|_, w| w.tce().set_bit());
+        self.info.sr().modify(|_, w| w.tce().set_bit());
     }
 
     /// Stop the RTC time counter
@@ -345,8 +340,7 @@ impl<'a, I: Instance> Rtc<'a, I> {
     ///
     /// Clears the Time Counter Enable (TCE) bit in the status register.
     pub fn stop(&self) {
-        let rtc = unsafe { &*I::ptr() };
-        rtc.sr().modify(|_, w| w.tce().clear_bit());
+        self.info.sr().modify(|_, w| w.tce().clear_bit());
     }
 
     /// Enable specific RTC interrupts
@@ -364,19 +358,17 @@ impl<'a, I: Instance> Rtc<'a, I> {
     /// - Alarm Interrupt
     /// - Seconds Interrupt
     pub fn set_interrupt(&self, mask: u32) {
-        let rtc = unsafe { &*I::ptr() };
-
         if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.tiie().tiie_1());
+            self.info.ier().modify(|_, w| w.tiie().tiie_1());
         }
         if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.toie().toie_1());
+            self.info.ier().modify(|_, w| w.toie().toie_1());
         }
         if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.taie().taie_1());
+            self.info.ier().modify(|_, w| w.taie().taie_1());
         }
         if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.tsie().tsie_1());
+            self.info.ier().modify(|_, w| w.tsie().tsie_1());
         }
     }
 
@@ -390,19 +382,17 @@ impl<'a, I: Instance> Rtc<'a, I> {
     ///
     /// This function disables the specified interrupt types.
     pub fn disable_interrupt(&self, mask: u32) {
-        let rtc = unsafe { &*I::ptr() };
-
         if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.tiie().tiie_0());
+            self.info.ier().modify(|_, w| w.tiie().tiie_0());
         }
         if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.toie().toie_0());
+            self.info.ier().modify(|_, w| w.toie().toie_0());
         }
         if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.taie().taie_0());
+            self.info.ier().modify(|_, w| w.taie().taie_0());
         }
         if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 {
-            rtc.ier().modify(|_, w| w.tsie().tsie_0());
+            self.info.ier().modify(|_, w| w.tsie().tsie_0());
         }
     }
 
@@ -412,8 +402,7 @@ impl<'a, I: Instance> Rtc<'a, I> {
     ///
     /// This function clears the Time Alarm Interrupt Enable bit.
     pub fn clear_alarm_flag(&self) {
-        let rtc = unsafe { &*I::ptr() };
-        rtc.ier().modify(|_, w| w.taie().clear_bit());
+        self.info.ier().modify(|_, w| w.taie().clear_bit());
     }
 
     /// Wait for an RTC alarm to trigger.
@@ -421,6 +410,7 @@ impl<'a, I: Instance> Rtc<'a, I> {
     /// # Arguments
     ///
     /// * `alarm` - The date and time when the alarm should trigger
+    ///
     /// This function will wait until the RTC alarm is triggered.
     /// If no alarm is scheduled, it will wait indefinitely until one is scheduled and triggered.
     pub async fn wait_for_alarm(&mut self, alarm: RtcDateTime) {