aboutsummaryrefslogtreecommitdiff
path: root/embassy-net-enc28j60/src/bank1.rs
diff options
context:
space:
mode:
Diffstat (limited to 'embassy-net-enc28j60/src/bank1.rs')
-rw-r--r--embassy-net-enc28j60/src/bank1.rs84
1 files changed, 84 insertions, 0 deletions
diff --git a/embassy-net-enc28j60/src/bank1.rs b/embassy-net-enc28j60/src/bank1.rs
new file mode 100644
index 000000000..30560edf6
--- /dev/null
+++ b/embassy-net-enc28j60/src/bank1.rs
@@ -0,0 +1,84 @@
1#[allow(dead_code)]
2#[derive(Clone, Copy)]
3pub enum Register {
4 EHT0 = 0x00,
5 EHT1 = 0x01,
6 EHT2 = 0x02,
7 EHT3 = 0x03,
8 EHT4 = 0x04,
9 EHT5 = 0x05,
10 EHT6 = 0x06,
11 EHT7 = 0x07,
12 EPMM0 = 0x08,
13 EPMM1 = 0x09,
14 EPMM2 = 0x0a,
15 EPMM3 = 0x0b,
16 EPMM4 = 0x0c,
17 EPMM5 = 0x0d,
18 EPMM6 = 0x0e,
19 EPMM7 = 0x0f,
20 EPMCSL = 0x10,
21 EPMCSH = 0x11,
22 EPMOL = 0x14,
23 EPMOH = 0x15,
24 ERXFCON = 0x18,
25 EPKTCNT = 0x19,
26}
27
28impl Register {
29 pub(crate) fn addr(&self) -> u8 {
30 *self as u8
31 }
32
33 pub(crate) fn is_eth_register(&self) -> bool {
34 match *self {
35 Register::EHT0 => true,
36 Register::EHT1 => true,
37 Register::EHT2 => true,
38 Register::EHT3 => true,
39 Register::EHT4 => true,
40 Register::EHT5 => true,
41 Register::EHT6 => true,
42 Register::EHT7 => true,
43 Register::EPMM0 => true,
44 Register::EPMM1 => true,
45 Register::EPMM2 => true,
46 Register::EPMM3 => true,
47 Register::EPMM4 => true,
48 Register::EPMM5 => true,
49 Register::EPMM6 => true,
50 Register::EPMM7 => true,
51 Register::EPMCSL => true,
52 Register::EPMCSH => true,
53 Register::EPMOL => true,
54 Register::EPMOH => true,
55 Register::ERXFCON => true,
56 Register::EPKTCNT => true,
57 }
58 }
59}
60
61impl Into<super::Register> for Register {
62 fn into(self) -> super::Register {
63 super::Register::Bank1(self)
64 }
65}
66
67register!(ERXFCON, 0b1010_0001, u8, {
68 #[doc = "Broadcast Filter Enable bit"]
69 bcen @ 0,
70 #[doc = "Multicast Filter Enable bit"]
71 mcen @ 1,
72 #[doc = "Hash Table Filter Enable bit"]
73 hten @ 2,
74 #[doc = "Magic Packetâ„¢ Filter Enable bit"]
75 mpen @ 3,
76 #[doc = "Pattern Match Filter Enable bit"]
77 pmen @ 4,
78 #[doc = "Post-Filter CRC Check Enable bit"]
79 crcen @ 5,
80 #[doc = "AND/OR Filter Select bit"]
81 andor @ 6,
82 #[doc = "Unicast Filter Enable bit"]
83 ucen @ 7,
84});