diff options
Diffstat (limited to 'embassy-nrf/src/chips/nrf52833.rs')
| -rw-r--r-- | embassy-nrf/src/chips/nrf52833.rs | 90 |
1 files changed, 43 insertions, 47 deletions
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs index 5e5db04de..bff7f4ebb 100644 --- a/embassy-nrf/src/chips/nrf52833.rs +++ b/embassy-nrf/src/chips/nrf52833.rs | |||
| @@ -306,50 +306,46 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7); | |||
| 306 | 306 | ||
| 307 | impl_i2s!(I2S, I2S, I2S); | 307 | impl_i2s!(I2S, I2S, I2S); |
| 308 | 308 | ||
| 309 | pub mod irqs { | 309 | embassy_hal_common::interrupt_mod!( |
| 310 | use embassy_cortex_m::interrupt::_export::declare; | 310 | POWER_CLOCK, |
| 311 | 311 | RADIO, | |
| 312 | use crate::pac::Interrupt as InterruptEnum; | 312 | UARTE0_UART0, |
| 313 | 313 | SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, | |
| 314 | declare!(POWER_CLOCK); | 314 | SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, |
| 315 | declare!(RADIO); | 315 | NFCT, |
| 316 | declare!(UARTE0_UART0); | 316 | GPIOTE, |
| 317 | declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | 317 | SAADC, |
| 318 | declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | 318 | TIMER0, |
| 319 | declare!(NFCT); | 319 | TIMER1, |
| 320 | declare!(GPIOTE); | 320 | TIMER2, |
| 321 | declare!(SAADC); | 321 | RTC0, |
| 322 | declare!(TIMER0); | 322 | TEMP, |
| 323 | declare!(TIMER1); | 323 | RNG, |
| 324 | declare!(TIMER2); | 324 | ECB, |
| 325 | declare!(RTC0); | 325 | CCM_AAR, |
| 326 | declare!(TEMP); | 326 | WDT, |
| 327 | declare!(RNG); | 327 | RTC1, |
| 328 | declare!(ECB); | 328 | QDEC, |
| 329 | declare!(CCM_AAR); | 329 | COMP_LPCOMP, |
| 330 | declare!(WDT); | 330 | SWI0_EGU0, |
| 331 | declare!(RTC1); | 331 | SWI1_EGU1, |
| 332 | declare!(QDEC); | 332 | SWI2_EGU2, |
| 333 | declare!(COMP_LPCOMP); | 333 | SWI3_EGU3, |
| 334 | declare!(SWI0_EGU0); | 334 | SWI4_EGU4, |
| 335 | declare!(SWI1_EGU1); | 335 | SWI5_EGU5, |
| 336 | declare!(SWI2_EGU2); | 336 | TIMER3, |
| 337 | declare!(SWI3_EGU3); | 337 | TIMER4, |
| 338 | declare!(SWI4_EGU4); | 338 | PWM0, |
| 339 | declare!(SWI5_EGU5); | 339 | PDM, |
| 340 | declare!(TIMER3); | 340 | MWU, |
| 341 | declare!(TIMER4); | 341 | PWM1, |
| 342 | declare!(PWM0); | 342 | PWM2, |
| 343 | declare!(PDM); | 343 | SPIM2_SPIS2_SPI2, |
| 344 | declare!(MWU); | 344 | RTC2, |
| 345 | declare!(PWM1); | 345 | FPU, |
| 346 | declare!(PWM2); | 346 | USBD, |
| 347 | declare!(SPIM2_SPIS2_SPI2); | 347 | UARTE1, |
| 348 | declare!(RTC2); | 348 | PWM3, |
| 349 | declare!(FPU); | 349 | SPIM3, |
| 350 | declare!(USBD); | 350 | I2S, |
| 351 | declare!(UARTE1); | 351 | ); |
| 352 | declare!(PWM3); | ||
| 353 | declare!(SPIM3); | ||
| 354 | declare!(I2S); | ||
| 355 | } | ||
