1 files changed, 402 insertions, 472 deletions

diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 16063ce4d..9cc44aa9a 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,19 +1,19 @@
 use cfg_if::cfg_if;
 #[cfg(adc_g0)]
 use heapless::Vec;
-use pac::adc::vals::Dmacfg;
 #[cfg(adc_g0)]
-use pac::adc::vals::{Ckmode, Smpsel};
+use pac::adc::vals::Ckmode;
+use pac::adc::vals::Dmacfg;
 #[cfg(adc_v3)]
 use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
 #[cfg(adc_g0)]
 pub use pac::adc::vals::{Ovsr, Ovss, Presc};
 
-use super::{
-    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
-};
-use crate::dma::Transfer;
-use crate::{pac, rcc, Peri};
+#[allow(unused_imports)]
+use super::SealedAdcChannel;
+use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::ConversionMode;
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -25,70 +25,64 @@ pub const VREF_CALIB_MV: u32 = 3000;
 // TODO: Use [#![feature(variant_count)]](https://github.com/rust-lang/rust/issues/73662) when stable
 const SAMPLE_TIMES_CAPACITY: usize = 2;
 
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        cfg_if! {
-            if #[cfg(adc_g0)] {
-                let val = 13;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 17;
-            } else if #[cfg(adc_u0)] {
-                let val = 12;
-            } else {
-                let val = 0;
-            }
-        }
-        val
-    }
+#[cfg(adc_g0)]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 13;
+}
+#[cfg(any(adc_h5, adc_h7rs))]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 17;
+}
+#[cfg(adc_u0)]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 12;
+}
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 0;
 }
 
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        cfg_if! {
-            if #[cfg(adc_g0)] {
-                let val = 12;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 16;
-            } else if #[cfg(adc_u0)] {
-                let val = 11;
-            } else {
-                let val = 17;
-            }
-        }
-        val
-    }
+#[cfg(adc_g0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 12;
+}
+#[cfg(any(adc_h5, adc_h7rs))]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 16;
+}
+#[cfg(adc_u0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 11;
+}
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 17;
 }
 
-pub struct Vbat;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
-    fn channel(&self) -> u8 {
-        cfg_if! {
-            if #[cfg(adc_g0)] {
-                let val = 14;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 2;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 13;
-            } else {
-                let val = 18;
-            }
-        }
-        val
-    }
+#[cfg(adc_g0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 14;
+}
+#[cfg(any(adc_h5, adc_h7rs))]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 16;
+}
+#[cfg(adc_u0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 13;
+}
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 18;
 }
 
 cfg_if! {
     if #[cfg(any(adc_h5, adc_h7rs))] {
         pub struct VddCore;
-        impl<T: Instance> AdcChannel<T> for VddCore {}
+        impl<T: Instance> super::AdcChannel<T> for VddCore {}
         impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
             fn channel(&self) -> u8 {
-                6
+                17
             }
         }
     }
@@ -97,7 +91,7 @@ cfg_if! {
 cfg_if! {
     if #[cfg(adc_u0)] {
         pub struct DacOut;
-        impl<T: Instance> AdcChannel<T> for DacOut {}
+        impl<T: Instance> super::AdcChannel<T> for DacOut {}
         impl<T: Instance> super::SealedAdcChannel<T> for DacOut {
             fn channel(&self) -> u8 {
                 19
@@ -106,21 +100,6 @@ cfg_if! {
     }
 }
 
-/// Number of samples used for averaging.
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-}
-
 cfg_if! { if #[cfg(adc_g0)] {
 
 /// Synchronous PCLK prescaler
@@ -141,295 +120,150 @@ pub enum Clock {
 
 }}
 
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Enable the voltage regulator
-    fn init_regulator() {
-        rcc::enable_and_reset::<T>();
-        T::regs().cr().modify(|reg| {
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            reg.set_deeppwd(false);
-            reg.set_advregen(true);
-        });
-
-        // If this is false then each ADC_CHSELR bit enables an input channel.
-        // This is the reset value, so has no effect.
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(false);
-        });
-
-        blocking_delay_us(20);
-    }
-
-    /// Calibrate to remove conversion offset
-    fn init_calibrate() {
-        T::regs().cr().modify(|reg| {
-            reg.set_adcal(true);
-        });
-
-        while T::regs().cr().read().adcal() {
-            // spin
-        }
-
-        blocking_delay_us(1);
-    }
-
-    /// Initialize the ADC leaving any analog clock at reset value.
-    /// For G0 and WL, this is the async clock without prescaler.
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        Self::init_regulator();
-        Self::init_calibrate();
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
-    }
-
+#[cfg(adc_u0)]
+type Ovss = u8;
+#[cfg(adc_u0)]
+type Ovsr = u8;
+#[cfg(adc_v3)]
+type Ovss = OversamplingShift;
+#[cfg(adc_v3)]
+type Ovsr = OversamplingRatio;
+
+/// Adc configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
+    pub oversampling_shift: Option<Ovss>,
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
+    pub oversampling_ratio: Option<Ovsr>,
+    #[cfg(any(adc_u0, adc_g0))]
+    pub oversampling_enable: Option<bool>,
+    #[cfg(adc_v3)]
+    pub oversampling_mode: Option<(Rovsm, Trovs, bool)>,
     #[cfg(adc_g0)]
-    /// Initialize ADC with explicit clock for the analog ADC
-    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
-        Self::init_regulator();
-
-        #[cfg(any(stm32wl5x))]
-        {
-            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
-            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
-            match clock {
-                Clock::Async { div: _ } => {
-                    assert!(async_clock_available);
-                }
-                Clock::Sync { div: _ } => {
-                    if async_clock_available {
-                        warn!("Not using configured ADC clock");
-                    }
-                }
-            }
-        }
-        match clock {
-            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
-            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
-                reg.set_ckmode(match div {
-                    CkModePclk::DIV1 => Ckmode::PCLK,
-                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
-                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
-                })
-            }),
-        }
-
-        Self::init_calibrate();
+    pub clock: Option<Clock>,
+    pub resolution: Option<Resolution>,
+    pub averaging: Option<Averaging>,
+}
 
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
+impl super::AdcRegs for crate::pac::adc::Adc {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc::dr(*self).as_ptr() as *mut u16
     }
 
     // Enable ADC only when it is not already running.
-    fn enable(&mut self) {
+    fn enable(&self) {
         // Make sure bits are off
-        while T::regs().cr().read().addis() {
+        while self.cr().read().addis() {
             // spin
         }
 
-        if !T::regs().cr().read().aden() {
+        if !self.cr().read().aden() {
             // Enable ADC
-            T::regs().isr().modify(|reg| {
+            self.isr().modify(|reg| {
                 reg.set_adrdy(true);
             });
-            T::regs().cr().modify(|reg| {
+            self.cr().modify(|reg| {
                 reg.set_aden(true);
             });
 
-            while !T::regs().isr().read().adrdy() {
+            while !self.isr().read().adrdy() {
                 // spin
             }
         }
     }
 
-    pub fn enable_vrefint(&self) -> VrefInt {
+    fn start(&self) {
+        self.cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    fn stop(&self) {
+        // Ensure conversions are finished.
+        if self.cr().read().adstart() && !self.cr().read().addis() {
+            self.cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while self.cr().read().adstart() {}
+        }
+
+        // Reset configuration.
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
+        self.cfgr().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmaen(false);
         });
         #[cfg(any(adc_g0, adc_u0))]
-        T::regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
+        self.cfgr1().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmaen(false);
         });
+    }
 
-        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
-        // to stabilize the internal voltage reference.
-        blocking_delay_us(15);
+    /// Perform a single conversion.
+    fn convert(&self) {
+        // Some models are affected by an erratum:
+        // If we perform conversions slower than 1 kHz, the first read ADC value can be
+        // corrupted, so we discard it and measure again.
+        //
+        // STM32L471xx: Section 2.7.3
+        // STM32G4: Section 2.7.3
+        #[cfg(any(rcc_l4, rcc_g4))]
+        let len = 2;
 
-        VrefInt {}
-    }
+        #[cfg(not(any(rcc_l4, rcc_g4)))]
+        let len = 1;
 
-    pub fn enable_temperature(&self) -> Temperature {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch17sel(true);
-                });
-            }
-        }
+        for _ in 0..len {
+            self.isr().modify(|reg| {
+                reg.set_eos(true);
+                reg.set_eoc(true);
+            });
 
-        Temperature {}
-    }
+            // Start conversion
+            self.cr().modify(|reg| {
+                reg.set_adstart(true);
+            });
 
-    pub fn enable_vbat(&self) -> Vbat {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch18sel(true);
-                });
+            while !self.isr().read().eos() {
+                // spin
             }
         }
-
-        Vbat {}
     }
 
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
-
-    /// Get the ADC sample time.
-    pub fn sample_time(&self) -> SampleTime {
-        self.sample_time
-    }
+    fn configure_dma(&self, conversion_mode: ConversionMode) {
+        // Set continuous mode with oneshot dma.
+        // Clear overrun flag before starting transfer.
+        self.isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
 
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
-    }
+        let regs = self.cfgr();
 
-    pub fn set_averaging(&mut self, averaging: Averaging) {
-        let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, 0, 0),
-            Averaging::Samples2 => (true, 0, 1),
-            Averaging::Samples4 => (true, 1, 2),
-            Averaging::Samples8 => (true, 2, 3),
-            Averaging::Samples16 => (true, 3, 4),
-            Averaging::Samples32 => (true, 4, 5),
-            Averaging::Samples64 => (true, 5, 6),
-            Averaging::Samples128 => (true, 6, 7),
-            Averaging::Samples256 => (true, 7, 8),
-        };
-        T::regs().cfgr2().modify(|reg| {
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            reg.set_rovse(enable);
-            #[cfg(any(adc_g0, adc_u0))]
-            reg.set_ovse(enable);
-            #[cfg(any(adc_h5, adc_h7rs))]
-            reg.set_ovsr(samples.into());
-            #[cfg(not(any(adc_h5, adc_h7rs)))]
-            reg.set_ovsr(samples.into());
-            reg.set_ovss(right_shift.into());
-        })
-    }
-    /*
-    /// Convert a raw sample from the `Temperature` to deg C
-    pub fn to_degrees_centigrade(sample: u16) -> f32 {
-        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
-            * (sample as f32 - VtempCal30::get().read() as f32)
-            + 30.0
-    }
-     */
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
+        #[cfg(any(adc_g0, adc_u0))]
+        let regs = self.cfgr1();
 
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+        regs.modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(match conversion_mode {
+                ConversionMode::Singular => Dmacfg::ONE_SHOT,
+                #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+                ConversionMode::Repeated(_) => Dmacfg::CIRCULAR,
+            });
+            reg.set_dmaen(true);
         });
-
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-
-        T::regs().dr().read().0 as u16
     }
 
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        self.read_channel(channel)
-    }
-
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `readings` must have a length that is a multiple of the length of the
-    /// `sequence` iterator.
-    ///
-    /// Note: The order of values in `readings` is defined by the pin ADC
-    /// channel number and not the pin order in `sequence`.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.degrade_adc();
-    /// let mut adc_pin1 = p.PA1.degrade_adc();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA1_CH2.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
-    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            readings.len() % sequence.len() == 0,
-            "Readings length must be a multiple of sequence length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-
-        // Ensure no conversions are ongoing and ADC is enabled.
-        Self::cancel_conversions();
-        self.enable();
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        #[cfg(adc_h5)]
+        self.cr().modify(|w| w.set_aden(false));
 
         // Set sequence length
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().modify(|w| {
+        self.sqr1().modify(|w| {
             w.set_l(sequence.len() as u8 - 1);
         });
 
@@ -437,12 +271,12 @@ impl<'d, T: Instance> Adc<'d, T> {
         {
             let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
 
-            T::regs().chselr().write(|chselr| {
-                T::regs().smpr().write(|smpr| {
-                    for (channel, sample_time) in sequence {
-                        chselr.set_chsel(channel.channel.into(), true);
+            self.chselr().write(|chselr| {
+                self.smpr().write(|smpr| {
+                    for ((channel, _), sample_time) in sequence {
+                        chselr.set_chsel(channel.into(), true);
                         if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
-                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
+                            smpr.set_smpsel(channel.into(), (i as u8).into());
                         } else {
                             smpr.set_sample_time(sample_times.len(), sample_time);
                             if let Err(_) = sample_times.push(sample_time) {
@@ -461,225 +295,321 @@ impl<'d, T: Instance> Adc<'d, T> {
             #[cfg(adc_u0)]
             let mut channel_mask = 0;
 
+            #[cfg(adc_h5)]
+            let mut difsel = 0u32;
+
             // Configure channels and ranks
-            for (_i, (channel, sample_time)) in sequence.enumerate() {
-                Self::configure_channel(channel, sample_time);
+            for (_i, ((channel, _is_differential), sample_time)) in sequence.enumerate() {
+                // RM0492, RM0481, etc.
+                // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
+                #[cfg(any(adc_h5, adc_h7rs))]
+                if channel == 0 {
+                    self.or().modify(|reg| reg.set_op0(true));
+                }
+
+                // Configure channel
+                cfg_if! {
+                    if #[cfg(adc_u0)] {
+                        // On G0 and U6 all channels use the same sampling time.
+                        self.smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+                    } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                        match channel {
+                            0..=9 => self.smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            _ => self.smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                        }
+                    } else {
+                        let sample_time = sample_time.into();
+                        self
+                            .smpr(channel as usize / 10)
+                            .modify(|reg| reg.set_smp(channel as usize % 10, sample_time));
+                    }
+                }
+
+                #[cfg(stm32h7)]
+                {
+                    use crate::pac::adc::vals::Pcsel;
+
+                    self.cfgr2().modify(|w| w.set_lshift(0));
+                    self.pcsel()
+                        .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
+                }
 
                 // Each channel is sampled according to sequence
                 #[cfg(not(any(adc_g0, adc_u0)))]
                 match _i {
                     0..=3 => {
-                        T::regs().sqr1().modify(|w| {
-                            w.set_sq(_i, channel.channel());
+                        self.sqr1().modify(|w| {
+                            w.set_sq(_i, channel);
                         });
                     }
                     4..=8 => {
-                        T::regs().sqr2().modify(|w| {
-                            w.set_sq(_i - 4, channel.channel());
+                        self.sqr2().modify(|w| {
+                            w.set_sq(_i - 4, channel);
                         });
                     }
                     9..=13 => {
-                        T::regs().sqr3().modify(|w| {
-                            w.set_sq(_i - 9, channel.channel());
+                        self.sqr3().modify(|w| {
+                            w.set_sq(_i - 9, channel);
                         });
                     }
                     14..=15 => {
-                        T::regs().sqr4().modify(|w| {
-                            w.set_sq(_i - 14, channel.channel());
+                        self.sqr4().modify(|w| {
+                            w.set_sq(_i - 14, channel);
                         });
                     }
                     _ => unreachable!(),
                 }
 
+                #[cfg(adc_h5)]
+                {
+                    difsel |= (_is_differential as u32) << channel;
+                }
+
                 #[cfg(adc_u0)]
                 {
-                    channel_mask |= 1 << channel.channel();
+                    channel_mask |= 1 << channel;
                 }
             }
 
+            #[cfg(adc_h5)]
+            self.difsel().write(|w| w.set_difsel(difsel));
+
             // On G0 and U0 enabled channels are sampled from 0 to last channel.
             // It is possible to add up to 8 sequences if CHSELRMOD = 1.
             // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
             #[cfg(adc_u0)]
-            T::regs().chselr().modify(|reg| {
+            self.chselr().modify(|reg| {
                 reg.set_chsel(channel_mask);
             });
         }
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
+    }
+}
 
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(true);
+impl<'d, T: Instance<Regs = crate::pac::adc::Adc>> Adc<'d, T> {
+    /// Enable the voltage regulator
+    fn init_regulator() {
+        rcc::enable_and_reset::<T>();
+        T::regs().cr().modify(|reg| {
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            reg.set_deeppwd(false);
+            reg.set_advregen(true);
         });
+
+        // If this is false then each ADC_CHSELR bit enables an input channel.
+        // This is the reset value, so has no effect.
         #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(true);
+            reg.set_chselrmod(false);
         });
 
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
+        blocking_delay_us(20);
+    }
 
-        // Start conversion
+    /// Calibrate to remove conversion offset
+    fn init_calibrate() {
         T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+            reg.set_adcal(true);
         });
 
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
+        while T::regs().cr().read().adcal() {
+            // spin
+        }
 
-        // Reset configuration.
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_cont(false);
-        });
+        blocking_delay_us(1);
     }
 
-    #[cfg(not(adc_g0))]
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        // RM0492, RM0481, etc.
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
-            T::regs().or().modify(|reg| reg.set_op0(true));
-        }
-
-        // Configure channel
-        Self::set_channel_sample_time(channel.channel(), sample_time);
+    /// Initialize the ADC leaving any analog clock at reset value.
+    /// For G0 and WL, this is the async clock without prescaler.
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        Self::init_regulator();
+        Self::init_calibrate();
+        Self { adc }
     }
 
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        self.enable();
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
         #[cfg(not(adc_g0))]
-        Self::configure_channel(channel, self.sample_time);
+        let s = Self::new(adc);
+
         #[cfg(adc_g0)]
-        T::regs().smpr().write(|reg| {
-            reg.set_sample_time(0, self.sample_time);
-            reg.set_smpsel(channel.channel().into(), Smpsel::SMP1);
-        });
-        // Select channel
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().write(|reg| reg.set_sq(0, channel.channel()));
+        let s = match config.clock {
+            Some(clock) => Self::new_with_clock(adc, clock),
+            None => Self::new(adc),
+        };
+
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
+        if let Some(shift) = config.oversampling_shift {
+            T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+        }
+
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
+        if let Some(ratio) = config.oversampling_ratio {
+            T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+        }
+
         #[cfg(any(adc_g0, adc_u0))]
-        T::regs().chselr().write(|reg| {
-            #[cfg(adc_g0)]
-            reg.set_chsel(channel.channel().into(), true);
-            #[cfg(adc_u0)]
-            reg.set_chsel(1 << channel.channel());
-        });
+        if let Some(enable) = config.oversampling_enable {
+            T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
+        }
 
-        // Some models are affected by an erratum:
-        // If we perform conversions slower than 1 kHz, the first read ADC value can be
-        // corrupted, so we discard it and measure again.
-        //
-        // STM32L471xx: Section 2.7.3
-        // STM32G4: Section 2.7.3
-        #[cfg(any(rcc_l4, rcc_g4))]
-        let _ = self.convert();
-        let val = self.convert();
+        #[cfg(adc_v3)]
+        if let Some((mode, trig_mode, enable)) = config.oversampling_mode {
+            T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        }
 
-        T::regs().cr().modify(|reg| reg.set_addis(true));
+        if let Some(resolution) = config.resolution {
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
+            #[cfg(any(adc_g0, adc_u0))]
+            T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
+        }
 
-        // RM0492, RM0481, etc.
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
-            T::regs().or().modify(|reg| reg.set_op0(false));
+        if let Some(averaging) = config.averaging {
+            let (enable, samples, right_shift) = match averaging {
+                Averaging::Disabled => (false, 0, 0),
+                Averaging::Samples2 => (true, 0, 1),
+                Averaging::Samples4 => (true, 1, 2),
+                Averaging::Samples8 => (true, 2, 3),
+                Averaging::Samples16 => (true, 3, 4),
+                Averaging::Samples32 => (true, 4, 5),
+                Averaging::Samples64 => (true, 5, 6),
+                Averaging::Samples128 => (true, 6, 7),
+                Averaging::Samples256 => (true, 7, 8),
+            };
+            T::regs().cfgr2().modify(|reg| {
+                #[cfg(not(any(adc_g0, adc_u0)))]
+                reg.set_rovse(enable);
+                #[cfg(any(adc_g0, adc_u0))]
+                reg.set_ovse(enable);
+                #[cfg(any(adc_h5, adc_h7rs))]
+                reg.set_ovsr(samples.into());
+                #[cfg(not(any(adc_h5, adc_h7rs)))]
+                reg.set_ovsr(samples.into());
+                reg.set_ovss(right_shift.into());
+            })
         }
 
-        val
+        s
     }
 
     #[cfg(adc_g0)]
-    pub fn set_oversampling_shift(&mut self, shift: Ovss) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_shift(&mut self, shift: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
+    /// Initialize ADC with explicit clock for the analog ADC
+    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
+        Self::init_regulator();
 
-    #[cfg(adc_g0)]
-    pub fn set_oversampling_ratio(&mut self, ratio: Ovsr) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
+        #[cfg(any(stm32wl5x))]
+        {
+            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
+            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
+            match clock {
+                Clock::Async { div: _ } => {
+                    assert!(async_clock_available);
+                }
+                Clock::Sync { div: _ } => {
+                    if async_clock_available {
+                        warn!("Not using configured ADC clock");
+                    }
+                }
+            }
+        }
+        match clock {
+            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
+            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
+                reg.set_ckmode(match div {
+                    CkModePclk::DIV1 => Ckmode::PCLK,
+                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
+                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
+                })
+            }),
+        }
 
-    #[cfg(any(adc_g0, adc_u0))]
-    pub fn oversampling_enable(&mut self, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
-    }
+        Self::init_calibrate();
 
-    #[cfg(adc_v3)]
-    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        Self { adc }
     }
 
-    #[cfg(adc_v3)]
-    pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+    pub fn enable_vrefint(&self) -> VrefInt {
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
+
+        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
+        // to stabilize the internal voltage reference.
+        blocking_delay_us(15);
+
+        VrefInt {}
     }
 
-    #[cfg(adc_v3)]
-    pub fn set_oversampling_shift(&mut self, shift: OversamplingShift) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+    pub fn enable_temperature(&self) -> Temperature {
+        cfg_if! {
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch17sel(true);
+                });
+            }
+        }
+
+        Temperature {}
     }
 
-    #[cfg(not(adc_g0))]
-    fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
+    pub fn enable_vbat(&self) -> Vbat {
         cfg_if! {
-            if #[cfg(adc_u0)] {
-                // On G0 and U6 all channels use the same sampling time.
-                T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
             } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                match _ch {
-                    0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
-                    _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
-                }
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
             } else {
-                let sample_time = sample_time.into();
-                T::regs()
-                    .smpr(_ch as usize / 10)
-                    .modify(|reg| reg.set_smp(_ch as usize % 10, sample_time));
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(true);
+                });
             }
         }
+
+        Vbat {}
     }
 
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(true);
-            });
-            while T::regs().cr().read().adstart() {}
+    pub fn disable_vbat(&self) {
+        cfg_if! {
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(false);
+                });
+            }
         }
     }
+
+    /*
+    /// Convert a raw sample from the `Temperature` to deg C
+    pub fn to_degrees_centigrade(sample: u16) -> f32 {
+        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
+            * (sample as f32 - VtempCal30::get().read() as f32)
+            + 30.0
+    }
+     */
 }