aboutsummaryrefslogtreecommitdiff
path: root/embassy-stm32/src/can/bxcan/mod.rs
diff options
context:
space:
mode:
Diffstat (limited to 'embassy-stm32/src/can/bxcan/mod.rs')
-rw-r--r--embassy-stm32/src/can/bxcan/mod.rs12
1 files changed, 6 insertions, 6 deletions
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index 8eb188560..507350c42 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -5,8 +5,8 @@ use core::future::poll_fn;
5use core::marker::PhantomData; 5use core::marker::PhantomData;
6use core::task::Poll; 6use core::task::Poll;
7 7
8use embassy_hal_internal::interrupt::InterruptExt;
9use embassy_hal_internal::PeripheralType; 8use embassy_hal_internal::PeripheralType;
9use embassy_hal_internal::interrupt::InterruptExt;
10use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex; 10use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
11use embassy_sync::channel::Channel; 11use embassy_sync::channel::Channel;
12use embassy_sync::waitqueue::AtomicWaker; 12use embassy_sync::waitqueue::AtomicWaker;
@@ -22,7 +22,7 @@ use crate::can::enums::{BusError, RefCountOp, TryReadError};
22use crate::gpio::{AfType, OutputType, Pull, Speed}; 22use crate::gpio::{AfType, OutputType, Pull, Speed};
23use crate::interrupt::typelevel::Interrupt; 23use crate::interrupt::typelevel::Interrupt;
24use crate::rcc::{self, RccPeripheral}; 24use crate::rcc::{self, RccPeripheral};
25use crate::{interrupt, peripherals, Peri}; 25use crate::{Peri, interrupt, peripherals};
26 26
27/// Interrupt handler. 27/// Interrupt handler.
28pub struct TxInterruptHandler<T: Instance> { 28pub struct TxInterruptHandler<T: Instance> {
@@ -186,10 +186,10 @@ impl<'d> Can<'d> {
186 rx: Peri<'d, if_afio!(impl RxPin<T, A>)>, 186 rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
187 tx: Peri<'d, if_afio!(impl TxPin<T, A>)>, 187 tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
188 _irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>> 188 _irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>>
189 + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>> 189 + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
190 + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>> 190 + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
191 + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>> 191 + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
192 + 'd, 192 + 'd,
193 ) -> Self { 193 ) -> Self {
194 let info = T::info(); 194 let info = T::info();
195 let regs = &T::info().regs; 195 let regs = &T::info().regs;