1 files changed, 9 insertions, 1 deletions

diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index adc45db9c..a3f9e00f7 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -5,13 +5,20 @@ use embedded_storage::nor_flash::{NorFlashError, NorFlashErrorKind};
 mod asynch;
 #[cfg(flash)]
 mod common;
+#[cfg(eeprom)]
+mod eeprom;
 
 #[cfg(flash_f4)]
 pub use asynch::InterruptHandler;
 #[cfg(flash)]
 pub use common::*;
+#[cfg(eeprom)]
+#[allow(unused_imports)]
+pub use eeprom::*;
 
 pub use crate::_generated::flash_regions::*;
+#[cfg(eeprom)]
+pub use crate::_generated::{EEPROM_BASE, EEPROM_SIZE};
 pub use crate::_generated::{FLASH_BASE, FLASH_SIZE, MAX_ERASE_SIZE, WRITE_SIZE};
 
 /// Get all flash regions.
@@ -83,7 +90,8 @@ pub enum FlashBank {
     /// OTP region,
     Otp,
 }
-
+#[cfg(all(eeprom, not(any(flash_l0, flash_l1))))]
+compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is an unsupported configuration.");
 #[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb), path = "l.rs")]
 #[cfg_attr(flash_f0, path = "f0.rs")]
 #[cfg_attr(any(flash_f1, flash_f3), path = "f1f3.rs")]