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Diffstat (limited to 'embassy-stm32/src/qspi/mod.rs')
-rw-r--r--embassy-stm32/src/qspi/mod.rs4
1 files changed, 3 insertions, 1 deletions
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index bb4f4f1d0..1f47f4845 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -111,7 +111,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
111 config: Config, 111 config: Config,
112 fsel: FlashSelection, 112 fsel: FlashSelection,
113 ) -> Self { 113 ) -> Self {
114 rcc::enable_and_reset::<T>(); 114 rcc::enable_and_reset_without_stop::<T>();
115 115
116 while T::REGS.sr().read().busy() {} 116 while T::REGS.sr().read().busy() {}
117 117
@@ -403,6 +403,7 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
403 403
404 /// Async read data, using DMA. 404 /// Async read data, using DMA.
405 pub async fn read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) { 405 pub async fn read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
406 let _scoped_block_stop = T::RCC_INFO.block_stop();
406 let transfer = self.start_read_transfer(transaction, buf); 407 let transfer = self.start_read_transfer(transaction, buf);
407 transfer.await; 408 transfer.await;
408 } 409 }
@@ -443,6 +444,7 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
443 444
444 /// Async write data, using DMA. 445 /// Async write data, using DMA.
445 pub async fn write_dma(&mut self, buf: &[u8], transaction: TransferConfig) { 446 pub async fn write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
447 let _scoped_block_stop = T::RCC_INFO.block_stop();
446 let transfer = self.start_write_transfer(transaction, buf); 448 let transfer = self.start_write_transfer(transaction, buf);
447 transfer.await; 449 transfer.await;
448 } 450 }