10 files changed, 28 insertions, 58 deletions

diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
index 1527afa05..427c958f0 100644
--- a/embassy-stm32/src/rcc/f0.rs
+++ b/embassy-stm32/src/rcc/f0.rs
@@ -1,4 +1,4 @@
-use crate::pac::rcc::vals::{Hpre, Hsebyp, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
+use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
 
@@ -16,7 +16,7 @@ pub struct Config {
     pub bypass_hse: bool,
     pub usb_pll: bool,
 
-    #[cfg(rcc_f0)]
+    #[cfg(not(stm32f0x0))]
     pub hsi48: bool,
 
     pub sys_ck: Option<Hertz>,
@@ -28,7 +28,7 @@ pub(crate) unsafe fn init(config: Config) {
     let sysclk = config.sys_ck.map(|v| v.0).unwrap_or(HSI);
 
     let (src_clk, use_hsi48) = config.hse.map(|v| (v.0, false)).unwrap_or_else(|| {
-        #[cfg(rcc_f0)]
+        #[cfg(not(stm32f0x0))]
         if config.hsi48 {
             return (48_000_000, true);
         }
@@ -97,10 +97,7 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().modify(|w| {
                 w.set_csson(true);
                 w.set_hseon(true);
-
-                if config.bypass_hse {
-                    w.set_hsebyp(Hsebyp::BYPASSED);
-                }
+                w.set_hsebyp(config.bypass_hse);
             });
             while !RCC.cr().read().hserdy() {}
 
@@ -108,14 +105,12 @@ pub(crate) unsafe fn init(config: Config) {
                 RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSE_DIV_PREDIV))
             }
         }
+        // use_hsi48 will always be false for stm32f0x0
+        #[cfg(not(stm32f0x0))]
         (false, true) => {
-            // use_hsi48 will always be false for rcc_f0x0
-            #[cfg(rcc_f0)]
             RCC.cr2().modify(|w| w.set_hsi48on(true));
-            #[cfg(rcc_f0)]
             while !RCC.cr2().read().hsi48rdy() {}
 
-            #[cfg(rcc_f0)]
             if pllmul_bits.is_some() {
                 RCC.cfgr()
                     .modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV))
@@ -155,7 +150,7 @@ pub(crate) unsafe fn init(config: Config) {
             if config.hse.is_some() {
                 w.set_sw(Sw::HSE);
             } else if use_hsi48 {
-                #[cfg(rcc_f0)]
+                #[cfg(not(stm32f0x0))]
                 w.set_sw(Sw::HSI48);
             } else {
                 w.set_sw(Sw::HSI)
@@ -169,6 +164,6 @@ pub(crate) unsafe fn init(config: Config) {
         apb2: Hertz(pclk),
         apb1_tim: Hertz(pclk * timer_mul),
         apb2_tim: Hertz(pclk * timer_mul),
-        ahb: Hertz(hclk),
+        ahb1: Hertz(hclk),
     });
 }
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index d44544d28..ca0883b4a 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -173,7 +173,7 @@ pub(crate) unsafe fn init(config: Config) {
         apb2: Hertz(pclk2),
         apb1_tim: Hertz(pclk1 * timer_mul1),
         apb2_tim: Hertz(pclk2 * timer_mul2),
-        ahb: Hertz(hclk),
+        ahb1: Hertz(hclk),
         adc: Hertz(adcclk),
     });
 }
diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f3.rs
index 2727a5b1c..820915312 100644
--- a/embassy-stm32/src/rcc/f3.rs
+++ b/embassy-stm32/src/rcc/f3.rs
@@ -1,5 +1,5 @@
 use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::{Hpre, Hsebyp, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
+use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
 use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -106,11 +106,7 @@ pub(crate) unsafe fn init(config: Config) {
     // Enable HSE
     if config.hse.is_some() {
         RCC.cr().write(|w| {
-            w.set_hsebyp(if config.bypass_hse {
-                Hsebyp::BYPASSED
-            } else {
-                Hsebyp::NOTBYPASSED
-            });
+            w.set_hsebyp(config.bypass_hse);
             // We turn on clock security to switch to HSI when HSE fails
             w.set_csson(true);
             w.set_hseon(true);
@@ -164,7 +160,7 @@ pub(crate) unsafe fn init(config: Config) {
         apb2: Hertz(pclk2),
         apb1_tim: Hertz(pclk1 * timer_mul1),
         apb2_tim: Hertz(pclk2 * timer_mul2),
-        ahb: Hertz(hclk),
+        ahb1: Hertz(hclk),
     });
 }
 
diff --git a/embassy-stm32/src/rcc/f4.rs b/embassy-stm32/src/rcc/f4.rs
index aba8fc0ef..22a2e9ad0 100644
--- a/embassy-stm32/src/rcc/f4.rs
+++ b/embassy-stm32/src/rcc/f4.rs
@@ -1,5 +1,5 @@
 use super::sealed::RccPeripheral;
-use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
+use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
 use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -200,7 +200,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     if config.hse.is_some() {
         RCC.cr().modify(|w| {
-            w.set_hsebyp(Hsebyp(config.bypass_hse as u8));
+            w.set_hsebyp(config.bypass_hse);
             w.set_hseon(true);
         });
         while !RCC.cr().read().hserdy() {}
diff --git a/embassy-stm32/src/rcc/f7.rs b/embassy-stm32/src/rcc/f7.rs
index 1a0530296..9f2c63c16 100644
--- a/embassy-stm32/src/rcc/f7.rs
+++ b/embassy-stm32/src/rcc/f7.rs
@@ -1,6 +1,6 @@
 use super::sealed::RccPeripheral;
 use crate::pac::pwr::vals::Vos;
-use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
+use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
 use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -213,7 +213,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     if config.hse.is_some() {
         RCC.cr().modify(|w| {
-            w.set_hsebyp(Hsebyp(config.bypass_hse as u8));
+            w.set_hsebyp(config.bypass_hse);
             w.set_hseon(true);
         });
         while !RCC.cr().read().hserdy() {}
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index a3a4c197f..71d44fd3c 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -176,8 +176,8 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk.hz(),
-        ahb: ahb_freq.hz(),
-        apb: apb_freq.hz(),
-        apb_tim: apb_tim_freq.hz(),
+        ahb1: ahb_freq.hz(),
+        apb1: apb_freq.hz(),
+        apb1_tim: apb_tim_freq.hz(),
     });
 }
diff --git a/embassy-stm32/src/rcc/h7.rs b/embassy-stm32/src/rcc/h7.rs
index 23c916365..1b2c595b3 100644
--- a/embassy-stm32/src/rcc/h7.rs
+++ b/embassy-stm32/src/rcc/h7.rs
@@ -7,7 +7,7 @@ use stm32_metapac::rcc::vals::{Mco1, Mco2};
 use crate::gpio::sealed::AFType;
 use crate::gpio::Speed;
 use crate::pac::rcc::vals::Timpre;
-use crate::pac::rcc::vals::{Ckpersel, Dppre, Hpre, Hsebyp, Hsidiv, Pllsrc, Sw};
+use crate::pac::rcc::vals::{Ckpersel, Dppre, Hpre, Hsidiv, Pllsrc, Sw};
 use crate::pac::{PWR, RCC, SYSCFG};
 use crate::peripherals;
 use crate::rcc::{set_freqs, Clocks};
@@ -569,11 +569,7 @@ pub(crate) unsafe fn init(mut config: Config) {
             // Ensure HSE is on and stable
             RCC.cr().modify(|w| {
                 w.set_hseon(true);
-                w.set_hsebyp(if config.bypass_hse {
-                    Hsebyp::BYPASSED
-                } else {
-                    Hsebyp::NOTBYPASSED
-                });
+                w.set_hsebyp(config.bypass_hse);
             });
             while !RCC.cr().read().hserdy() {}
             Some(hse)
diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs
index 25daeedf0..e482dcc21 100644
--- a/embassy-stm32/src/rcc/l0.rs
+++ b/embassy-stm32/src/rcc/l0.rs
@@ -353,7 +353,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk.hz(),
-        ahb: ahb_freq.hz(),
+        ahb1: ahb_freq.hz(),
         apb1: apb1_freq.hz(),
         apb2: apb2_freq.hz(),
         apb1_tim: apb1_tim_freq.hz(),
diff --git a/embassy-stm32/src/rcc/l1.rs b/embassy-stm32/src/rcc/l1.rs
index 904e6ab5d..dfcbd4f21 100644
--- a/embassy-stm32/src/rcc/l1.rs
+++ b/embassy-stm32/src/rcc/l1.rs
@@ -319,7 +319,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk.hz(),
-        ahb: ahb_freq.hz(),
+        ahb1: ahb_freq.hz(),
         apb1: apb1_freq.hz(),
         apb2: apb2_freq.hz(),
         apb1_tim: apb1_tim_freq.hz(),
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 3aab01afd..5c223bc43 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -3,7 +3,7 @@
 use crate::time::Hertz;
 use core::mem::MaybeUninit;
 
-#[cfg_attr(any(rcc_f0, rcc_f0x0), path = "f0.rs")]
+#[cfg_attr(rcc_f0, path = "f0.rs")]
 #[cfg_attr(rcc_f1, path = "f1.rs")]
 #[cfg_attr(rcc_f3, path = "f3.rs")]
 #[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")]
@@ -24,46 +24,29 @@ pub use _version::*;
 pub struct Clocks {
     pub sys: Hertz,
 
-    #[cfg(rcc_g0)]
-    pub apb: Hertz,
-    #[cfg(rcc_g0)]
-    pub apb_tim: Hertz,
-
-    #[cfg(not(rcc_g0))]
+    // APB
     pub apb1: Hertz,
-    #[cfg(not(rcc_g0))]
     pub apb1_tim: Hertz,
-
     #[cfg(not(rcc_g0))]
     pub apb2: Hertz,
     #[cfg(not(rcc_g0))]
     pub apb2_tim: Hertz,
-
     #[cfg(any(rcc_wl5, rcc_u5))]
     pub apb3: Hertz,
+    #[cfg(any(rcc_h7))]
+    pub apb4: Hertz,
 
-    #[cfg(any(rcc_l0, rcc_l1, rcc_f0, rcc_f1, rcc_f3, rcc_f0x0, rcc_g0))]
-    pub ahb: Hertz,
-
-    #[cfg(any(
-        rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_g4, rcc_u5, rcc_wb, rcc_wl5
-    ))]
+    // AHB
     pub ahb1: Hertz,
-
     #[cfg(any(
         rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_g4, rcc_u5, rcc_wb, rcc_wl5
     ))]
     pub ahb2: Hertz,
-
     #[cfg(any(rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_u5, rcc_wb, rcc_wl5))]
     pub ahb3: Hertz,
-
     #[cfg(any(rcc_h7))]
     pub ahb4: Hertz,
 
-    #[cfg(any(rcc_h7))]
-    pub apb4: Hertz,
-
     #[cfg(any(rcc_f4, rcc_f410, rcc_f7))]
     pub pll48: Option<Hertz>,