1 files changed, 71 insertions, 120 deletions

diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index aba08081f..73a81bff1 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -268,6 +268,11 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         unsafe { crate::pac::timer::TimGp32::from_ptr(T::regs()) }
     }
 
+    #[cfg(stm32l0)]
+    fn regs_gp32_unchecked(&self) -> crate::pac::timer::TimGp16 {
+        unsafe { crate::pac::timer::TimGp16::from_ptr(T::regs()) }
+    }
+
     /// Start the timer.
     pub fn start(&self) {
         self.regs_core().cr1().modify(|r| r.set_cen(true));
@@ -296,7 +301,12 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
 
     /// get the capability of the timer
     pub fn bits(&self) -> TimerBits {
-        T::BITS
+        match T::Word::bits() {
+            16 => TimerBits::Bits16,
+            #[cfg(not(stm32l0))]
+            32 => TimerBits::Bits32,
+            _ => unreachable!(),
+        }
     }
 
     /// Set the frequency of how many times per second the timer counts up to the max value or down to 0.
@@ -306,18 +316,10 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     /// In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved
     /// because it needs to count up and down.
     pub fn set_frequency(&self, frequency: Hertz) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                self.set_frequency_internal(frequency, 16);
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                self.set_frequency_internal(frequency, 32);
-            }
-        }
+        self.set_frequency_internal(frequency, T::Word::bits());
     }
 
-    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: u8) {
+    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: usize) {
         let f = frequency.0;
         assert!(f > 0);
         let timer_f = T::frequency().0;
@@ -326,25 +328,15 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << max_divide_by_bits)).try_into());
         let divide_by = pclk_ticks_per_timer_period / (u64::from(psc) + 1);
 
-        match T::BITS {
-            TimerBits::Bits16 => {
-                // the timer counts `0..=arr`, we want it to count `0..divide_by`
-                let arr = unwrap!(u16::try_from(divide_by - 1));
-
-                let regs = self.regs_core();
-                regs.psc().write_value(psc);
-                regs.arr().write(|r| r.set_arr(arr));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                // the timer counts `0..=arr`, we want it to count `0..divide_by`
-                let arr: u32 = unwrap!(u32::try_from(divide_by - 1));
+        // the timer counts `0..=arr`, we want it to count `0..divide_by`
+        let arr: T::Word = unwrap!(T::Word::try_from(divide_by - 1));
 
-                let regs = self.regs_gp32_unchecked();
-                regs.psc().write_value(psc);
-                regs.arr().write_value(arr);
-            }
-        }
+        let regs = self.regs_gp32_unchecked();
+        regs.psc().write_value(psc);
+        #[cfg(stm32l0)]
+        regs.arr().write(|r| r.set_arr(unwrap!(arr.try_into())));
+        #[cfg(not(stm32l0))]
+        regs.arr().write_value(arr.into());
     }
 
     /// Set tick frequency.
@@ -393,23 +385,14 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     pub fn get_frequency(&self) -> Hertz {
         let timer_f = T::frequency();
 
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let regs = self.regs_core();
-                let arr = regs.arr().read().arr();
-                let psc = regs.psc().read();
+        let regs = self.regs_gp32_unchecked();
+        #[cfg(not(stm32l0))]
+        let arr = regs.arr().read();
+        #[cfg(stm32l0)]
+        let arr = regs.arr().read().arr();
+        let psc = regs.psc().read();
 
-                timer_f / arr / (psc + 1)
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                let regs = self.regs_gp32_unchecked();
-                let arr = regs.arr().read();
-                let psc = regs.psc().read();
-
-                timer_f / arr / (psc + 1)
-            }
-        }
+        timer_f / arr / (psc + 1)
     }
 
     /// Get the clock frequency of the timer (before prescaler is applied).
@@ -469,42 +452,29 @@ impl<'d, T: GeneralInstance1Channel> Timer<'d, T> {
     }
 
     /// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
-    pub fn get_max_compare_value(&self) -> u32 {
-        match T::BITS {
-            TimerBits::Bits16 => self.regs_1ch().arr().read().arr() as u32,
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => self.regs_gp32_unchecked().arr().read(),
-        }
+    pub fn get_max_compare_value(&self) -> T::Word {
+        #[cfg(not(stm32l0))]
+        return unwrap!(self.regs_gp32_unchecked().arr().read().try_into());
+        #[cfg(stm32l0)]
+        return unwrap!(self.regs_gp32_unchecked().arr().read().arr().try_into());
     }
 
     /// Set the max compare value.
     ///
     /// An update event is generated to load the new value. The update event is
     /// generated such that it will not cause an interrupt or DMA request.
-    pub fn set_max_compare_value(&self, ticks: u32) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let arr = unwrap!(u16::try_from(ticks));
+    pub fn set_max_compare_value(&self, ticks: T::Word) {
+        let arr = ticks;
 
-                let regs = self.regs_1ch();
-                regs.arr().write(|r| r.set_arr(arr));
+        let regs = self.regs_gp32_unchecked();
+        #[cfg(not(stm32l0))]
+        regs.arr().write_value(arr.into());
+        #[cfg(stm32l0)]
+        regs.arr().write(|r| r.set_arr(unwrap!(arr.try_into())));
 
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                let arr = ticks;
-
-                let regs = self.regs_gp32_unchecked();
-                regs.arr().write_value(arr);
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
-            }
-        }
+        regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+        regs.egr().write(|r| r.set_ug(true));
+        regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
     }
 }
 
@@ -638,26 +608,23 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     }
 
     /// Set compare value for a channel.
-    pub fn set_compare_value(&self, channel: Channel, value: u32) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let value = unwrap!(u16::try_from(value));
-                self.regs_gp16().ccr(channel.index()).modify(|w| w.set_ccr(value));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                self.regs_gp32_unchecked().ccr(channel.index()).write_value(value);
-            }
-        }
+    pub fn set_compare_value(&self, channel: Channel, value: T::Word) {
+        #[cfg(not(stm32l0))]
+        self.regs_gp32_unchecked()
+            .ccr(channel.index())
+            .write_value(value.into());
+        #[cfg(stm32l0)]
+        self.regs_gp16()
+            .ccr(channel.index())
+            .modify(|w| w.set_ccr(unwrap!(value.try_into())));
     }
 
     /// Get compare value for a channel.
-    pub fn get_compare_value(&self, channel: Channel) -> u32 {
-        match T::BITS {
-            TimerBits::Bits16 => self.regs_gp16().ccr(channel.index()).read().ccr() as u32,
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => self.regs_gp32_unchecked().ccr(channel.index()).read(),
-        }
+    pub fn get_compare_value(&self, channel: Channel) -> T::Word {
+        #[cfg(not(stm32l0))]
+        return unwrap!(self.regs_gp32_unchecked().ccr(channel.index()).read().try_into());
+        #[cfg(stm32l0)]
+        return unwrap!(self.regs_gp32_unchecked().ccr(channel.index()).read().ccr().try_into());
     }
 
     /// Setup a ring buffer for the channel
@@ -665,8 +632,8 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        dma_buf: &'a mut [u16],
-    ) -> WritableRingBuffer<'a, u16> {
+        dma_buf: &'a mut [T::Word],
+    ) -> WritableRingBuffer<'a, T::Word> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
 
@@ -686,7 +653,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
             WritableRingBuffer::new(
                 dma,
                 req,
-                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut T::Word,
                 dma_buf,
                 dma_transfer_option,
             )
@@ -701,7 +668,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        duty: &'a [u16],
+        duty: &'a [T::Word],
     ) -> Transfer<'a> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
@@ -719,29 +686,13 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 ..Default::default()
             };
 
-            match self.bits() {
-                TimerBits::Bits16 => Transfer::new_write(
-                    dma,
-                    req,
-                    duty,
-                    self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
-                    dma_transfer_option,
-                ),
-                #[cfg(not(any(stm32l0)))]
-                TimerBits::Bits32 => {
-                    #[cfg(not(any(bdma, gpdma)))]
-                    panic!("unsupported timer bits");
-
-                    #[cfg(any(bdma, gpdma))]
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
-                        dma_transfer_option,
-                    )
-                }
-            }
+            Transfer::new_write(
+                dma,
+                req,
+                duty,
+                self.regs_gp16().ccr(channel.index()).as_ptr() as *mut T::Word,
+                dma_transfer_option,
+            )
         }
     }
 
@@ -779,7 +730,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         dma: Peri<'a, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &'a [u16],
+        duty: &'a [T::Word],
     ) -> Transfer<'a> {
         let cr1_addr = self.regs_gp16().cr1().as_ptr() as u32;
         let start_ch_index = starting_channel.index();
@@ -815,14 +766,14 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 dma,
                 req,
                 duty,
-                self.regs_gp16().dmar().as_ptr() as *mut u16,
+                self.regs_gp16().dmar().as_ptr() as *mut T::Word,
                 dma_transfer_option,
             )
         }
     }
 
     /// Get capture value for a channel.
-    pub fn get_capture_value(&self, channel: Channel) -> u32 {
+    pub fn get_capture_value(&self, channel: Channel) -> T::Word {
         self.get_compare_value(channel)
     }