1 files changed, 25 insertions, 0 deletions

diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index dc8ceb725..01bf60869 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -686,6 +686,16 @@ impl<'d, T: AdvancedInstance1Channel> Timer<'d, T> {
         self.regs_1ch_cmp().bdtr().modify(|w| w.set_dtg(value));
     }
 
+    /// Set state of OSSI-bit in BDTR register
+    pub fn set_ossi(&self, val: vals::Ossi) {
+        self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossi(val));
+    }
+
+    /// Set state of OSSR-bit in BDTR register
+    pub fn set_ossr(&self, val: vals::Ossr) {
+        self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossr(val));
+    }
+
     /// Set state of MOE-bit in BDTR register to en-/disable output
     pub fn set_moe(&self, enable: bool) {
         self.regs_1ch_cmp().bdtr().modify(|w| w.set_moe(enable));
@@ -725,4 +735,19 @@ impl<'d, T: AdvancedInstance4Channel> Timer<'d, T> {
             .ccer()
             .modify(|w| w.set_ccne(channel.index(), enable));
     }
+
+    /// Set Output Idle State
+    pub fn set_ois(&self, channel: Channel, val: bool) {
+        self.regs_advanced().cr2().modify(|w| w.set_ois(channel.index(), val));
+    }
+    /// Set Output Idle State Complementary Channel
+    pub fn set_oisn(&self, channel: Channel, val: bool) {
+        self.regs_advanced().cr2().modify(|w| w.set_oisn(channel.index(), val));
+    }
+
+    /// Trigger software break 1 or 2
+    /// Setting this bit generates a break event. This bit is automatically cleared by the hardware.
+    pub fn trigger_software_break(&self, n: usize) {
+        self.regs_advanced().egr().write(|r| r.set_bg(n, true));
+    }
 }