diff options
Diffstat (limited to 'embassy-stm32/src/timer/mod.rs')
| -rw-r--r-- | embassy-stm32/src/timer/mod.rs | 64 |
1 files changed, 25 insertions, 39 deletions
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs index 14db97024..09b7a3776 100644 --- a/embassy-stm32/src/timer/mod.rs +++ b/embassy-stm32/src/timer/mod.rs | |||
| @@ -60,25 +60,19 @@ macro_rules! impl_basic_16bit_timer { | |||
| 60 | type Interrupt = crate::interrupt::typelevel::$irq; | 60 | type Interrupt = crate::interrupt::typelevel::$irq; |
| 61 | 61 | ||
| 62 | fn regs() -> crate::pac::timer::TimBasic { | 62 | fn regs() -> crate::pac::timer::TimBasic { |
| 63 | crate::pac::timer::TimBasic(crate::pac::$inst.0) | 63 | unsafe { crate::pac::timer::TimBasic::from_ptr(crate::pac::$inst.as_ptr()) } |
| 64 | } | 64 | } |
| 65 | 65 | ||
| 66 | fn start(&mut self) { | 66 | fn start(&mut self) { |
| 67 | unsafe { | 67 | Self::regs().cr1().modify(|r| r.set_cen(true)); |
| 68 | Self::regs().cr1().modify(|r| r.set_cen(true)); | ||
| 69 | } | ||
| 70 | } | 68 | } |
| 71 | 69 | ||
| 72 | fn stop(&mut self) { | 70 | fn stop(&mut self) { |
| 73 | unsafe { | 71 | Self::regs().cr1().modify(|r| r.set_cen(false)); |
| 74 | Self::regs().cr1().modify(|r| r.set_cen(false)); | ||
| 75 | } | ||
| 76 | } | 72 | } |
| 77 | 73 | ||
| 78 | fn reset(&mut self) { | 74 | fn reset(&mut self) { |
| 79 | unsafe { | 75 | Self::regs().cnt().write(|r| r.set_cnt(0)); |
| 80 | Self::regs().cnt().write(|r| r.set_cnt(0)); | ||
| 81 | } | ||
| 82 | } | 76 | } |
| 83 | 77 | ||
| 84 | fn set_frequency(&mut self, frequency: Hertz) { | 78 | fn set_frequency(&mut self, frequency: Hertz) { |
| @@ -90,35 +84,29 @@ macro_rules! impl_basic_16bit_timer { | |||
| 90 | let arr: u16 = unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into()); | 84 | let arr: u16 = unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into()); |
| 91 | 85 | ||
| 92 | let regs = Self::regs(); | 86 | let regs = Self::regs(); |
| 93 | unsafe { | 87 | regs.psc().write(|r| r.set_psc(psc)); |
| 94 | regs.psc().write(|r| r.set_psc(psc)); | 88 | regs.arr().write(|r| r.set_arr(arr)); |
| 95 | regs.arr().write(|r| r.set_arr(arr)); | ||
| 96 | 89 | ||
| 97 | regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY)); | 90 | regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY)); |
| 98 | regs.egr().write(|r| r.set_ug(true)); | 91 | regs.egr().write(|r| r.set_ug(true)); |
| 99 | regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT)); | 92 | regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT)); |
| 100 | } | ||
| 101 | } | 93 | } |
| 102 | 94 | ||
| 103 | fn clear_update_interrupt(&mut self) -> bool { | 95 | fn clear_update_interrupt(&mut self) -> bool { |
| 104 | let regs = Self::regs(); | 96 | let regs = Self::regs(); |
| 105 | unsafe { | 97 | let sr = regs.sr().read(); |
| 106 | let sr = regs.sr().read(); | 98 | if sr.uif() { |
| 107 | if sr.uif() { | 99 | regs.sr().modify(|r| { |
| 108 | regs.sr().modify(|r| { | 100 | r.set_uif(false); |
| 109 | r.set_uif(false); | 101 | }); |
| 110 | }); | 102 | true |
| 111 | true | 103 | } else { |
| 112 | } else { | 104 | false |
| 113 | false | ||
| 114 | } | ||
| 115 | } | 105 | } |
| 116 | } | 106 | } |
| 117 | 107 | ||
| 118 | fn enable_update_interrupt(&mut self, enable: bool) { | 108 | fn enable_update_interrupt(&mut self, enable: bool) { |
| 119 | unsafe { | 109 | Self::regs().dier().write(|r| r.set_uie(enable)); |
| 120 | Self::regs().dier().write(|r| r.set_uie(enable)); | ||
| 121 | } | ||
| 122 | } | 110 | } |
| 123 | } | 111 | } |
| 124 | }; | 112 | }; |
| @@ -141,14 +129,12 @@ macro_rules! impl_32bit_timer { | |||
| 141 | let arr: u32 = unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into())); | 129 | let arr: u32 = unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into())); |
| 142 | 130 | ||
| 143 | let regs = Self::regs_gp32(); | 131 | let regs = Self::regs_gp32(); |
| 144 | unsafe { | 132 | regs.psc().write(|r| r.set_psc(psc)); |
| 145 | regs.psc().write(|r| r.set_psc(psc)); | 133 | regs.arr().write(|r| r.set_arr(arr)); |
| 146 | regs.arr().write(|r| r.set_arr(arr)); | ||
| 147 | 134 | ||
| 148 | regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY)); | 135 | regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY)); |
| 149 | regs.egr().write(|r| r.set_ug(true)); | 136 | regs.egr().write(|r| r.set_ug(true)); |
| 150 | regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT)); | 137 | regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT)); |
| 151 | } | ||
| 152 | } | 138 | } |
| 153 | } | 139 | } |
| 154 | }; | 140 | }; |
| @@ -185,7 +171,7 @@ foreach_interrupt! { | |||
| 185 | 171 | ||
| 186 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { | 172 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { |
| 187 | fn regs_gp16() -> crate::pac::timer::TimGp16 { | 173 | fn regs_gp16() -> crate::pac::timer::TimGp16 { |
| 188 | crate::pac::timer::TimGp16(crate::pac::$inst.0) | 174 | unsafe { crate::pac::timer::TimGp16::from_ptr(crate::pac::$inst.as_ptr()) } |
| 189 | } | 175 | } |
| 190 | } | 176 | } |
| 191 | 177 | ||
| @@ -206,7 +192,7 @@ foreach_interrupt! { | |||
| 206 | 192 | ||
| 207 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { | 193 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { |
| 208 | fn regs_gp16() -> crate::pac::timer::TimGp16 { | 194 | fn regs_gp16() -> crate::pac::timer::TimGp16 { |
| 209 | crate::pac::timer::TimGp16(crate::pac::$inst.0) | 195 | unsafe { crate::pac::timer::TimGp16::from_ptr(crate::pac::$inst.as_ptr()) } |
| 210 | } | 196 | } |
| 211 | } | 197 | } |
| 212 | 198 | ||