1 files changed, 9 insertions, 8 deletions

diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
index c024b2ed6..c315e2320 100644
--- a/embassy-stm32/src/xspi/mod.rs
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -335,8 +335,17 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
             w.set_prescaler(config.clock_prescaler);
         });
 
+        // Wait for busy flag to clear after changing prescaler, during calibration
+        while T::REGS.sr().read().busy() {}
+
         T::REGS.cr().modify(|w| {
             w.set_dmm(dual_quad);
+
+            // TODO: at the moment only ncs1 seems to get passed in?
+            // Only one must be selected
+            assert!(!(ncs1.is_some() && ncs2.is_some()));
+            assert!(!(ncs1.is_none() && ncs2.is_none()));
+            w.set_cssel(if ncs1.is_some() { Cssel::B_0X0 } else { Cssel::B_0X1 });
         });
 
         T::REGS.tcr().modify(|w| {
@@ -344,14 +353,6 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
             w.set_dhqc(config.delay_hold_quarter_cycle);
         });
 
-        // TODO: at the moment only ncs1 seems to get passed in?
-        // Only one must be selected
-        assert!(!(ncs1.is_some() && ncs2.is_some()));
-        assert!(!(ncs1.is_none() && ncs2.is_none()));
-        T::REGS.cr().modify(|w| {
-            w.set_cssel(if ncs1.is_some() { Cssel::B_0X0 } else { Cssel::B_0X1 });
-        });
-
         // Enable peripheral
         T::REGS.cr().modify(|w| {
             w.set_en(true);