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-rw-r--r--examples/boot/bootloader/stm32/src/main.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/boot/bootloader/stm32/src/main.rs b/examples/boot/bootloader/stm32/src/main.rs
index 99a7a6a6b..f74edd75f 100644
--- a/examples/boot/bootloader/stm32/src/main.rs
+++ b/examples/boot/bootloader/stm32/src/main.rs
@@ -32,8 +32,8 @@ fn main() -> ! {
32 unsafe { bl.load(BANK1_REGION.base + active_offset) } 32 unsafe { bl.load(BANK1_REGION.base + active_offset) }
33} 33}
34 34
35#[no_mangle] 35#[unsafe(no_mangle)]
36#[cfg_attr(target_os = "none", link_section = ".HardFault.user")] 36#[cfg_attr(target_os = "none", unsafe(link_section = ".HardFault.user"))]
37unsafe extern "C" fn HardFault() { 37unsafe extern "C" fn HardFault() {
38 cortex_m::peripheral::SCB::sys_reset(); 38 cortex_m::peripheral::SCB::sys_reset();
39} 39}
@@ -41,7 +41,7 @@ unsafe extern "C" fn HardFault() {
41#[exception] 41#[exception]
42unsafe fn DefaultHandler(_: i16) -> ! { 42unsafe fn DefaultHandler(_: i16) -> ! {
43 const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32; 43 const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
44 let irqn = core::ptr::read_volatile(SCB_ICSR) as u8 as i16 - 16; 44 let irqn = unsafe { core::ptr::read_volatile(SCB_ICSR) } as u8 as i16 - 16;
45 45
46 panic!("DefaultHandler #{:?}", irqn); 46 panic!("DefaultHandler #{:?}", irqn);
47} 47}