aboutsummaryrefslogtreecommitdiff
path: root/examples/stm32h755cm7
diff options
context:
space:
mode:
Diffstat (limited to 'examples/stm32h755cm7')
-rw-r--r--examples/stm32h755cm7/src/bin/intercore.rs4
1 files changed, 3 insertions, 1 deletions
diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs
index 5783d05e1..464357185 100644
--- a/examples/stm32h755cm7/src/bin/intercore.rs
+++ b/examples/stm32h755cm7/src/bin/intercore.rs
@@ -48,6 +48,7 @@ mod shared {
48 48
49 /// Get LED state using safe bit operations 49 /// Get LED state using safe bit operations
50 #[inline(never)] 50 #[inline(never)]
51 #[allow(dead_code)]
51 pub fn get_led(&self, is_green: bool) -> bool { 52 pub fn get_led(&self, is_green: bool) -> bool {
52 let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; 53 let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT };
53 54
@@ -69,6 +70,7 @@ mod shared {
69 70
70 /// Get counter without incrementing 71 /// Get counter without incrementing
71 #[inline(never)] 72 #[inline(never)]
73 #[allow(dead_code)]
72 pub fn get_counter(&self) -> u32 { 74 pub fn get_counter(&self) -> u32 {
73 let value = self.counter.load(Ordering::SeqCst); 75 let value = self.counter.load(Ordering::SeqCst);
74 core::sync::atomic::compiler_fence(Ordering::SeqCst); 76 core::sync::atomic::compiler_fence(Ordering::SeqCst);
@@ -144,7 +146,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) {
144} 146}
145 147
146#[embassy_executor::main] 148#[embassy_executor::main]
147async fn main(spawner: Spawner) -> ! { 149async fn main(_spawner: Spawner) -> ! {
148 // Configure MPU to make SRAM4 non-cacheable 150 // Configure MPU to make SRAM4 non-cacheable
149 { 151 {
150 let mut cp = cortex_m::Peripherals::take().unwrap(); 152 let mut cp = cortex_m::Peripherals::take().unwrap();