4 files changed, 4 insertions, 4 deletions

diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index 3d0c623fd..a0ec5c33e 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -13,7 +13,7 @@ fn main() -> ! {
     info!("Hello World!");
 
     pac::RCC.ccipr().modify(|w| {
-        w.set_adcsel(pac::rcc::vals::Adcsel::SYSCLK);
+        w.set_adcsel(pac::rcc::vals::Adcsel::SYS);
     });
     pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
 
diff --git a/examples/stm32l4/src/bin/mco.rs b/examples/stm32l4/src/bin/mco.rs
index 2833bb636..504879887 100644
--- a/examples/stm32l4/src/bin/mco.rs
+++ b/examples/stm32l4/src/bin/mco.rs
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let _mco = Mco::new(p.MCO, p.PA8, McoSource::HSI16, McoPrescaler::DIV1);
+    let _mco = Mco::new(p.MCO, p.PA8, McoSource::HSI, McoPrescaler::DIV1);
 
     let mut led = Output::new(p.PB14, Level::High, Speed::Low);
 
diff --git a/examples/stm32l4/src/bin/rng.rs b/examples/stm32l4/src/bin/rng.rs
index d184bcf77..49ae15e6b 100644
--- a/examples/stm32l4/src/bin/rng.rs
+++ b/examples/stm32l4/src/bin/rng.rs
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hsi16 = true;
     config.rcc.pll = Some(Pll {
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL18,
         divp: None,
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index 3785c6898..34361d112 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -27,7 +27,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hsi16 = true;
     config.rcc.pll = Some(Pll {
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,