diff options
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/stm32f7/src/bin/qspi.rs | 4 | ||||
| -rw-r--r-- | examples/stm32h7b0/src/bin/ospi_memory_mapped.rs | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs index 90d319b7a..bd3287964 100644 --- a/examples/stm32f7/src/bin/qspi.rs +++ b/examples/stm32f7/src/bin/qspi.rs | |||
| @@ -72,7 +72,7 @@ impl<I: Instance> FlashMemory<I> { | |||
| 72 | address: None, | 72 | address: None, |
| 73 | dummy: DummyCycles::_0, | 73 | dummy: DummyCycles::_0, |
| 74 | }; | 74 | }; |
| 75 | self.qspi.command(transaction); | 75 | self.qspi.blocking_command(transaction); |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | pub fn reset_memory(&mut self) { | 78 | pub fn reset_memory(&mut self) { |
| @@ -143,7 +143,7 @@ impl<I: Instance> FlashMemory<I> { | |||
| 143 | dummy: DummyCycles::_0, | 143 | dummy: DummyCycles::_0, |
| 144 | }; | 144 | }; |
| 145 | self.enable_write(); | 145 | self.enable_write(); |
| 146 | self.qspi.command(transaction); | 146 | self.qspi.blocking_command(transaction); |
| 147 | self.wait_write_finish(); | 147 | self.wait_write_finish(); |
| 148 | } | 148 | } |
| 149 | 149 | ||
diff --git a/examples/stm32h7b0/src/bin/ospi_memory_mapped.rs b/examples/stm32h7b0/src/bin/ospi_memory_mapped.rs index 9c397e507..dffb740a9 100644 --- a/examples/stm32h7b0/src/bin/ospi_memory_mapped.rs +++ b/examples/stm32h7b0/src/bin/ospi_memory_mapped.rs | |||
| @@ -223,7 +223,7 @@ impl<I: Instance> FlashMemory<I> { | |||
| 223 | dummy: DummyCycles::_0, | 223 | dummy: DummyCycles::_0, |
| 224 | ..Default::default() | 224 | ..Default::default() |
| 225 | }; | 225 | }; |
| 226 | self.ospi.command(&transaction).await.unwrap(); | 226 | self.ospi.blocking_command(&transaction).unwrap(); |
| 227 | } | 227 | } |
| 228 | 228 | ||
| 229 | async fn exec_command(&mut self, cmd: u8) { | 229 | async fn exec_command(&mut self, cmd: u8) { |
| @@ -238,7 +238,7 @@ impl<I: Instance> FlashMemory<I> { | |||
| 238 | ..Default::default() | 238 | ..Default::default() |
| 239 | }; | 239 | }; |
| 240 | // info!("Excuting command: {:x}", transaction.instruction); | 240 | // info!("Excuting command: {:x}", transaction.instruction); |
| 241 | self.ospi.command(&transaction).await.unwrap(); | 241 | self.ospi.blocking_command(&transaction).unwrap(); |
| 242 | } | 242 | } |
| 243 | 243 | ||
| 244 | pub async fn reset_memory(&mut self) { | 244 | pub async fn reset_memory(&mut self) { |
| @@ -318,7 +318,7 @@ impl<I: Instance> FlashMemory<I> { | |||
| 318 | ..Default::default() | 318 | ..Default::default() |
| 319 | }; | 319 | }; |
| 320 | self.enable_write().await; | 320 | self.enable_write().await; |
| 321 | self.ospi.command(&transaction).await.unwrap(); | 321 | self.ospi.blocking_command(&transaction).unwrap(); |
| 322 | self.wait_write_finish(); | 322 | self.wait_write_finish(); |
| 323 | } | 323 | } |
| 324 | 324 | ||
