1 files changed, 242 insertions, 1 deletions

diff --git a/src/gpio.rs b/src/gpio.rs
index 4f79aff93..332c4c8b2 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -3,13 +3,96 @@
 //! concrete pin type.
 
 use core::convert::Infallible;
+use core::future::Future;
 use core::marker::PhantomData;
+use core::pin::pin;
 
 use embassy_hal_internal::{Peri, PeripheralType};
+use maitake_sync::WaitMap;
 use paste::paste;
 
+use crate::pac::interrupt;
 use crate::pac::port0::pcr0::{Dse, Inv, Mux, Pe, Ps, Sre};
 
+struct BitIter(u32);
+
+impl Iterator for BitIter {
+    type Item = usize;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        match self.0.trailing_zeros() {
+            32 => None,
+            b => {
+                self.0 &= !(1 << b);
+                Some(b as usize)
+            }
+        }
+    }
+}
+
+const PORT_COUNT: usize = 5;
+
+static PORT_WAIT_MAPS: [WaitMap<usize, ()>; PORT_COUNT] = [
+    WaitMap::new(),
+    WaitMap::new(),
+    WaitMap::new(),
+    WaitMap::new(),
+    WaitMap::new(),
+];
+
+fn irq_handler(port_index: usize, gpio_base: *const crate::pac::gpio0::RegisterBlock) {
+    let gpio = unsafe { &*gpio_base };
+    let isfr = gpio.isfr0().read().bits();
+
+    for pin in BitIter(isfr) {
+        // Clear all pending interrupts
+        gpio.isfr0().write(|w| unsafe { w.bits(1 << pin) });
+        gpio.icr(pin).modify(|_, w| w.irqc().irqc0()); // Disable interrupt
+
+        // Wake the corresponding port waker
+        if let Some(w) = PORT_WAIT_MAPS.get(port_index) {
+            w.wake(&pin, ());
+        }
+    }
+}
+
+#[interrupt]
+fn GPIO0() {
+    irq_handler(0, crate::pac::Gpio0::ptr());
+}
+
+#[interrupt]
+fn GPIO1() {
+    irq_handler(1, crate::pac::Gpio1::ptr());
+}
+
+#[interrupt]
+fn GPIO2() {
+    irq_handler(2, crate::pac::Gpio2::ptr());
+}
+
+#[interrupt]
+fn GPIO3() {
+    irq_handler(3, crate::pac::Gpio3::ptr());
+}
+
+#[interrupt]
+fn GPIO4() {
+    irq_handler(4, crate::pac::Gpio4::ptr());
+}
+
+pub(crate) unsafe fn init() {
+    use embassy_hal_internal::interrupt::InterruptExt;
+
+    crate::pac::interrupt::GPIO0.enable();
+    crate::pac::interrupt::GPIO1.enable();
+    crate::pac::interrupt::GPIO2.enable();
+    crate::pac::interrupt::GPIO3.enable();
+    crate::pac::interrupt::GPIO4.enable();
+
+    cortex_m::interrupt::enable();
+}
+
 /// Logical level for GPIO pins.
 #[derive(Copy, Clone, Eq, PartialEq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -598,6 +681,77 @@ impl<'d> Flex<'d> {
     }
 }
 
+/// Async methods
+impl<'d> Flex<'d> {
+    /// Helper function that waits for a given interrupt trigger
+    async fn wait_for_inner(&mut self, level: crate::pac::gpio0::icr::Irqc) {
+        // First, ensure that we have a waker that is ready for this port+pin
+        let w = PORT_WAIT_MAPS[self.pin.port].wait(self.pin.pin);
+        let mut w = pin!(w);
+        // Wait for the subscription to occur, which requires polling at least once
+        //
+        // This function returns a result, but can only be an Err if:
+        //
+        // * We call `.close()` on a WaitMap, which we never do
+        // * We have a duplicate key, which can't happen because `wait_for_*` methods
+        //   take an &mut ref of their unique port+pin combo
+        //
+        // So we wait for it to complete, but ignore the result.
+        _ = w.as_mut().subscribe().await;
+
+        // Now that our waker is in the map, we can enable the appropriate interrupt
+        //
+        // Clear any existing pending interrupt on this pin
+        self.pin
+            .gpio()
+            .isfr0()
+            .write(|w| unsafe { w.bits(1 << self.pin.pin()) });
+        self.pin.gpio().icr(self.pin.pin()).write(|w| w.isf().isf1());
+
+        // Pin interrupt configuration
+        self.pin
+            .gpio()
+            .icr(self.pin.pin())
+            .modify(|_, w| w.irqc().variant(level));
+
+        // Finally, we can await the matching call to `.wake()` from the interrupt.
+        //
+        // Again, technically, this could return a result, but for the same reasons
+        // as above, this can't be an error in our case, so just wait for it to complete
+        _ = w.await;
+    }
+
+    /// Wait until the pin is high. If it is already high, return immediately.
+    #[inline]
+    pub fn wait_for_high(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc12)
+    }
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    #[inline]
+    pub fn wait_for_low(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc8)
+    }
+
+    /// Wait for the pin to undergo a transition from low to high.
+    #[inline]
+    pub fn wait_for_rising_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc9)
+    }
+
+    /// Wait for the pin to undergo a transition from high to low.
+    #[inline]
+    pub fn wait_for_falling_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc10)
+    }
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    #[inline]
+    pub fn wait_for_any_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc11)
+    }
+}
+
 /// GPIO output driver that owns a `Flex` pin.
 pub struct Output<'d> {
     flex: Flex<'d>,
@@ -691,12 +845,99 @@ impl<'d> Input<'d> {
         self.flex
     }
 
-    // Get the pin level.
+    /// Get the pin level.
     pub fn get_level(&self) -> Level {
         self.flex.get_level()
     }
 }
 
+/// Async methods
+impl<'d> Input<'d> {
+    /// Wait until the pin is high. If it is already high, return immediately.
+    #[inline]
+    pub fn wait_for_high(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_high()
+    }
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    #[inline]
+    pub fn wait_for_low(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_low()
+    }
+
+    /// Wait for the pin to undergo a transition from low to high.
+    #[inline]
+    pub fn wait_for_rising_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_rising_edge()
+    }
+
+    /// Wait for the pin to undergo a transition from high to low.
+    #[inline]
+    pub fn wait_for_falling_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_falling_edge()
+    }
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    #[inline]
+    pub fn wait_for_any_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_any_edge()
+    }
+}
+
+impl embedded_hal_async::digital::Wait for Input<'_> {
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_high().await;
+        Ok(())
+    }
+
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_low().await;
+        Ok(())
+    }
+
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_rising_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_falling_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_any_edge().await;
+        Ok(())
+    }
+}
+
+impl embedded_hal_async::digital::Wait for Flex<'_> {
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_high().await;
+        Ok(())
+    }
+
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_low().await;
+        Ok(())
+    }
+
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_rising_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_falling_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_any_edge().await;
+        Ok(())
+    }
+}
+
 // Both embedded_hal 0.2 and 1.0 must be supported by embassy HALs.
 impl embedded_hal_02::digital::v2::InputPin for Flex<'_> {
     // GPIO operations on this block cannot fail, therefor we set the error type