1 files changed, 11 insertions, 1 deletions

diff --git a/src/uart.rs b/src/uart.rs
index 3209a318d..3705959d3 100644
--- a/src/uart.rs
+++ b/src/uart.rs
@@ -1,6 +1,10 @@
 //! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering.
 //! WARNING: This is a narrow implementation only for debug console (115200 8N1).
 
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
+
 use core::cell::RefCell;
 
 use cortex_m::interrupt::Mutex;
@@ -118,7 +122,7 @@ impl<I: Instance> Uart<I> {
                 StopBits::Two => w.sbns().two(),
             };
             // OSR field encodes (osr-1); use raw bits to avoid a long match on all variants
-            let raw_osr = osr.saturating_sub(1) as u8;
+            let raw_osr = osr.saturating_sub(1);
             unsafe { w.osr().bits(raw_osr).sbr().bits(sbr) }
         });
         // 3) CTRL baseline and parity
@@ -195,6 +199,12 @@ pub struct RingBuffer {
     count: usize,
 }
 
+impl Default for RingBuffer {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl RingBuffer {
     pub const fn new() -> Self {
         Self {