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-rw-r--r--src/bus.rs104
-rw-r--r--src/lib.rs7
2 files changed, 18 insertions, 93 deletions
diff --git a/src/bus.rs b/src/bus.rs
index e4f9a69bb..90990f35a 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -2,22 +2,22 @@ use core::slice;
2 2
3use embassy_time::{Duration, Timer}; 3use embassy_time::{Duration, Timer};
4use embedded_hal_1::digital::OutputPin; 4use embedded_hal_1::digital::OutputPin;
5use embedded_hal_1::spi::ErrorType;
6use embedded_hal_async::spi::{transaction, SpiDevice};
7use futures::FutureExt; 5use futures::FutureExt;
8 6
9use crate::consts::*; 7use crate::consts::*;
10 8
11/// Custom Spi Trait that _only_ supports the bus operation of the cyw43 9/// Custom Spi Trait that _only_ supports the bus operation of the cyw43
12pub trait SpiBusCyw43<Word: 'static + Copy>: ErrorType { 10/// Implementors are expected to hold the CS pin low during an operation.
11pub trait SpiBusCyw43 {
13 /// Issues a write command on the bus 12 /// Issues a write command on the bus
14 /// Frist 32 bits of `word` are expected to be a cmd word 13 /// First 32 bits of `word` are expected to be a cmd word
15 async fn cmd_write<'a>(&'a mut self, write: &'a [Word]) -> Result<(), Self::Error>; 14 async fn cmd_write(&mut self, write: &[u32]);
16 15
17 /// Issues a read command on the bus 16 /// Issues a read command on the bus
18 /// `write` is expected to be a 32 bit cmd word 17 /// `write` is expected to be a 32 bit cmd word
19 /// `read` will contain the response of the device 18 /// `read` will contain the response of the device
20 async fn cmd_read<'a>(&'a mut self, write: &'a [Word], read: &'a mut [Word]) -> Result<(), Self::Error>; 19 ///
20 async fn cmd_read(&mut self, write: u32, read: &mut [u32]);
21} 21}
22 22
23pub(crate) struct Bus<PWR, SPI> { 23pub(crate) struct Bus<PWR, SPI> {
@@ -29,8 +29,7 @@ pub(crate) struct Bus<PWR, SPI> {
29impl<PWR, SPI> Bus<PWR, SPI> 29impl<PWR, SPI> Bus<PWR, SPI>
30where 30where
31 PWR: OutputPin, 31 PWR: OutputPin,
32 SPI: SpiDevice, 32 SPI: SpiBusCyw43,
33 SPI::Bus: SpiBusCyw43<u32>,
34{ 33{
35 pub(crate) fn new(pwr: PWR, spi: SPI) -> Self { 34 pub(crate) fn new(pwr: PWR, spi: SPI) -> Self {
36 Self { 35 Self {
@@ -87,14 +86,8 @@ where
87 pub async fn wlan_read(&mut self, buf: &mut [u32], len_in_u8: u32) { 86 pub async fn wlan_read(&mut self, buf: &mut [u32], len_in_u8: u32) {
88 let cmd = cmd_word(READ, INC_ADDR, FUNC_WLAN, 0, len_in_u8); 87 let cmd = cmd_word(READ, INC_ADDR, FUNC_WLAN, 0, len_in_u8);
89 let len_in_u32 = (len_in_u8 as usize + 3) / 4; 88 let len_in_u32 = (len_in_u8 as usize + 3) / 4;
90 transaction!(&mut self.spi, |bus| async { 89
91 // bus.write(&[cmd]).await?; 90 self.spi.cmd_read(cmd, &mut buf[..len_in_u32]).await;
92 // bus.read(&mut buf[..len_in_u32]).await?;
93 bus.cmd_read(slice::from_ref(&cmd), &mut buf[..len_in_u32]).await?;
94 Ok(())
95 })
96 .await
97 .unwrap();
98 } 91 }
99 92
100 pub async fn wlan_write(&mut self, buf: &[u32]) { 93 pub async fn wlan_write(&mut self, buf: &[u32]) {
@@ -104,15 +97,7 @@ where
104 cmd_buf[0] = cmd; 97 cmd_buf[0] = cmd;
105 cmd_buf[1..][..buf.len()].copy_from_slice(buf); 98 cmd_buf[1..][..buf.len()].copy_from_slice(buf);
106 99
107 transaction!(&mut self.spi, |bus| async { 100 self.spi.cmd_write(&cmd_buf).await;
108 // bus.write(&[cmd]).await?;
109 // bus.write(buf).await?;
110
111 bus.cmd_write(&cmd_buf).await?;
112 Ok(())
113 })
114 .await
115 .unwrap();
116 } 101 }
117 102
118 #[allow(unused)] 103 #[allow(unused)]
@@ -136,22 +121,7 @@ where
136 121
137 let cmd = cmd_word(READ, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32); 122 let cmd = cmd_word(READ, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32);
138 123
139 transaction!(&mut self.spi, |bus| async { 124 self.spi.cmd_read(cmd, &mut buf[..(len + 3) / 4 + 1]).await;
140 // bus.write(&[cmd]).await?;
141
142 // // 4-byte response delay.
143 // let mut junk = [0; 1];
144 // bus.read(&mut junk).await?;
145
146 // // Read data
147 // bus.read(&mut buf[..(len + 3) / 4]).await?;
148
149 bus.cmd_read(slice::from_ref(&cmd), &mut buf[..(len + 3) / 4 + 1])
150 .await?;
151 Ok(())
152 })
153 .await
154 .unwrap();
155 125
156 data[..len].copy_from_slice(&slice8_mut(&mut buf[1..])[..len]); 126 data[..len].copy_from_slice(&slice8_mut(&mut buf[1..])[..len]);
157 127
@@ -183,16 +153,7 @@ where
183 let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32); 153 let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32);
184 buf[0] = cmd; 154 buf[0] = cmd;
185 155
186 transaction!(&mut self.spi, |bus| async { 156 self.spi.cmd_write(&buf[..(len + 3) / 4 + 1]).await;
187 // bus.write(&[cmd]).await?;
188 // bus.write(&buf[..(len + 3) / 4]).await?;
189
190 bus.cmd_write(&buf[..(len + 3) / 4 + 1]).await?;
191
192 Ok(())
193 })
194 .await
195 .unwrap();
196 157
197 // Advance ptr. 158 // Advance ptr.
198 addr += len as u32; 159 addr += len as u32;
@@ -307,19 +268,7 @@ where
307 let mut buf = [0; 2]; 268 let mut buf = [0; 2];
308 let len = if func == FUNC_BACKPLANE { 2 } else { 1 }; 269 let len = if func == FUNC_BACKPLANE { 2 } else { 1 };
309 270
310 transaction!(&mut self.spi, |bus| async { 271 self.spi.cmd_read(cmd, &mut buf[..len]).await;
311 // bus.write(&[cmd]).await?;
312 // if func == FUNC_BACKPLANE {
313 // // 4-byte response delay.
314 // bus.read(&mut buf).await?;
315 // }
316 // bus.read(&mut buf).await?;
317
318 bus.cmd_read(slice::from_ref(&cmd), &mut buf[..len]).await?;
319 Ok(())
320 })
321 .await
322 .unwrap();
323 272
324 if func == FUNC_BACKPLANE { 273 if func == FUNC_BACKPLANE {
325 buf[1] 274 buf[1]
@@ -331,13 +280,7 @@ where
331 async fn writen(&mut self, func: u32, addr: u32, val: u32, len: u32) { 280 async fn writen(&mut self, func: u32, addr: u32, val: u32, len: u32) {
332 let cmd = cmd_word(WRITE, INC_ADDR, func, addr, len); 281 let cmd = cmd_word(WRITE, INC_ADDR, func, addr, len);
333 282
334 transaction!(&mut self.spi, |bus| async { 283 self.spi.cmd_write(&[cmd, val]).await;
335 // bus.write(&[cmd, val]).await?;
336 bus.cmd_write(&[cmd, val]).await?;
337 Ok(())
338 })
339 .await
340 .unwrap();
341 } 284 }
342 285
343 async fn read32_swapped(&mut self, addr: u32) -> u32 { 286 async fn read32_swapped(&mut self, addr: u32) -> u32 {
@@ -345,15 +288,7 @@ where
345 let cmd = swap16(cmd); 288 let cmd = swap16(cmd);
346 let mut buf = [0; 1]; 289 let mut buf = [0; 1];
347 290
348 transaction!(&mut self.spi, |bus| async { 291 self.spi.cmd_read(cmd, &mut buf).await;
349 // bus.write(&[swap16(cmd)]).await?;
350 // bus.read(&mut buf).await?;
351
352 bus.cmd_read(slice::from_ref(&cmd), &mut buf).await?;
353 Ok(())
354 })
355 .await
356 .unwrap();
357 292
358 swap16(buf[0]) 293 swap16(buf[0])
359 } 294 }
@@ -362,14 +297,7 @@ where
362 let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BUS, addr, 4); 297 let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BUS, addr, 4);
363 let buf = [swap16(cmd), swap16(val)]; 298 let buf = [swap16(cmd), swap16(val)];
364 299
365 transaction!(&mut self.spi, |bus| async { 300 self.spi.cmd_write(&buf).await;
366 // bus.write(&[swap16(cmd), swap16(val)]).await?;
367
368 bus.cmd_write(&buf).await?;
369 Ok(())
370 })
371 .await
372 .unwrap();
373 } 301 }
374} 302}
375 303
diff --git a/src/lib.rs b/src/lib.rs
index bcc3c59bd..f0a7aaa0f 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -22,7 +22,6 @@ use embassy_futures::yield_now;
22use embassy_net_driver_channel as ch; 22use embassy_net_driver_channel as ch;
23use embassy_time::{block_for, Duration, Timer}; 23use embassy_time::{block_for, Duration, Timer};
24use embedded_hal_1::digital::OutputPin; 24use embedded_hal_1::digital::OutputPin;
25use embedded_hal_async::spi::SpiDevice;
26 25
27use crate::bus::Bus; 26use crate::bus::Bus;
28pub use crate::bus::SpiBusCyw43; 27pub use crate::bus::SpiBusCyw43;
@@ -513,8 +512,7 @@ pub async fn new<'a, PWR, SPI>(
513) -> (NetDriver<'a>, Control<'a>, Runner<'a, PWR, SPI>) 512) -> (NetDriver<'a>, Control<'a>, Runner<'a, PWR, SPI>)
514where 513where
515 PWR: OutputPin, 514 PWR: OutputPin,
516 SPI: SpiDevice, 515 SPI: SpiBusCyw43,
517 SPI::Bus: SpiBusCyw43<u32>,
518{ 516{
519 let (ch_runner, device) = ch::new(&mut state.ch, [0; 6]); 517 let (ch_runner, device) = ch::new(&mut state.ch, [0; 6]);
520 let state_ch = ch_runner.state_runner(); 518 let state_ch = ch_runner.state_runner();
@@ -552,8 +550,7 @@ where
552impl<'a, PWR, SPI> Runner<'a, PWR, SPI> 550impl<'a, PWR, SPI> Runner<'a, PWR, SPI>
553where 551where
554 PWR: OutputPin, 552 PWR: OutputPin,
555 SPI: SpiDevice, 553 SPI: SpiBusCyw43,
556 SPI::Bus: SpiBusCyw43<u32>,
557{ 554{
558 async fn init(&mut self, firmware: &[u8]) { 555 async fn init(&mut self, firmware: &[u8]) {
559 self.bus.init().await; 556 self.bus.init().await;