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-rw-r--r--tests/stm32/src/bin/afio.rs1156
-rw-r--r--tests/stm32/src/bin/can.rs1
-rw-r--r--tests/stm32/src/bin/can_common.rs109
-rw-r--r--tests/stm32/src/bin/cryp.rs2
-rw-r--r--tests/stm32/src/bin/eeprom.rs30
-rw-r--r--tests/stm32/src/bin/eth.rs3
-rw-r--r--tests/stm32/src/bin/fdcan.rs1
-rw-r--r--tests/stm32/src/bin/hash.rs48
-rw-r--r--tests/stm32/src/bin/sdmmc.rs4
-rw-r--r--tests/stm32/src/bin/stop.rs6
-rw-r--r--tests/stm32/src/bin/usart_rx_ringbuffered.rs4
-rw-r--r--tests/stm32/src/bin/wpan_ble.rs2
-rw-r--r--tests/stm32/src/bin/wpan_mac.rs2
13 files changed, 1244 insertions, 124 deletions
diff --git a/tests/stm32/src/bin/afio.rs b/tests/stm32/src/bin/afio.rs
new file mode 100644
index 000000000..cc44dc59c
--- /dev/null
+++ b/tests/stm32/src/bin/afio.rs
@@ -0,0 +1,1156 @@
1// required-features: afio
2#![no_std]
3#![no_main]
4#[path = "../common.rs"]
5mod common;
6
7use common::*;
8use embassy_executor::Spawner;
9use embassy_stm32::gpio::{AfioRemap, OutputType, Pull};
10use embassy_stm32::pac::AFIO;
11use embassy_stm32::time::khz;
12use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, ComplementaryPwmPin};
13use embassy_stm32::timer::input_capture::{CapturePin, InputCapture};
14use embassy_stm32::timer::pwm_input::PwmInput;
15use embassy_stm32::timer::qei::{Qei, QeiPin};
16use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
17use embassy_stm32::usart::{Uart, UartRx, UartTx};
18use embassy_stm32::{bind_interrupts, Peripherals};
19
20#[cfg(not(feature = "afio-connectivity-line"))]
21bind_interrupts!(struct Irqs {
22 USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;
23 TIM1_CC => embassy_stm32::timer::CaptureCompareInterruptHandler<embassy_stm32::peripherals::TIM1>;
24});
25
26#[cfg(feature = "afio-connectivity-line")]
27bind_interrupts!(struct Irqs {
28 CAN1_RX0 => embassy_stm32::can::Rx0InterruptHandler<embassy_stm32::peripherals::CAN1>;
29 CAN1_RX1 => embassy_stm32::can::Rx1InterruptHandler<embassy_stm32::peripherals::CAN1>;
30 CAN1_SCE => embassy_stm32::can::SceInterruptHandler<embassy_stm32::peripherals::CAN1>;
31 CAN1_TX => embassy_stm32::can::TxInterruptHandler<embassy_stm32::peripherals::CAN1>;
32
33 CAN2_RX0 => embassy_stm32::can::Rx0InterruptHandler<embassy_stm32::peripherals::CAN2>;
34 CAN2_RX1 => embassy_stm32::can::Rx1InterruptHandler<embassy_stm32::peripherals::CAN2>;
35 CAN2_SCE => embassy_stm32::can::SceInterruptHandler<embassy_stm32::peripherals::CAN2>;
36 CAN2_TX => embassy_stm32::can::TxInterruptHandler<embassy_stm32::peripherals::CAN2>;
37
38 ETH => embassy_stm32::eth::InterruptHandler;
39 USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;
40 TIM1_CC => embassy_stm32::timer::CaptureCompareInterruptHandler<embassy_stm32::peripherals::TIM1>;
41});
42
43#[embassy_executor::main]
44async fn main(_spawner: Spawner) {
45 let mut p = init();
46 info!("Hello World!");
47
48 // USART3
49 {
50 // no remap RX/TX/RTS/CTS
51 afio_registers_set_remap();
52 Uart::new_blocking_with_rtscts(
53 p.USART3.reborrow(),
54 p.PB11.reborrow(),
55 p.PB10.reborrow(),
56 p.PB14.reborrow(),
57 p.PB13.reborrow(),
58 Default::default(),
59 )
60 .unwrap();
61 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
62 }
63 {
64 // no remap RX/TX
65 afio_registers_set_remap();
66 Uart::new_blocking(
67 p.USART3.reborrow(),
68 p.PB11.reborrow(),
69 p.PB10.reborrow(),
70 Default::default(),
71 )
72 .unwrap();
73 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
74 }
75 {
76 // no remap TX
77 afio_registers_set_remap();
78 Uart::new_blocking_half_duplex(
79 p.USART3.reborrow(),
80 p.PB10.reborrow(),
81 Default::default(),
82 embassy_stm32::usart::HalfDuplexReadback::NoReadback,
83 )
84 .unwrap();
85 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
86 }
87 {
88 // no remap TX async
89 afio_registers_set_remap();
90 UartTx::new(
91 p.USART3.reborrow(),
92 p.PB10.reborrow(),
93 p.DMA1_CH2.reborrow(),
94 Default::default(),
95 )
96 .unwrap();
97 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
98 }
99 {
100 // no remap TX/CTS async
101 afio_registers_set_remap();
102 UartTx::new_with_cts(
103 p.USART3.reborrow(),
104 p.PB10.reborrow(),
105 p.PB13.reborrow(),
106 p.DMA1_CH2.reborrow(),
107 Default::default(),
108 )
109 .unwrap();
110 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
111 }
112 {
113 // no remap RX async
114 afio_registers_set_remap();
115 UartRx::new(
116 p.USART3.reborrow(),
117 Irqs,
118 p.PB11.reborrow(),
119 p.DMA1_CH3.reborrow(),
120 Default::default(),
121 )
122 .unwrap();
123 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
124 }
125 {
126 // no remap RX async
127 afio_registers_set_remap();
128 UartRx::new_with_rts(
129 p.USART3.reborrow(),
130 Irqs,
131 p.PB11.reborrow(),
132 p.PB14.reborrow(),
133 p.DMA1_CH3.reborrow(),
134 Default::default(),
135 )
136 .unwrap();
137 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
138 }
139 {
140 // no remap RX/TX async
141 afio_registers_set_remap();
142 Uart::new(
143 p.USART3.reborrow(),
144 p.PB11.reborrow(),
145 p.PB10.reborrow(),
146 Irqs,
147 p.DMA1_CH2.reborrow(),
148 p.DMA1_CH3.reborrow(),
149 Default::default(),
150 )
151 .unwrap();
152 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
153 }
154 {
155 // no remap RX/TX/RTS/CTS async
156 afio_registers_set_remap();
157 Uart::new_with_rtscts(
158 p.USART3.reborrow(),
159 p.PB11.reborrow(),
160 p.PB10.reborrow(),
161 Irqs,
162 p.PB14.reborrow(),
163 p.PB13.reborrow(),
164 p.DMA1_CH2.reborrow(),
165 p.DMA1_CH3.reborrow(),
166 Default::default(),
167 )
168 .unwrap();
169 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
170 }
171
172 // TIM1
173 {
174 // no remap
175 afio_registers_set_remap();
176 SimplePwm::new::<AfioRemap<0>>(
177 p.TIM1.reborrow(),
178 Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
179 Some(PwmPin::new(p.PA9.reborrow(), OutputType::PushPull)),
180 Some(PwmPin::new(p.PA10.reborrow(), OutputType::PushPull)),
181 Some(PwmPin::new(p.PA11.reborrow(), OutputType::PushPull)),
182 khz(10),
183 Default::default(),
184 );
185 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 0);
186 }
187 {
188 // no remap
189 afio_registers_set_remap();
190 SimplePwm::new::<AfioRemap<0>>(
191 p.TIM1.reborrow(),
192 Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
193 None,
194 None,
195 None,
196 khz(10),
197 Default::default(),
198 );
199 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 0);
200 }
201 {
202 // partial remap
203 reset_afio_registers();
204 ComplementaryPwm::new::<AfioRemap<1>>(
205 p.TIM1.reborrow(),
206 Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
207 None,
208 None,
209 None,
210 None,
211 None,
212 None,
213 None,
214 khz(10),
215 Default::default(),
216 );
217 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
218 }
219 {
220 // partial remap
221 reset_afio_registers();
222 ComplementaryPwm::new::<AfioRemap<1>>(
223 p.TIM1.reborrow(),
224 Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
225 Some(ComplementaryPwmPin::new(p.PA7.reborrow(), OutputType::PushPull)),
226 Some(PwmPin::new(p.PA9.reborrow(), OutputType::PushPull)),
227 Some(ComplementaryPwmPin::new(p.PB0.reborrow(), OutputType::PushPull)),
228 Some(PwmPin::new(p.PA10.reborrow(), OutputType::PushPull)),
229 None, // pin does not exist on medium-density devices
230 Some(PwmPin::new(p.PA11.reborrow(), OutputType::PushPull)),
231 None, // signal does not exist
232 khz(10),
233 Default::default(),
234 );
235 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
236 }
237 {
238 // partial remap
239 reset_afio_registers();
240 InputCapture::new::<AfioRemap<1>>(
241 p.TIM1.reborrow(),
242 Some(CapturePin::new(p.PA8.reborrow(), Pull::Down)),
243 None,
244 None,
245 None,
246 Irqs,
247 khz(10),
248 Default::default(),
249 );
250 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
251 }
252 {
253 // partial remap
254 reset_afio_registers();
255 PwmInput::new_ch1::<AfioRemap<1>>(p.TIM1.reborrow(), p.PA8.reborrow(), Pull::Down, khz(10));
256 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
257 }
258 {
259 // partial remap
260 reset_afio_registers();
261 Qei::new::<AfioRemap<1>>(
262 p.TIM1.reborrow(),
263 QeiPin::new(p.PA8.reborrow()),
264 QeiPin::new(p.PA9.reborrow()),
265 );
266 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
267 }
268
269 // TIM2
270 {
271 // no remap
272 afio_registers_set_remap();
273 SimplePwm::new::<AfioRemap<0>>(
274 p.TIM2.reborrow(),
275 Some(PwmPin::new(p.PA0.reborrow(), OutputType::PushPull)),
276 Some(PwmPin::new(p.PA1.reborrow(), OutputType::PushPull)),
277 Some(PwmPin::new(p.PA2.reborrow(), OutputType::PushPull)),
278 Some(PwmPin::new(p.PA3.reborrow(), OutputType::PushPull)),
279 khz(10),
280 Default::default(),
281 );
282 defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 0);
283 }
284 {
285 // partial remap 1
286 reset_afio_registers();
287 SimplePwm::new::<AfioRemap<1>>(
288 p.TIM2.reborrow(),
289 Some(PwmPin::new(p.PA15.reborrow(), OutputType::PushPull)),
290 Some(PwmPin::new(p.PB3.reborrow(), OutputType::PushPull)),
291 Some(PwmPin::new(p.PA2.reborrow(), OutputType::PushPull)),
292 Some(PwmPin::new(p.PA3.reborrow(), OutputType::PushPull)),
293 khz(10),
294 Default::default(),
295 );
296 defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 1);
297 }
298 {
299 // partial remap 2
300 reset_afio_registers();
301 SimplePwm::new::<AfioRemap<2>>(
302 p.TIM2.reborrow(),
303 Some(PwmPin::new(p.PA0.reborrow(), OutputType::PushPull)),
304 Some(PwmPin::new(p.PA1.reborrow(), OutputType::PushPull)),
305 Some(PwmPin::new(p.PB10.reborrow(), OutputType::PushPull)),
306 Some(PwmPin::new(p.PB11.reborrow(), OutputType::PushPull)),
307 khz(10),
308 Default::default(),
309 );
310 defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 2);
311 }
312 {
313 // full remap
314 reset_afio_registers();
315 SimplePwm::new::<AfioRemap<3>>(
316 p.TIM2.reborrow(),
317 Some(PwmPin::new(p.PA15.reborrow(), OutputType::PushPull)),
318 Some(PwmPin::new(p.PB3.reborrow(), OutputType::PushPull)),
319 Some(PwmPin::new(p.PB10.reborrow(), OutputType::PushPull)),
320 Some(PwmPin::new(p.PB11.reborrow(), OutputType::PushPull)),
321 khz(10),
322 Default::default(),
323 );
324 defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 3);
325 }
326
327 connectivity_line::run(&mut p);
328 value_line::run(&mut p);
329
330 info!("Test OK");
331 cortex_m::asm::bkpt();
332}
333
334#[cfg(feature = "afio-connectivity-line")]
335mod connectivity_line {
336 use embassy_stm32::can::Can;
337 use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
338 use embassy_stm32::i2s::I2S;
339 use embassy_stm32::spi::Spi;
340
341 use super::*;
342
343 pub fn run(p: &mut Peripherals) {
344 // USART3
345 {
346 // partial remap RX/TX/RTS/CTS
347 reset_afio_registers();
348 Uart::new_blocking_with_rtscts(
349 p.USART3.reborrow(),
350 p.PC11.reborrow(),
351 p.PC10.reborrow(),
352 p.PB14.reborrow(),
353 p.PB13.reborrow(),
354 Default::default(),
355 )
356 .unwrap();
357 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
358 }
359 {
360 // partial remap RX/TX
361 reset_afio_registers();
362 Uart::new_blocking(
363 p.USART3.reborrow(),
364 p.PC11.reborrow(),
365 p.PC10.reborrow(),
366 Default::default(),
367 )
368 .unwrap();
369 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
370 }
371 {
372 // partial remap TX
373 reset_afio_registers();
374 Uart::new_blocking_half_duplex(
375 p.USART3.reborrow(),
376 p.PC10.reborrow(),
377 Default::default(),
378 embassy_stm32::usart::HalfDuplexReadback::NoReadback,
379 )
380 .unwrap();
381 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
382 }
383 {
384 // partial remap TX async
385 reset_afio_registers();
386 UartTx::new(
387 p.USART3.reborrow(),
388 p.PC10.reborrow(),
389 p.DMA1_CH2.reborrow(),
390 Default::default(),
391 )
392 .unwrap();
393 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
394 }
395 {
396 // partial remap TX/CTS async
397 reset_afio_registers();
398 UartTx::new_with_cts(
399 p.USART3.reborrow(),
400 p.PC10.reborrow(),
401 p.PB13.reborrow(),
402 p.DMA1_CH2.reborrow(),
403 Default::default(),
404 )
405 .unwrap();
406 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
407 }
408 {
409 // partial remap RX async
410 reset_afio_registers();
411 UartRx::new(
412 p.USART3.reborrow(),
413 Irqs,
414 p.PC11.reborrow(),
415 p.DMA1_CH3.reborrow(),
416 Default::default(),
417 )
418 .unwrap();
419 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
420 }
421 {
422 // partial remap RX async
423 reset_afio_registers();
424 UartRx::new_with_rts(
425 p.USART3.reborrow(),
426 Irqs,
427 p.PC11.reborrow(),
428 p.PB14.reborrow(),
429 p.DMA1_CH3.reborrow(),
430 Default::default(),
431 )
432 .unwrap();
433 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
434 }
435 {
436 // partial remap RX/TX async
437 reset_afio_registers();
438 Uart::new(
439 p.USART3.reborrow(),
440 p.PC11.reborrow(),
441 p.PC10.reborrow(),
442 Irqs,
443 p.DMA1_CH2.reborrow(),
444 p.DMA1_CH3.reborrow(),
445 Default::default(),
446 )
447 .unwrap();
448 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
449 }
450 {
451 // partial remap RX/TX/RTS/CTS async
452 reset_afio_registers();
453 Uart::new_with_rtscts(
454 p.USART3.reborrow(),
455 p.PC11.reborrow(),
456 p.PC10.reborrow(),
457 Irqs,
458 p.PB14.reborrow(),
459 p.PB13.reborrow(),
460 p.DMA1_CH2.reborrow(),
461 p.DMA1_CH3.reborrow(),
462 Default::default(),
463 )
464 .unwrap();
465 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
466 }
467 {
468 // full remap RX/TX/RTS/CTS
469 reset_afio_registers();
470 Uart::new_blocking_with_rtscts(
471 p.USART3.reborrow(),
472 p.PD9.reborrow(),
473 p.PD8.reborrow(),
474 p.PD12.reborrow(),
475 p.PD11.reborrow(),
476 Default::default(),
477 )
478 .unwrap();
479 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
480 }
481 {
482 // full remap RX/TX
483 reset_afio_registers();
484 Uart::new_blocking(
485 p.USART3.reborrow(),
486 p.PD9.reborrow(),
487 p.PD8.reborrow(),
488 Default::default(),
489 )
490 .unwrap();
491 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
492 }
493 {
494 // full remap TX
495 reset_afio_registers();
496 Uart::new_blocking_half_duplex(
497 p.USART3.reborrow(),
498 p.PD8.reborrow(),
499 Default::default(),
500 embassy_stm32::usart::HalfDuplexReadback::NoReadback,
501 )
502 .unwrap();
503 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
504 }
505 {
506 // full remap TX async
507 reset_afio_registers();
508 UartTx::new(
509 p.USART3.reborrow(),
510 p.PD8.reborrow(),
511 p.DMA1_CH2.reborrow(),
512 Default::default(),
513 )
514 .unwrap();
515 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
516 }
517 {
518 // full remap TX/CTS async
519 reset_afio_registers();
520 UartTx::new_with_cts(
521 p.USART3.reborrow(),
522 p.PD8.reborrow(),
523 p.PD11.reborrow(),
524 p.DMA1_CH2.reborrow(),
525 Default::default(),
526 )
527 .unwrap();
528 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
529 }
530 {
531 // full remap RX async
532 reset_afio_registers();
533 UartRx::new(
534 p.USART3.reborrow(),
535 Irqs,
536 p.PD9.reborrow(),
537 p.DMA1_CH3.reborrow(),
538 Default::default(),
539 )
540 .unwrap();
541 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
542 }
543 {
544 // full remap RX async
545 reset_afio_registers();
546 UartRx::new_with_rts(
547 p.USART3.reborrow(),
548 Irqs,
549 p.PD9.reborrow(),
550 p.PD12.reborrow(),
551 p.DMA1_CH3.reborrow(),
552 Default::default(),
553 )
554 .unwrap();
555 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
556 }
557 {
558 // full remap RX/TX async
559 reset_afio_registers();
560 Uart::new(
561 p.USART3.reborrow(),
562 p.PD9.reborrow(),
563 p.PD8.reborrow(),
564 Irqs,
565 p.DMA1_CH2.reborrow(),
566 p.DMA1_CH3.reborrow(),
567 Default::default(),
568 )
569 .unwrap();
570 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
571 }
572 {
573 // full remap RX/TX/RTS/CTS async
574 reset_afio_registers();
575 Uart::new_with_rtscts(
576 p.USART3.reborrow(),
577 p.PD9.reborrow(),
578 p.PD8.reborrow(),
579 Irqs,
580 p.PD12.reborrow(),
581 p.PD11.reborrow(),
582 p.DMA1_CH2.reborrow(),
583 p.DMA1_CH3.reborrow(),
584 Default::default(),
585 )
586 .unwrap();
587 defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
588 }
589
590 // SPI3
591 {
592 // no remap SCK/MISO/MOSI
593 afio_registers_set_remap();
594 Spi::new_blocking(
595 p.SPI3.reborrow(),
596 p.PB3.reborrow(),
597 p.PB5.reborrow(),
598 p.PB4.reborrow(),
599 Default::default(),
600 );
601 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
602 }
603 {
604 // no remap SCK/MOSI
605 afio_registers_set_remap();
606 Spi::new_blocking_txonly(
607 p.SPI3.reborrow(),
608 p.PB3.reborrow(),
609 p.PB5.reborrow(),
610 Default::default(),
611 );
612 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
613 }
614 {
615 // no remap MOSI
616 afio_registers_set_remap();
617 Spi::new_blocking_txonly_nosck(p.SPI3.reborrow(), p.PB5.reborrow(), Default::default());
618 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
619 }
620 {
621 // no remap SCK/MISO
622 afio_registers_set_remap();
623 Spi::new_blocking_rxonly(
624 p.SPI3.reborrow(),
625 p.PB3.reborrow(),
626 p.PB4.reborrow(),
627 Default::default(),
628 );
629 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
630 }
631 {
632 // remap SCK/MISO/MOSI
633 reset_afio_registers();
634 Spi::new_blocking(
635 p.SPI3.reborrow(),
636 p.PC10.reborrow(),
637 p.PC12.reborrow(),
638 p.PC11.reborrow(),
639 Default::default(),
640 );
641
642 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
643 }
644 {
645 // remap SCK/MOSI
646 reset_afio_registers();
647 Spi::new_blocking_txonly(
648 p.SPI3.reborrow(),
649 p.PC10.reborrow(),
650 p.PC12.reborrow(),
651 Default::default(),
652 );
653 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
654 }
655 {
656 // remap MOSI
657 reset_afio_registers();
658 Spi::new_blocking_txonly_nosck(p.SPI3.reborrow(), p.PB5.reborrow(), Default::default());
659 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
660 }
661 {
662 // remap SCK/MISO
663 reset_afio_registers();
664 Spi::new_blocking_rxonly(
665 p.SPI3.reborrow(),
666 p.PC10.reborrow(),
667 p.PC11.reborrow(),
668 Default::default(),
669 );
670 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
671 }
672
673 // I2S3
674 {
675 // no remap SD/WS/CK/MCK
676 afio_registers_set_remap();
677 I2S::new_txonly(
678 p.SPI3.reborrow(),
679 p.PB5.reborrow(),
680 p.PA15.reborrow(),
681 p.PB3.reborrow(),
682 p.PC7.reborrow(),
683 p.DMA2_CH2.reborrow(),
684 &mut [0u16; 0],
685 Default::default(),
686 );
687 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
688 }
689 {
690 // no remap SD/WS/CK
691 afio_registers_set_remap();
692 I2S::new_txonly_nomck(
693 p.SPI3.reborrow(),
694 p.PB5.reborrow(),
695 p.PA15.reborrow(),
696 p.PB3.reborrow(),
697 p.DMA2_CH2.reborrow(),
698 &mut [0u16; 0],
699 Default::default(),
700 );
701 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
702 }
703 {
704 // no remap SD/WS/CK/MCK
705 afio_registers_set_remap();
706 I2S::new_rxonly(
707 p.SPI3.reborrow(),
708 p.PB4.reborrow(),
709 p.PA15.reborrow(),
710 p.PB3.reborrow(),
711 p.PC7.reborrow(),
712 p.DMA2_CH1.reborrow(),
713 &mut [0u16; 0],
714 Default::default(),
715 );
716 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
717 }
718 {
719 // remap SD/WS/CK/MCK
720 reset_afio_registers();
721 I2S::new_txonly(
722 p.SPI3.reborrow(),
723 p.PC12.reborrow(),
724 p.PA4.reborrow(),
725 p.PC10.reborrow(),
726 p.PC7.reborrow(),
727 p.DMA2_CH2.reborrow(),
728 &mut [0u16; 0],
729 Default::default(),
730 );
731 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
732 }
733 {
734 // remap SD/WS/CK
735 reset_afio_registers();
736 I2S::new_txonly_nomck(
737 p.SPI3.reborrow(),
738 p.PC12.reborrow(),
739 p.PA4.reborrow(),
740 p.PC10.reborrow(),
741 p.DMA2_CH2.reborrow(),
742 &mut [0u16; 0],
743 Default::default(),
744 );
745 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
746 }
747 {
748 // remap SD/WS/CK/MCK
749 reset_afio_registers();
750 I2S::new_rxonly(
751 p.SPI3.reborrow(),
752 p.PC11.reborrow(),
753 p.PA4.reborrow(),
754 p.PC10.reborrow(),
755 p.PC7.reborrow(),
756 p.DMA2_CH1.reborrow(),
757 &mut [0u16; 0],
758 Default::default(),
759 );
760 defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
761 }
762
763 // CAN2
764 {
765 // no remap
766 afio_registers_set_remap();
767 Can::new(p.CAN2.reborrow(), p.PB12.reborrow(), p.PB13.reborrow(), Irqs);
768 defmt::assert_eq!(AFIO.mapr().read().can2_remap(), false);
769 }
770 {
771 // remap
772 reset_afio_registers();
773 Can::new(p.CAN2.reborrow(), p.PB5.reborrow(), p.PB6.reborrow(), Irqs);
774 defmt::assert_eq!(AFIO.mapr().read().can2_remap(), true);
775 }
776
777 // Ethernet
778 {
779 // no remap RMII
780 afio_registers_set_remap();
781 Ethernet::new(
782 &mut PacketQueue::<1, 1>::new(),
783 p.ETH.reborrow(),
784 Irqs,
785 p.PA1.reborrow(),
786 p.PA2.reborrow(),
787 p.PC1.reborrow(),
788 p.PA7.reborrow(),
789 p.PC4.reborrow(),
790 p.PC5.reborrow(),
791 p.PB12.reborrow(),
792 p.PB13.reborrow(),
793 p.PB11.reborrow(),
794 GenericPhy::new_auto(),
795 Default::default(),
796 );
797 defmt::assert_eq!(AFIO.mapr().read().eth_remap(), false);
798 }
799 {
800 // no remap MII
801 afio_registers_set_remap();
802 Ethernet::new_mii(
803 &mut PacketQueue::<1, 1>::new(),
804 p.ETH.reborrow(),
805 Irqs,
806 p.PA1.reborrow(),
807 p.PC3.reborrow(),
808 p.PA2.reborrow(),
809 p.PC1.reborrow(),
810 p.PA7.reborrow(),
811 p.PC4.reborrow(),
812 p.PC5.reborrow(),
813 p.PB0.reborrow(),
814 p.PB1.reborrow(),
815 p.PB12.reborrow(),
816 p.PB13.reborrow(),
817 p.PC2.reborrow(),
818 p.PB8.reborrow(),
819 p.PB11.reborrow(),
820 GenericPhy::new_auto(),
821 Default::default(),
822 );
823 defmt::assert_eq!(AFIO.mapr().read().eth_remap(), false);
824 }
825 {
826 // remap RMII
827 reset_afio_registers();
828 Ethernet::new(
829 &mut PacketQueue::<1, 1>::new(),
830 p.ETH.reborrow(),
831 Irqs,
832 p.PA1.reborrow(),
833 p.PA2.reborrow(),
834 p.PC1.reborrow(),
835 p.PD8.reborrow(),
836 p.PD9.reborrow(),
837 p.PD10.reborrow(),
838 p.PB12.reborrow(),
839 p.PB13.reborrow(),
840 p.PB11.reborrow(),
841 GenericPhy::new_auto(),
842 Default::default(),
843 );
844 defmt::assert_eq!(AFIO.mapr().read().eth_remap(), true);
845 }
846 {
847 // remap MII
848 reset_afio_registers();
849 Ethernet::new_mii(
850 &mut PacketQueue::<1, 1>::new(),
851 p.ETH.reborrow(),
852 Irqs,
853 p.PA1.reborrow(),
854 p.PC3.reborrow(),
855 p.PA2.reborrow(),
856 p.PC1.reborrow(),
857 p.PD8.reborrow(),
858 p.PD9.reborrow(),
859 p.PD10.reborrow(),
860 p.PD11.reborrow(),
861 p.PD12.reborrow(),
862 p.PB12.reborrow(),
863 p.PB13.reborrow(),
864 p.PC2.reborrow(),
865 p.PB8.reborrow(),
866 p.PB11.reborrow(),
867 GenericPhy::new_auto(),
868 Default::default(),
869 );
870 defmt::assert_eq!(AFIO.mapr().read().eth_remap(), true);
871 }
872
873 // CAN1
874 {
875 // no remap
876 afio_registers_set_remap();
877 Can::new(p.CAN1.reborrow(), p.PA11.reborrow(), p.PA12.reborrow(), Irqs);
878 defmt::assert_eq!(AFIO.mapr().read().can1_remap(), 0);
879 }
880 {
881 // partial remap
882 reset_afio_registers();
883 Can::new(p.CAN1.reborrow(), p.PB8.reborrow(), p.PB9.reborrow(), Irqs);
884 defmt::assert_eq!(AFIO.mapr().read().can1_remap(), 2);
885 }
886 {
887 // full remap
888 reset_afio_registers();
889 Can::new(p.CAN1.reborrow(), p.PD0.reborrow(), p.PD1.reborrow(), Irqs);
890 defmt::assert_eq!(AFIO.mapr().read().can1_remap(), 3);
891 }
892
893 // USART2
894 {
895 // no remap RX/TX/RTS/CTS
896 afio_registers_set_remap();
897 Uart::new_blocking_with_rtscts(
898 p.USART2.reborrow(),
899 p.PA3.reborrow(),
900 p.PA2.reborrow(),
901 p.PA1.reborrow(),
902 p.PA0.reborrow(),
903 Default::default(),
904 )
905 .unwrap();
906 defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
907 }
908 {
909 // no remap RX/TX
910 afio_registers_set_remap();
911 Uart::new_blocking(
912 p.USART2.reborrow(),
913 p.PA3.reborrow(),
914 p.PA2.reborrow(),
915 Default::default(),
916 )
917 .unwrap();
918 defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
919 }
920 {
921 // no remap TX
922 afio_registers_set_remap();
923 Uart::new_blocking_half_duplex(
924 p.USART2.reborrow(),
925 p.PA2.reborrow(),
926 Default::default(),
927 embassy_stm32::usart::HalfDuplexReadback::NoReadback,
928 )
929 .unwrap();
930 defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
931 }
932 {
933 // full remap RX/TX/RTS/CTS
934 reset_afio_registers();
935 Uart::new_blocking_with_rtscts(
936 p.USART2.reborrow(),
937 p.PD6.reborrow(),
938 p.PD5.reborrow(),
939 p.PD4.reborrow(),
940 p.PD3.reborrow(),
941 Default::default(),
942 )
943 .unwrap();
944 defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
945 }
946 {
947 // full remap RX/TX
948 reset_afio_registers();
949 Uart::new_blocking(
950 p.USART2.reborrow(),
951 p.PD6.reborrow(),
952 p.PD5.reborrow(),
953 Default::default(),
954 )
955 .unwrap();
956 defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
957 }
958 {
959 // full remap TX
960 reset_afio_registers();
961 Uart::new_blocking_half_duplex(
962 p.USART2.reborrow(),
963 p.PD5.reborrow(),
964 Default::default(),
965 embassy_stm32::usart::HalfDuplexReadback::NoReadback,
966 )
967 .unwrap();
968 defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), true);
969 }
970
971 // USART1
972 {
973 // no remap RX/TX/RTS/CTS
974 afio_registers_set_remap();
975 Uart::new_blocking_with_rtscts(
976 p.USART1.reborrow(),
977 p.PA10.reborrow(),
978 p.PA9.reborrow(),
979 p.PA12.reborrow(),
980 p.PA11.reborrow(),
981 Default::default(),
982 )
983 .unwrap();
984 defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), false);
985 }
986 {
987 // no remap RX/TX
988 afio_registers_set_remap();
989 Uart::new_blocking(
990 p.USART1.reborrow(),
991 p.PA10.reborrow(),
992 p.PA9.reborrow(),
993 Default::default(),
994 )
995 .unwrap();
996 defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), false);
997 }
998 {
999 // no remap TX
1000 afio_registers_set_remap();
1001 Uart::new_blocking_half_duplex(
1002 p.USART1.reborrow(),
1003 p.PA9.reborrow(),
1004 Default::default(),
1005 embassy_stm32::usart::HalfDuplexReadback::NoReadback,
1006 )
1007 .unwrap();
1008 defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), false);
1009 }
1010 {
1011 // remap RX/TX/RTS/CTS
1012 reset_afio_registers();
1013 Uart::new_blocking_with_rtscts(
1014 p.USART1.reborrow(),
1015 p.PB7.reborrow(),
1016 p.PB6.reborrow(),
1017 p.PA12.reborrow(),
1018 p.PA11.reborrow(),
1019 Default::default(),
1020 )
1021 .unwrap();
1022 defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), true);
1023 }
1024 {
1025 // remap RX/TX
1026 reset_afio_registers();
1027 Uart::new_blocking(
1028 p.USART1.reborrow(),
1029 p.PB7.reborrow(),
1030 p.PB6.reborrow(),
1031 Default::default(),
1032 )
1033 .unwrap();
1034 defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), true);
1035 }
1036 {
1037 // remap TX
1038 reset_afio_registers();
1039 Uart::new_blocking_half_duplex(
1040 p.USART1.reborrow(),
1041 p.PB6.reborrow(),
1042 Default::default(),
1043 embassy_stm32::usart::HalfDuplexReadback::NoReadback,
1044 )
1045 .unwrap();
1046 defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), true);
1047 }
1048
1049 // TIM1
1050 {
1051 // full remap
1052 reset_afio_registers();
1053 SimplePwm::new(
1054 p.TIM1.reborrow(),
1055 Some(PwmPin::new(p.PE9.reborrow(), OutputType::PushPull)),
1056 Some(PwmPin::new(p.PE11.reborrow(), OutputType::PushPull)),
1057 None,
1058 None,
1059 khz(10),
1060 Default::default(),
1061 );
1062 defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 3);
1063 }
1064 }
1065}
1066
1067#[cfg(feature = "afio-value-line")]
1068mod value_line {
1069 use super::*;
1070
1071 pub fn run(p: &mut Peripherals) {
1072 // TIM13
1073 {
1074 // no remap
1075 reset_afio_registers();
1076 SimplePwm::new(
1077 p.TIM13.reborrow(),
1078 Some(PwmPin::new(p.PC8.reborrow(), OutputType::PushPull)),
1079 None,
1080 None,
1081 None,
1082 khz(10),
1083 Default::default(),
1084 );
1085 defmt::assert_eq!(AFIO.mapr2().read().tim13_remap(), false);
1086 }
1087 {
1088 // remap
1089 reset_afio_registers();
1090 SimplePwm::new(
1091 p.TIM13.reborrow(),
1092 Some(PwmPin::new(p.PB0.reborrow(), OutputType::PushPull)),
1093 None,
1094 None,
1095 None,
1096 khz(10),
1097 Default::default(),
1098 );
1099 defmt::assert_eq!(AFIO.mapr2().read().tim13_remap(), true);
1100 }
1101 }
1102}
1103
1104#[cfg(not(feature = "afio-connectivity-line"))]
1105mod connectivity_line {
1106 use super::*;
1107
1108 pub fn run(_: &mut Peripherals) {}
1109}
1110
1111#[cfg(not(feature = "afio-value-line"))]
1112mod value_line {
1113 use super::*;
1114
1115 pub fn run(_: &mut Peripherals) {}
1116}
1117
1118fn reset_afio_registers() {
1119 set_afio_registers(false, 0);
1120}
1121
1122fn afio_registers_set_remap() {
1123 set_afio_registers(true, 1);
1124}
1125
1126fn set_afio_registers(bool_val: bool, num_val: u8) {
1127 AFIO.mapr().modify(|w| {
1128 w.set_swj_cfg(embassy_stm32::pac::afio::vals::SwjCfg::NO_OP);
1129 w.set_can1_remap(num_val);
1130 w.set_can2_remap(bool_val);
1131 w.set_eth_remap(bool_val);
1132 w.set_i2c1_remap(bool_val);
1133 w.set_spi1_remap(bool_val);
1134 w.set_spi3_remap(bool_val);
1135 w.set_tim1_remap(num_val);
1136 w.set_tim2_remap(num_val);
1137 w.set_tim3_remap(num_val);
1138 w.set_tim4_remap(bool_val);
1139 w.set_usart1_remap(bool_val);
1140 w.set_usart2_remap(bool_val);
1141 w.set_usart3_remap(num_val);
1142 });
1143
1144 AFIO.mapr2().modify(|w| {
1145 w.set_cec_remap(bool_val);
1146 w.set_tim9_remap(bool_val);
1147 w.set_tim10_remap(bool_val);
1148 w.set_tim11_remap(bool_val);
1149 w.set_tim12_remap(bool_val);
1150 w.set_tim13_remap(bool_val);
1151 w.set_tim14_remap(bool_val);
1152 w.set_tim15_remap(bool_val);
1153 w.set_tim16_remap(bool_val);
1154 w.set_tim17_remap(bool_val);
1155 });
1156}
diff --git a/tests/stm32/src/bin/can.rs b/tests/stm32/src/bin/can.rs
index 778d88a7b..348cd049d 100644
--- a/tests/stm32/src/bin/can.rs
+++ b/tests/stm32/src/bin/can.rs
@@ -15,6 +15,7 @@ use embassy_stm32::peripherals::CAN1;
15use embassy_time::Duration; 15use embassy_time::Duration;
16use {defmt_rtt as _, panic_probe as _}; 16use {defmt_rtt as _, panic_probe as _};
17 17
18#[path = "../can_common.rs"]
18mod can_common; 19mod can_common;
19use can_common::*; 20use can_common::*;
20 21
diff --git a/tests/stm32/src/bin/can_common.rs b/tests/stm32/src/bin/can_common.rs
deleted file mode 100644
index 4e1740ad5..000000000
--- a/tests/stm32/src/bin/can_common.rs
+++ /dev/null
@@ -1,109 +0,0 @@
1use defmt::{assert, *};
2use embassy_stm32::can;
3use embassy_time::{Duration, Instant};
4
5#[derive(Clone, Copy, Debug)]
6pub struct TestOptions {
7 pub max_latency: Duration,
8 pub max_buffered: u8,
9}
10
11pub async fn run_can_tests<'d>(can: &mut can::Can<'d>, options: &TestOptions) {
12 //pub async fn run_can_tests<'d, T: can::Instance>(can: &mut can::Can<'d, T>, options: &TestOptions) {
13 let mut i: u8 = 0;
14 loop {
15 //let tx_frame = can::frame::Frame::new_standard(0x123, &[i, 0x12 as u8, 0x34 as u8, 0x56 as u8, 0x78 as u8, 0x9A as u8, 0xBC as u8 ]).unwrap();
16 let tx_frame = can::frame::Frame::new_standard(0x123, &[i; 1]).unwrap();
17
18 //info!("Transmitting frame...");
19 let tx_ts = Instant::now();
20 can.write(&tx_frame).await;
21
22 let (frame, timestamp) = can.read().await.unwrap().parts();
23 //info!("Frame received!");
24
25 // Check data.
26 assert!(i == frame.data()[0], "{} == {}", i, frame.data()[0]);
27
28 //info!("loopback time {}", timestamp);
29 //info!("loopback frame {=u8}", frame.data()[0]);
30 let latency = timestamp.saturating_duration_since(tx_ts);
31 info!("loopback latency {} us", latency.as_micros());
32
33 // Theoretical minimum latency is 55us, actual is usually ~80us
34 const MIN_LATENCY: Duration = Duration::from_micros(50);
35 // Was failing at 150 but we are not getting a real time stamp. I'm not
36 // sure if there are other delays
37 assert!(
38 MIN_LATENCY <= latency && latency <= options.max_latency,
39 "{} <= {} <= {}",
40 MIN_LATENCY,
41 latency,
42 options.max_latency
43 );
44
45 i += 1;
46 if i > 5 {
47 break;
48 }
49 }
50
51 // Below here, check that we can receive from both FIFO0 and FIFO1
52 // Above we configured FIFO1 for extended ID packets. There are only 3 slots
53 // in each FIFO so make sure we write enough to fill them both up before reading.
54 for i in 0..options.max_buffered {
55 // Try filling up the RX FIFO0 buffers
56 //let tx_frame = if 0 != (i & 0x01) {
57 let tx_frame = if i < options.max_buffered / 2 {
58 info!("Transmitting standard frame {}", i);
59 can::frame::Frame::new_standard(0x123, &[i; 1]).unwrap()
60 } else {
61 info!("Transmitting extended frame {}", i);
62 can::frame::Frame::new_extended(0x1232344, &[i; 1]).unwrap()
63 };
64 can.write(&tx_frame).await;
65 }
66
67 // Try and receive all 6 packets
68 for _i in 0..options.max_buffered {
69 let (frame, _ts) = can.read().await.unwrap().parts();
70 match frame.id() {
71 embedded_can::Id::Extended(_id) => {
72 info!("Extended received! {}", frame.data()[0]);
73 //info!("Extended received! {:x} {} {}", id.as_raw(), frame.data()[0], i);
74 }
75 embedded_can::Id::Standard(_id) => {
76 info!("Standard received! {}", frame.data()[0]);
77 //info!("Standard received! {:x} {} {}", id.as_raw(), frame.data()[0], i);
78 }
79 }
80 }
81}
82
83pub async fn run_split_can_tests<'d>(tx: &mut can::CanTx<'d>, rx: &mut can::CanRx<'d>, options: &TestOptions) {
84 for i in 0..options.max_buffered {
85 // Try filling up the RX FIFO0 buffers
86 //let tx_frame = if 0 != (i & 0x01) {
87 let tx_frame = if i < options.max_buffered / 2 {
88 info!("Transmitting standard frame {}", i);
89 can::frame::Frame::new_standard(0x123, &[i; 1]).unwrap()
90 } else {
91 info!("Transmitting extended frame {}", i);
92 can::frame::Frame::new_extended(0x1232344, &[i; 1]).unwrap()
93 };
94 tx.write(&tx_frame).await;
95 }
96
97 // Try and receive all 6 packets
98 for _i in 0..options.max_buffered {
99 let (frame, _ts) = rx.read().await.unwrap().parts();
100 match frame.id() {
101 embedded_can::Id::Extended(_id) => {
102 info!("Extended received! {}", frame.data()[0]);
103 }
104 embedded_can::Id::Standard(_id) => {
105 info!("Standard received! {}", frame.data()[0]);
106 }
107 }
108 }
109}
diff --git a/tests/stm32/src/bin/cryp.rs b/tests/stm32/src/bin/cryp.rs
index 028775ac8..f54c99cc3 100644
--- a/tests/stm32/src/bin/cryp.rs
+++ b/tests/stm32/src/bin/cryp.rs
@@ -72,7 +72,7 @@ async fn main(_spawner: Spawner) {
72 defmt::assert!(encrypt_tag == payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]); 72 defmt::assert!(encrypt_tag == payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]);
73 73
74 // Decrypt in software using AES-GCM 128-bit 74 // Decrypt in software using AES-GCM 128-bit
75 let _ = cipher.decrypt_in_place(&iv.into(), &aad, &mut payload_vec); 75 cipher.decrypt_in_place(&iv.into(), &aad, &mut payload_vec).unwrap();
76 76
77 info!("Test OK"); 77 info!("Test OK");
78 cortex_m::asm::bkpt(); 78 cortex_m::asm::bkpt();
diff --git a/tests/stm32/src/bin/eeprom.rs b/tests/stm32/src/bin/eeprom.rs
new file mode 100644
index 000000000..61d249fd7
--- /dev/null
+++ b/tests/stm32/src/bin/eeprom.rs
@@ -0,0 +1,30 @@
1#![no_std]
2#![no_main]
3
4// required-features: eeprom
5
6#[path = "../common.rs"]
7mod common;
8
9use common::*;
10use defmt::assert_eq;
11use embassy_executor::Spawner;
12use embassy_stm32::flash::Flash;
13use {defmt_rtt as _, panic_probe as _};
14
15#[embassy_executor::main]
16async fn main(_spawner: Spawner) {
17 // Initialize the board and obtain a Peripherals instance
18 let p: embassy_stm32::Peripherals = init();
19
20 let mut f = Flash::new_blocking(p.FLASH);
21 const ADDR: u32 = 0x0;
22
23 unwrap!(f.eeprom_write_slice(ADDR, &[1, 2, 3, 4, 5, 6, 7, 8]));
24 let mut buf = [0u8; 8];
25 unwrap!(f.eeprom_read_slice(ADDR, &mut buf));
26 assert_eq!(&buf[..], &[1, 2, 3, 4, 5, 6, 7, 8]);
27
28 info!("Test OK");
29 cortex_m::asm::bkpt();
30}
diff --git a/tests/stm32/src/bin/eth.rs b/tests/stm32/src/bin/eth.rs
index a7e76fd8e..a65682a02 100644
--- a/tests/stm32/src/bin/eth.rs
+++ b/tests/stm32/src/bin/eth.rs
@@ -11,7 +11,6 @@ use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
11use embassy_stm32::peripherals::ETH; 11use embassy_stm32::peripherals::ETH;
12use embassy_stm32::rng::Rng; 12use embassy_stm32::rng::Rng;
13use embassy_stm32::{bind_interrupts, eth, peripherals, rng}; 13use embassy_stm32::{bind_interrupts, eth, peripherals, rng};
14use rand_core::RngCore;
15use static_cell::StaticCell; 14use static_cell::StaticCell;
16use {defmt_rtt as _, panic_probe as _}; 15use {defmt_rtt as _, panic_probe as _};
17 16
@@ -102,7 +101,7 @@ async fn main(spawner: Spawner) {
102 let (stack, runner) = embassy_net::new(device, config, RESOURCES.init(StackResources::new()), seed); 101 let (stack, runner) = embassy_net::new(device, config, RESOURCES.init(StackResources::new()), seed);
103 102
104 // Launch network task 103 // Launch network task
105 unwrap!(spawner.spawn(net_task(runner))); 104 spawner.spawn(unwrap!(net_task(runner)));
106 105
107 perf_client::run( 106 perf_client::run(
108 stack, 107 stack,
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
index 83d7eca85..c2a1a7bb8 100644
--- a/tests/stm32/src/bin/fdcan.rs
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -12,6 +12,7 @@ use embassy_stm32::{bind_interrupts, can, Config};
12use embassy_time::Duration; 12use embassy_time::Duration;
13use {defmt_rtt as _, panic_probe as _}; 13use {defmt_rtt as _, panic_probe as _};
14 14
15#[path = "../can_common.rs"]
15mod can_common; 16mod can_common;
16use can_common::*; 17use can_common::*;
17 18
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 52b84a499..bb08d0cf1 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -7,6 +7,7 @@ mod common;
7use common::*; 7use common::*;
8use embassy_executor::Spawner; 8use embassy_executor::Spawner;
9use embassy_stm32::hash::*; 9use embassy_stm32::hash::*;
10use embassy_stm32::mode::Blocking;
10use embassy_stm32::{bind_interrupts, hash, peripherals}; 11use embassy_stm32::{bind_interrupts, hash, peripherals};
11use hmac::{Hmac, Mac}; 12use hmac::{Hmac, Mac};
12use sha2::{Digest, Sha224, Sha256}; 13use sha2::{Digest, Sha224, Sha256};
@@ -32,11 +33,7 @@ bind_interrupts!(struct Irqs {
32 HASH => hash::InterruptHandler<peripherals::HASH>; 33 HASH => hash::InterruptHandler<peripherals::HASH>;
33}); 34});
34 35
35#[embassy_executor::main] 36fn test_interrupt(hw_hasher: &mut Hash<'_, peripherals::HASH, Blocking>) {
36async fn main(_spawner: Spawner) {
37 let p: embassy_stm32::Peripherals = init();
38 let mut hw_hasher = Hash::new_blocking(p.HASH, Irqs);
39
40 let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh"; 37 let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
41 let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr"; 38 let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
42 let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk"; 39 let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
@@ -95,6 +92,47 @@ async fn main(_spawner: Spawner) {
95 info!("Hardware HMAC: {:?}", hw_hmac); 92 info!("Hardware HMAC: {:?}", hw_hmac);
96 info!("Software HMAC: {:?}", sw_hmac[..]); 93 info!("Software HMAC: {:?}", sw_hmac[..]);
97 defmt::assert!(hw_hmac == sw_hmac[..]); 94 defmt::assert!(hw_hmac == sw_hmac[..]);
95}
96
97// This uses sha512, so only supported on hash_v3 and up
98#[cfg(feature = "hash-v34")]
99fn test_sizes(hw_hasher: &mut Hash<'_, peripherals::HASH, Blocking>) {
100 let in1 = b"4BPuGudaDK";
101 let in2 = b"cfFIGf0XSNhFBQ5LaIqzjnRKDRkoWweJI06HLUcicIUGjpuDNfOTQNSrRxDoveDPlazeZtt06SIYO5CvHvsJ98XSfO9yJEMHoDpDAmNQtwZOPlKmdiagRXsJ7w7IjdKpQH6I2t";
102
103 for i in 1..10 {
104 // sha512 block size is 128, so test around there
105 for j in [1, 1, 2, 3, 4, 5, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133] {
106 info!("test_sizes i {} j {}", i, j);
107 let mut sw = sha2::Sha512::new();
108 let mut ctx = hw_hasher.start(Algorithm::SHA512, DataType::Width8, None);
109
110 sw.update(&in1[..i]);
111 sw.update(&in2[..j]);
112 hw_hasher.update_blocking(&mut ctx, &in1[..i]);
113 hw_hasher.update_blocking(&mut ctx, &in2[..j]);
114
115 let sw_digest = sw.finalize();
116 let mut hw_digest = [0u8; 64];
117 hw_hasher.finish_blocking(ctx, &mut hw_digest);
118 info!("Hardware: {:?}", hw_digest);
119 info!("Software: {:?}", sw_digest[..]);
120 defmt::assert!(hw_digest == *sw_digest);
121 }
122 }
123}
124
125#[embassy_executor::main]
126async fn main(_spawner: Spawner) {
127 let p: embassy_stm32::Peripherals = init();
128 let mut hw_hasher = Hash::new_blocking(p.HASH, Irqs);
129
130 test_interrupt(&mut hw_hasher);
131 // Run it a second time to check hash-after-hmac
132 test_interrupt(&mut hw_hasher);
133
134 #[cfg(feature = "hash-v34")]
135 test_sizes(&mut hw_hasher);
98 136
99 info!("Test OK"); 137 info!("Test OK");
100 cortex_m::asm::bkpt(); 138 cortex_m::asm::bkpt();
diff --git a/tests/stm32/src/bin/sdmmc.rs b/tests/stm32/src/bin/sdmmc.rs
index 34a53a725..9f9c526e1 100644
--- a/tests/stm32/src/bin/sdmmc.rs
+++ b/tests/stm32/src/bin/sdmmc.rs
@@ -95,6 +95,9 @@ async fn main(_spawner: Spawner) {
95 95
96 drop(s); 96 drop(s);
97 97
98 // FIXME: this hangs on Rust 1.86 and higher.
99 // I haven't been able to figure out why.
100 /*
98 // ======== Try 1bit. ============== 101 // ======== Try 1bit. ==============
99 info!("initializing in 1-bit mode..."); 102 info!("initializing in 1-bit mode...");
100 let mut s = Sdmmc::new_1bit( 103 let mut s = Sdmmc::new_1bit(
@@ -151,6 +154,7 @@ async fn main(_spawner: Spawner) {
151 assert_eq!(&blocks, &patterns); 154 assert_eq!(&blocks, &patterns);
152 155
153 drop(s); 156 drop(s);
157 */
154 158
155 info!("Test OK"); 159 info!("Test OK");
156 cortex_m::asm::bkpt(); 160 cortex_m::asm::bkpt();
diff --git a/tests/stm32/src/bin/stop.rs b/tests/stm32/src/bin/stop.rs
index 772bc527c..8119c1f39 100644
--- a/tests/stm32/src/bin/stop.rs
+++ b/tests/stm32/src/bin/stop.rs
@@ -19,7 +19,7 @@ use static_cell::StaticCell;
19#[entry] 19#[entry]
20fn main() -> ! { 20fn main() -> ! {
21 Executor::take().run(|spawner| { 21 Executor::take().run(|spawner| {
22 unwrap!(spawner.spawn(async_main(spawner))); 22 spawner.spawn(unwrap!(async_main(spawner)));
23 }); 23 });
24} 24}
25 25
@@ -75,6 +75,6 @@ async fn async_main(spawner: Spawner) {
75 75
76 stop_with_rtc(rtc); 76 stop_with_rtc(rtc);
77 77
78 spawner.spawn(task_1()).unwrap(); 78 spawner.spawn(task_1().unwrap());
79 spawner.spawn(task_2()).unwrap(); 79 spawner.spawn(task_2().unwrap());
80} 80}
diff --git a/tests/stm32/src/bin/usart_rx_ringbuffered.rs b/tests/stm32/src/bin/usart_rx_ringbuffered.rs
index 83c0887ac..15a0b0d60 100644
--- a/tests/stm32/src/bin/usart_rx_ringbuffered.rs
+++ b/tests/stm32/src/bin/usart_rx_ringbuffered.rs
@@ -46,8 +46,8 @@ async fn main(spawner: Spawner) {
46 let rx = rx.into_ring_buffered(unsafe { &mut *core::ptr::addr_of_mut!(DMA_BUF) }); 46 let rx = rx.into_ring_buffered(unsafe { &mut *core::ptr::addr_of_mut!(DMA_BUF) });
47 47
48 info!("Spawning tasks"); 48 info!("Spawning tasks");
49 spawner.spawn(transmit_task(tx)).unwrap(); 49 spawner.spawn(transmit_task(tx).unwrap());
50 spawner.spawn(receive_task(rx)).unwrap(); 50 spawner.spawn(receive_task(rx).unwrap());
51} 51}
52 52
53#[embassy_executor::task] 53#[embassy_executor::task]
diff --git a/tests/stm32/src/bin/wpan_ble.rs b/tests/stm32/src/bin/wpan_ble.rs
index fde1dfa9b..8957bfc04 100644
--- a/tests/stm32/src/bin/wpan_ble.rs
+++ b/tests/stm32/src/bin/wpan_ble.rs
@@ -47,7 +47,7 @@ async fn main(spawner: Spawner) {
47 let config = Config::default(); 47 let config = Config::default();
48 let mut mbox = TlMbox::init(p.IPCC, Irqs, config); 48 let mut mbox = TlMbox::init(p.IPCC, Irqs, config);
49 49
50 spawner.spawn(run_mm_queue(mbox.mm_subsystem)).unwrap(); 50 spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
51 51
52 let sys_event = mbox.sys_subsystem.read().await; 52 let sys_event = mbox.sys_subsystem.read().await;
53 info!("sys event: {}", sys_event.payload()); 53 info!("sys event: {}", sys_event.payload());
diff --git a/tests/stm32/src/bin/wpan_mac.rs b/tests/stm32/src/bin/wpan_mac.rs
index b65ace40f..79e13d524 100644
--- a/tests/stm32/src/bin/wpan_mac.rs
+++ b/tests/stm32/src/bin/wpan_mac.rs
@@ -40,7 +40,7 @@ async fn main(spawner: Spawner) {
40 let config = Config::default(); 40 let config = Config::default();
41 let mbox = TlMbox::init(p.IPCC, Irqs, config); 41 let mbox = TlMbox::init(p.IPCC, Irqs, config);
42 42
43 spawner.spawn(run_mm_queue(mbox.mm_subsystem)).unwrap(); 43 spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
44 44
45 let sys_event = mbox.sys_subsystem.read().await; 45 let sys_event = mbox.sys_subsystem.read().await;
46 info!("sys event: {}", sys_event.payload()); 46 info!("sys event: {}", sys_event.payload());
generated by cgit (git 2.34.1) at 2026-04-05 23:09:10 +0000