diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/stm32/src/common.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index a0ccfe3a4..693fd067f 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs | |||
| @@ -365,7 +365,7 @@ pub fn config() -> Config { | |||
| 365 | { | 365 | { |
| 366 | use embassy_stm32::rcc::*; | 366 | use embassy_stm32::rcc::*; |
| 367 | config.rcc.mux = ClockSrc::PLL1_R; | 367 | config.rcc.mux = ClockSrc::PLL1_R; |
| 368 | config.rcc.hsi16 = true; | 368 | config.rcc.hsi = true; |
| 369 | config.rcc.pll = Some(Pll { | 369 | config.rcc.pll = Some(Pll { |
| 370 | source: PLLSource::HSI, | 370 | source: PLLSource::HSI, |
| 371 | prediv: PllPreDiv::DIV1, | 371 | prediv: PllPreDiv::DIV1, |
| @@ -388,7 +388,7 @@ pub fn config() -> Config { | |||
| 388 | #[cfg(any(feature = "stm32l552ze"))] | 388 | #[cfg(any(feature = "stm32l552ze"))] |
| 389 | { | 389 | { |
| 390 | use embassy_stm32::rcc::*; | 390 | use embassy_stm32::rcc::*; |
| 391 | config.rcc.hsi16 = true; | 391 | config.rcc.hsi = true; |
| 392 | config.rcc.mux = ClockSrc::PLL1_R; | 392 | config.rcc.mux = ClockSrc::PLL1_R; |
| 393 | config.rcc.pll = Some(Pll { | 393 | config.rcc.pll = Some(Pll { |
| 394 | // 110Mhz clock (16 / 4 * 55 / 2) | 394 | // 110Mhz clock (16 / 4 * 55 / 2) |
| @@ -412,7 +412,7 @@ pub fn config() -> Config { | |||
| 412 | use embassy_stm32::rcc::*; | 412 | use embassy_stm32::rcc::*; |
| 413 | config.rcc.mux = ClockSrc::PLL( | 413 | config.rcc.mux = ClockSrc::PLL( |
| 414 | // 32Mhz clock (16 * 4 / 2) | 414 | // 32Mhz clock (16 * 4 / 2) |
| 415 | PLLSource::HSI16, | 415 | PLLSource::HSI, |
| 416 | PLLMul::MUL4, | 416 | PLLMul::MUL4, |
| 417 | PLLDiv::DIV2, | 417 | PLLDiv::DIV2, |
| 418 | ); | 418 | ); |
| @@ -423,7 +423,7 @@ pub fn config() -> Config { | |||
| 423 | use embassy_stm32::rcc::*; | 423 | use embassy_stm32::rcc::*; |
| 424 | config.rcc.mux = ClockSrc::PLL( | 424 | config.rcc.mux = ClockSrc::PLL( |
| 425 | // 32Mhz clock (16 * 4 / 2) | 425 | // 32Mhz clock (16 * 4 / 2) |
| 426 | PLLSource::HSI16, | 426 | PLLSource::HSI, |
| 427 | PLLMul::MUL4, | 427 | PLLMul::MUL4, |
| 428 | PLLDiv::DIV2, | 428 | PLLDiv::DIV2, |
| 429 | ); | 429 | ); |
