5 files changed, 56 insertions, 6 deletions

diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index b1b2f55c3..48598ec2d 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -12,6 +12,8 @@ stm32g071rb = ["embassy-stm32/stm32g071rb", "not-gpdma", "dac-adc-pin"]
 stm32c031c6 = ["embassy-stm32/stm32c031c6", "not-gpdma"]
 stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "not-gpdma", "rng"]
 stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac-adc-pin", "rng"]
+stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng"]
+stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng"]
 stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
 stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
 stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng"]
diff --git a/tests/stm32/src/bin/eth.rs b/tests/stm32/src/bin/eth.rs
index 6d5e05cd6..754354944 100644
--- a/tests/stm32/src/bin/eth.rs
+++ b/tests/stm32/src/bin/eth.rs
@@ -60,6 +60,8 @@ async fn main(spawner: Spawner) {
     let n = 4;
     #[cfg(feature = "stm32f207zg")]
     let n = 5;
+    #[cfg(feature = "stm32h753zi")]
+    let n = 6;
 
     let mac_addr = [0x00, n, 0xDE, 0xAD, 0xBE, 0xEF];
 
diff --git a/tests/stm32/src/bin/gpio.rs b/tests/stm32/src/bin/gpio.rs
index 49d9a60f7..83c96ce95 100644
--- a/tests/stm32/src/bin/gpio.rs
+++ b/tests/stm32/src/bin/gpio.rs
@@ -217,8 +217,7 @@ async fn main(_spawner: Spawner) {
 }
 
 fn delay() {
-    #[cfg(feature = "stm32h755zi")]
-    cortex_m::asm::delay(10000);
-    #[cfg(not(feature = "stm32h755zi"))]
+    #[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi", feature = "stm32h7a3zi"))]
+    cortex_m::asm::delay(9000);
     cortex_m::asm::delay(1000);
 }
diff --git a/tests/stm32/src/bin/rng.rs b/tests/stm32/src/bin/rng.rs
index 65da737d0..b7f361372 100644
--- a/tests/stm32/src/bin/rng.rs
+++ b/tests/stm32/src/bin/rng.rs
@@ -11,7 +11,12 @@ use embassy_stm32::rng::Rng;
 use embassy_stm32::{bind_interrupts, peripherals, rng};
 use {defmt_rtt as _, panic_probe as _};
 
-#[cfg(any(feature = "stm32l4a6zg", feature = "stm32h755zi", feature = "stm32f429zi"))]
+#[cfg(any(
+    feature = "stm32l4a6zg",
+    feature = "stm32h755zi",
+    feature = "stm32h753zi",
+    feature = "stm32f429zi"
+))]
 bind_interrupts!(struct Irqs {
    HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
 });
@@ -23,6 +28,7 @@ bind_interrupts!(struct Irqs {
     feature = "stm32l4a6zg",
     feature = "stm32l073rz",
     feature = "stm32h755zi",
+    feature = "stm32h753zi",
     feature = "stm32f429zi"
 )))]
 bind_interrupts!(struct Irqs {
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 95b5318f7..a0ccfe3a4 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -18,6 +18,10 @@ teleprobe_meta::target!(b"nucleo-stm32f429zi");
 teleprobe_meta::target!(b"nucleo-stm32wb55rg");
 #[cfg(feature = "stm32h755zi")]
 teleprobe_meta::target!(b"nucleo-stm32h755zi");
+#[cfg(feature = "stm32h753zi")]
+teleprobe_meta::target!(b"nucleo-stm32h753zi");
+#[cfg(feature = "stm32h7a3zi")]
+teleprobe_meta::target!(b"nucleo-stm32h7a3zi");
 #[cfg(feature = "stm32u585ai")]
 teleprobe_meta::target!(b"iot-stm32u585ai");
 #[cfg(feature = "stm32h563zi")]
@@ -105,12 +109,18 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
 );
-#[cfg(feature = "stm32h755zi")]
+#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
 define_peris!(
     UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
 );
+#[cfg(feature = "stm32h7a3zi")]
+define_peris!(
+    UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
+    @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+);
 #[cfg(feature = "stm32u585ai")]
 define_peris!(
     UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
@@ -289,7 +299,7 @@ pub fn config() -> Config {
         config.rcc.voltage_scale = VoltageScale::Scale0;
     }
 
-    #[cfg(feature = "stm32h755zi")]
+    #[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
     {
         use embassy_stm32::rcc::*;
         config.rcc.hsi = Some(Hsi::Mhz64);
@@ -320,6 +330,37 @@ pub fn config() -> Config {
         config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
     }
 
+    #[cfg(any(feature = "stm32h7a3zi"))]
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.csi = true;
+        config.rcc.hsi48 = true; // needed for RNG
+        config.rcc.pll_src = PllSource::Hsi;
+        config.rcc.pll1 = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL35,
+            divp: Some(PllDiv::DIV2), // 280 Mhz
+            divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
+            divr: None,
+        });
+        config.rcc.pll2 = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL35,
+            divp: Some(PllDiv::DIV8), // 70 Mhz
+            divq: None,
+            divr: None,
+        });
+        config.rcc.sys = Sysclk::Pll1P; // 280 Mhz
+        config.rcc.ahb_pre = AHBPrescaler::DIV1; // 280 Mhz
+        config.rcc.apb1_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.apb2_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.apb3_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.apb4_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.voltage_scale = VoltageScale::Scale0;
+        config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+    }
+
     #[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
     {
         use embassy_stm32::rcc::*;