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* Merge pull request #1953 from embassy-rs/stm32l-testsDario Nieuwenhuis2023-09-274-2/+102
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| * tests/stm32: add L0, L1, L4, L4+, L5Dario Nieuwenhuis2023-09-264-2/+102
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* Merge pull request #1952 from embassy-rs/stm32-test-cleanupDario Nieuwenhuis2023-09-263-8/+27
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| * stm32/rcc: remove bad limits on l5.Dario Nieuwenhuis2023-09-261-5/+0
| * stm32/rcc: add voltage_scale, flash waitstates.Dario Nieuwenhuis2023-09-262-3/+27
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* Merge pull request #1951 from embassy-rs/stm32-test-cleanupDario Nieuwenhuis2023-09-262-16/+28
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| * stm32/usart: enable fifo mode on usartv4.Dario Nieuwenhuis2023-09-262-16/+28
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* Merge pull request #1950 from embassy-rs/stm32-test-cleanupDario Nieuwenhuis2023-09-2522-75/+94
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| * stm32/usart: return error instead of panicking on bad baudrate.Dario Nieuwenhuis2023-09-2622-75/+94
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* Merge pull request #1949 from xoviat/rtcxoviat2023-09-255-47/+9
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| * rtc: use enable on known working chips onlyxoviat2023-09-251-2/+2
| * stm32/rtc: always set wakeup alarmxoviat2023-09-251-9/+0
| * stm32/rtc: use rccperi enablexoviat2023-09-255-38/+9
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* Merge pull request #1948 from embassy-rs/stm32-test-cleanupDario Nieuwenhuis2023-09-2510-244/+123
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| * tests/stm32: centralize pin configuration.Dario Nieuwenhuis2023-09-257-243/+119
| * Make irq token Copy+CloneDario Nieuwenhuis2023-09-253-1/+4
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* Merge pull request #1947 from ceekdee/rust-lorawan-lora-phy-v2Dario Nieuwenhuis2023-09-2521-124/+56
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| * Update rust-lorawan crate versions.ceekdee2023-09-255-28/+9
| * Merge branch 'embassy-rs:main' into rust-lorawan-lora-phy-v2Chuck Davis2023-09-2416-73/+27
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* | Merge pull request #1945 from xoviat/bd-2xoviat2023-09-241-6/+7
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| * | stm32: fix bd lsixoviat2023-09-241-6/+7
* | | Merge pull request #1943 from embassy-rs/centralize-pwr-syscfgDario Nieuwenhuis2023-09-2415-67/+20
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| * | stm32: centralize enabling pwr, syscfg, flash.Dario Nieuwenhuis2023-09-2515-67/+20
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| * Update for rust-lorawan and lora-phy version 2.ceekdee2023-09-2421-105/+56
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* Merge pull request #1940 from luveti/patch-1Dario Nieuwenhuis2023-09-241-0/+1
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| * stm32: fix rtc exampleluveti2023-09-241-0/+1
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* Merge pull request #1939 from nilfit/spim-anomaly-109Dario Nieuwenhuis2023-09-232-31/+56
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| * Add separate work-around specific flag for DMA errata on NRF52832Priit Laes2023-09-222-12/+14
| * spim: Fix SPIM with polling executorsNils Fitinghoff2023-09-221-22/+45
* | Merge pull request #1938 from xoviat/low-powerxoviat2023-09-221-7/+13
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| * stm32/lp: clamp requested_duration to avoid overflowxoviat2023-09-221-7/+13
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* Merge pull request #1937 from xoviat/low-powerxoviat2023-09-223-82/+101
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| * stm32/low-power: create one critical-section for all time opsxoviat2023-09-213-82/+101
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* Merge pull request #1935 from embassy-rs/stm32-update-metapacgcDario Nieuwenhuis2023-09-211-2/+2
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| * stm32: update metapac.Dario Nieuwenhuis2023-09-221-2/+2
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* Merge pull request #1927 from embassy-rs/stm32-rcc-unify-hDario Nieuwenhuis2023-09-2126-1529/+1195
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| * stm32/rcc: unify h5 and h7.Dario Nieuwenhuis2023-09-2126-1529/+1195
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* Merge pull request #1934 from chrenderle/low-power-l0xoviat2023-09-212-2/+5
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| * fix low-power: APB1 needed for LSEChristian Enderle2023-09-212-2/+5
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* Merge pull request #1930 from xoviat/adcxoviat2023-09-203-59/+100
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| * stm32/adc: make v1 async and leave enxoviat2023-09-203-59/+100
* | Merge pull request #1932 from embassy-rs/h7fixDario Nieuwenhuis2023-09-201-2/+4
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| * | stm32/h7: fix bad PWR reg versions.Dario Nieuwenhuis2023-09-211-2/+4
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* | Merge pull request #1929 from sgoll/exti-levelDario Nieuwenhuis2023-09-191-1/+5
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| * Add get_level() to ExtiInputSebastian Goll2023-09-201-1/+5
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* Merge pull request #1928 from sgoll/fix-r2-voltage-rangeDario Nieuwenhuis2023-09-191-4/+4
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| * Fix typo in F2 RCC voltage rangesSebastian Goll2023-09-191-4/+4
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* Merge pull request #1919 from xoviat/adcxoviat2023-09-183-18/+109
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| * stm32/adc: add async conversionxoviat2023-09-183-18/+109
* | Merge pull request #1924 from embassy-rs/rp-remove-pasteDario Nieuwenhuis2023-09-182-9/+33
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