aboutsummaryrefslogtreecommitdiff
path: root/embassy-stm32/src/dma
Commit message (Expand)AuthorAgeFilesLines
* Enable STM32N6 DMA and I2C clock sourcesLambert Sartory2025-12-112-5/+0
* dma: add functionsxoviat2025-12-091-0/+58
* low-power: rework stoppableperipheral traitsxoviat2025-12-061-22/+18
* GPDMA suspend channel before reset if already enabledAlbin Hedman2025-12-031-0/+5
* timer: clamp compare value before dmaxoviat2025-12-011-0/+4
* stm32: extract busychannel into common apixoviat2025-11-254-58/+28
* low power: store stop mode for dma channelsxoviat2025-11-214-18/+87
* cfg out unused itemseverdrone2025-11-112-0/+5
* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-065-7/+7
* fix: ping-pong helper DMA directionAdrian Figueroa2025-09-053-9/+25
* refactor: make dma implementations match in interfaceelagil2025-09-053-61/+69
* fix: consolidate namingelagil2025-09-052-15/+15
* fix: buildelagil2025-09-052-86/+29
* fix: renamed simple table as per ST nomenclatureetiennecollin2025-09-051-4/+4
* fix: removed unnecessary mut referenceetiennecollin2025-09-051-3/+3
* feat: use register wrappers instead of u32 for LinearItemetiennecollin2025-09-051-15/+12
* feat: add new_with_table() initializer for ring-buffers and removal of Regist...etiennecollin2025-09-053-71/+84
* fix: moved channel configuration from new() to start()etiennecollin2025-09-051-6/+4
* fix: removed functions exposing channel registersetiennecollin2025-09-052-21/+0
* feat: custom dma configuration using RegisterUpdaters structetiennecollin2025-09-053-7/+51
* fix: suspend before resetetiennecollin2025-09-051-0/+3
* feat: use provided TransferOptions instead of defaultsetiennecollin2025-09-051-4/+4
* feat: custom DMA channel configurationetiennecollin2025-09-052-6/+27
* fix: writing reserved bitsetiennecollin2025-09-051-2/+20
* fix: modified dma channel state managementetiennecollin2025-09-052-43/+77
* fix: docstringelagil2025-09-051-1/+1
* fix: build warningselagil2025-09-051-8/+0
* fix: simplifyelagil2025-09-052-73/+5
* fix: build issueselagil2025-09-052-17/+13
* feat: wip, write buffer in halveselagil2025-09-052-107/+53
* chore: change namingelagil2025-09-053-57/+87
* fix: wip gpdmaelagil2025-09-052-15/+16
* fix: load/store orderingelagil2025-09-052-6/+6
* fix: read transfer optionselagil2025-09-051-12/+7
* chore: clean up transfer optionselagil2025-09-053-36/+6
* fix: transfer optionselagil2025-09-052-1/+8
* fix: disable half-complete interruptelagil2025-09-051-2/+2
* style: formattingelagil2025-09-052-17/+11
* feat: ping-pong bufferselagil2025-09-053-16/+92
* feat: gpdma support (wip)elagil2025-09-055-91/+307
* feat: GPDAM linked-list + ringbuffer supportelagil2025-09-054-75/+825
* stm32/dma: fix packing/unpacking not working.Dario Nieuwenhuis2025-07-043-32/+49
* stm32/dma: add missing fence on BDMA start.Dario Nieuwenhuis2025-07-041-3/+3
* Remove Peripheral trait, rename PeripheralRef->Peri.Dario Nieuwenhuis2025-03-274-65/+49
* stm32/cryp: remove DMA generic param.Dario Nieuwenhuis2025-03-251-11/+0
* stm32/hash: remove DMA generic param.Dario Nieuwenhuis2025-03-251-3/+3
* Reset complete count global variable on Dma configurenoracarmig2025-01-261-0/+2
* Merge pull request #3704 from CNLHC/pwm_support_gp32Dario Nieuwenhuis2025-01-212-29/+47
|\
| * refactor: update write DMA transfer function to use separate memory word typeLiu Hancheng2025-01-051-5/+5
| * refactor: update DMA transfer functions to support separate memory and periph...Liu Hancheng2025-01-041-14/+18
generated by cgit (git 2.34.1) at 2026-04-05 22:45:40 +0000