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path: root/embassy-stm32/src/rcc/c0.rs
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* stm32: disable HSI48 if not in useBernát Süli2025-12-191-0/+6
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* Add support for USB CRS syncNarottam Royal2025-09-211-2/+12
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* Added missing guard for hsi48. Updated use of removed enums from stm32-data ↵Chris Storah2025-07-231-0/+1
| | | | u5 chip
* Formatting update to resolve rustfmt errorChris Storah2025-07-231-2/+3
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* Updated version of stm32-data and added c071 and c051 into ci.shChris Storah2025-07-231-9/+2
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* hsi48 field missing for STM32C071obe1line2025-07-211-1/+4
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* Added ccipr1 conditional for STM32C071obe1line2025-07-211-2/+6
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* fixup! feat(stm32-c0): provide a `const` constructor on `rcc::Config`ROMemories2025-05-261-2/+0
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* feat(stm32-c0): provide a `const` constructor on `rcc::Config`ROMemories2025-05-211-4/+11
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* stm32: run cargo fmttechmccat2025-03-281-1/+4
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* stm32: allow using LSI/LSE as SYSCLK on g0/c0techmccat2025-03-281-2/+5
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* Added ADC support for STM32C0.Timofei Korostelev2025-03-201-0/+3
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* Fix & RevertBing Wen2024-11-271-1/+2
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* Add newBing Wen2024-11-271-12/+6
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* Add new feature to enable overclockingBing Wen2024-11-261-4/+9
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* Fix dma nvic issues on dual core linesAlexandros Liarokapis2024-08-171-0/+1
| | | | | | This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup. Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration. This ensures that each core will only handle the interrupts of the DMA channels that it uses.
* stm32: ensure the core runs on HSI clock while setting up rccAurélien Jacobs2024-05-271-17/+27
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* update stm32c0 HSI frequencyTomas Barton2024-03-071-1/+1
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* stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS support.Dario Nieuwenhuis2024-03-041-95/+129
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* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-011-14/+20
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* stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.Dario Nieuwenhuis2024-02-261-7/+7
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* stm32: autogenerate clocks struct, enable mux for all chips.Dario Nieuwenhuis2024-02-021-8/+7
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* stm32: update metapacxoviat2023-10-161-0/+2
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* rcc: ahb/apb -> hclk/pclkxoviat2023-10-151-3/+3
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* stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.Dario Nieuwenhuis2023-10-111-4/+6
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* stm32/rcc: use more PLL etc enums from PAC.Dario Nieuwenhuis2023-10-111-57/+15
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* stm32/rcc: use PLL enums from PAC.Dario Nieuwenhuis2023-10-091-1/+1
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* stm32/rcc: convert bus prescalers to pac enumsxoviat2023-09-161-12/+13
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* stm32/rcc: rename common to busxoviat2023-08-271-1/+1
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* stm32/rcc: extract and combine ahb/apb prescalersxoviat2023-07-301-53/+2
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* Update stm32-metapac, includes chiptool changes to use real Rust enums now.Dario Nieuwenhuis2023-06-291-5/+5
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* stm32: add stm32c0 support.Dario Nieuwenhuis2023-01-171-0/+233