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path: root/embassy-stm32/src/rcc/g4.rs
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* stm32: disable HSI48 if not in useBernát Süli2025-12-191-0/+6
* fixup! feat(stm32-g4): provide a `const` constructor on `rcc::Config`ROMemories2025-05-261-2/+0
* feat(stm32-g4): provide a `const` constructor on `rcc::Config`ROMemories2025-05-211-5/+12
* stm32: update metapac, cleanup clocks a bit.Dario Nieuwenhuis2025-04-181-0/+2
* Add missing clock checkBing Wen2024-11-271-0/+1
* Add newBing Wen2024-11-271-22/+11
* Add new feature to enable overclockingBing Wen2024-11-261-4/+14
* Fix dma nvic issues on dual core linesAlexandros Liarokapis2024-08-171-0/+2
* stm32: ensure the core runs on HSI clock while setting up rccAurélien Jacobs2024-05-271-9/+16
* stm32/rcc: g4: consistent PllSource, add pll pqr limits, simplify a bit.Dario Nieuwenhuis2024-03-041-107/+111
* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-011-64/+14
* [embassy-stm32] G4 RCC refactor amendments and additionsBarnaby Walters2024-02-231-17/+35
* RefinementsBarnaby Walters2024-02-171-35/+32
* Configured SYSCLK after boost mode, added commentsBarnaby Walters2024-02-161-7/+12
* Added documentation, fixed and refined boost and flash read latency configBarnaby Walters2024-02-161-30/+39
* Configured HSI48 if enabled, assert is enabled if chosen as clk48 sourceBarnaby Walters2024-02-161-2/+11
* Removed redundant HSI48 configurationBarnaby Walters2024-02-161-22/+10
* Removed dangling doc commentsBarnaby Walters2024-02-161-2/+2
* Commented out currently unused constantsBarnaby Walters2024-02-161-5/+5
* [embassy-stm32]: started stm32g4 RCC refactorBarnaby Walters2024-02-151-80/+124
* stm32: autogenerate clocks struct, enable mux for all chips.Dario Nieuwenhuis2024-02-021-12/+11
* Add FDCAN clock registers to G4 RCC.Tomasz bla Fortuna2024-01-311-2/+5
* stm32: update stm32-metapac. Fixes USB on STM32WB.Dario Nieuwenhuis2023-12-081-0/+1
* Update stm32-metapac.Dario Nieuwenhuis2023-12-081-0/+2
* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-131-7/+7
* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-051-46/+4
* stm32: rename HSI16 -> HSIDario Nieuwenhuis2023-10-221-7/+7
* stm32/rng: add test.Dario Nieuwenhuis2023-10-161-1/+1
* rcc: ahb/apb -> hclk/pclkxoviat2023-10-151-10/+10
* stm32: expand rcc mux to g4 and h7xoviat2023-10-141-8/+9
* enable clock firstpbert2023-10-121-1/+1
* STM32: combine RccPeripherals reset() and enable() to reset_and_enable()pbert2023-10-121-1/+1
* stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.Dario Nieuwenhuis2023-10-111-3/+6
* stm32/rcc: use more PLL etc enums from PAC.Dario Nieuwenhuis2023-10-111-92/+35
* stm32/rcc: use PLL enums from PAC.Dario Nieuwenhuis2023-10-091-185/+12
* stm32/rcc: convert bus prescalers to pac enumsxoviat2023-09-161-60/+30
* stm32: fix merge issuesxoviat2023-09-051-2/+2
* initial support for STM32G4 ADCDaehyeok Mun2023-09-041-1/+53
* stm32/rcc: rename common to busxoviat2023-08-271-1/+1
* stm32/rcc: cleanup mergexoviat2023-07-301-2/+9
* stm32/rcc: extract and combine ahb/apb prescalersxoviat2023-07-301-33/+3
* STM32G4: Add CRS support to RCCKevin Lannen2023-06-281-1/+76
* stm32g4: PLL: Add support for configuring PLL_P and PLL_QKevin Lannen2023-06-141-35/+172
* Rename to follow ref manual and CubeIDECarl St-Laurent2023-06-081-10/+10
* CleanupCarl St-Laurent2023-06-041-5/+3
* Added Vcore boost mode and Flash wait stateCarl St-Laurent2023-06-041-0/+35
* Better commentsCarl St-Laurent2023-06-041-3/+4
* stm32/rcc: Implement basic PLL support for STM32G4 seriesCarl St-Laurent2023-06-031-1/+162
* Align with updated stm32 metapacRasmus Melchior Jacobsen2023-05-251-31/+53
* embassy-stm32: Simplify timeGrant Miller2022-07-101-9/+9
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