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path: root/embassy-stm32/src/rcc/h.rs
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* stm32: disable HSI48 if not in useBernát Süli2025-12-191-0/+6
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* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-061-1/+4
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* don't save and reset XSPI clock source; let mux config handle itRogan Morrow2025-08-291-12/+2
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* set XSPI clock source to HSI and reset after clock init; dont reset SYSCFGRogan Morrow2025-08-291-1/+18
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* include proper pll divs/divt initializationRick Rogers2025-07-251-1/+33
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* address rustfmt ci checkRick Rogers2025-07-251-3/+3
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* add pll divs/t for h7rsRick Rogers2025-07-241-0/+9
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* feat(stm32-h): provide a `const` constructor on `rcc::Config`ROMemories2025-05-211-5/+11
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* stm32: update metapac, cleanup clocks a bit.Dario Nieuwenhuis2025-04-181-3/+2
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* remove Hz from logSteven Friedman2025-04-081-2/+2
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* Frequency display is now consistentSteven Friedman2025-04-081-1/+1
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* chore: fix buildelagil2025-01-031-4/+4
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* Fix wrong unitJunfeng Liu2024-11-121-1/+1
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* Add presence check for OTG_HS peripheral on STM32H7R/S seriesKevin2024-09-221-7/+7
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* Add USBPHYC clock configuration for H7RS seriesKevin2024-09-221-1/+31
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* Add OTG_HS support for STM32H7R/SKevin2024-09-221-2/+2
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* Fix dma nvic issues on dual core linesAlexandros Liarokapis2024-08-171-1/+2
| | | | | | This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup. Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration. This ensures that each core will only handle the interrupts of the DMA channels that it uses.
* stm32: ensure the core runs on HSI clock while setting up rccAurélien Jacobs2024-05-271-12/+21
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* Remove redundant dsi_phy: None from rccJoël Schulz-Ansres2024-05-021-2/+0
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* Add stm32 dsihost driverJoël Schulz-Ansres2024-05-021-0/+3
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* stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.Dario Nieuwenhuis2024-05-011-55/+160
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* low power for h5eZio Pan2024-04-281-0/+2
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* Check for CPU_FREQ_BOOSTDominic2024-03-091-1/+8
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* Fix incorrect D1CPRE max for STM32H7 RM0468Dominic2024-03-091-1/+1
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* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-011-63/+9
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* added FDCANSEL logic for H7Maia2024-02-271-0/+3
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* stm32: update metapac.Dario Nieuwenhuis2024-02-261-0/+1
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* stm32/rcc: use h7 sdlevel enum from pac.Dario Nieuwenhuis2024-02-121-21/+6
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* stm32: update metapac.Dario Nieuwenhuis2024-02-101-0/+1
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* fix(stm32/h7): use correct unit in vco clock checkBadr Bouslikhin2024-02-061-1/+1
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* stm32: autogenerate clocks struct, enable mux for all chips.Dario Nieuwenhuis2024-02-021-39/+22
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* Initial FDCAN driver implementation.Corey Schuhen2024-01-311-4/+3
| | | | | | | | | | | | | | | | | | | | | Original author: Torin Cooper-Bennun <[email protected]> Cleanup and documentaion by: Tomasz bla Fortuna <[email protected]> Corey Schuhen <[email protected]> Use new PAC method now that the names are common. Use broken out definitions that can be shared with bxcan Populate Rx struct with an embassy timestamp. Remove use of RefCell. As per review comment. - THis will probably get squashed down. Fix
* Add FDCAN clock registers to G4 RCC.Tomasz bla Fortuna2024-01-311-1/+7
| | | | | | | | Author: Adam Morgan <[email protected]> Break definitions out of bxcan that can be used innm fdcan. Typo
* STM32H7: adjust flash latency and programming delay for series in RM0468Oliver Rockstedt2023-12-151-1/+25
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* STM32H7: limit max frequency to 520MHz until cpu frequency boost option is ↵Oliver Rockstedt2023-12-151-1/+1
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* STM32H7: adjust frequency limits for series in RM0468Oliver Rockstedt2023-12-151-1/+8
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* STM32H7: Allow PLL1 DIVP of 1 for certain seriesOliver Rockstedt2023-12-151-2/+7
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* stm32/rcc: add missing h7 power configBadr Bouslikhin2023-12-021-0/+12
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* stm32/rcc: refactor h7 rm0455,rm0468 and rm0468 power managementBadr Bouslikhin2023-12-021-58/+29
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* stm32/rcc: enable power supply configurability for rm0455 and rm0468Badr Bouslikhin2023-12-021-13/+5
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* stm32/rcc: make h7 rm0399 power supply configurableBadr Bouslikhin2023-12-011-1/+147
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* PR feedbackRobertTDowling2023-11-191-2/+2
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* stm32h7 ADC: Fix stalled clock in default h7 configRobertTDowling2023-11-151-1/+6
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* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-051-13/+3
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* stm32/rcc: misc cleanups.Dario Nieuwenhuis2023-10-231-76/+34
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* stm32/tests: add stm32h753zi, stm32h7a3zi.Dario Nieuwenhuis2023-10-211-1/+8
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* stm32/rcc: remove unused enum.Dario Nieuwenhuis2023-10-181-9/+0
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* rcc: ahb/apb -> hclk/pclkxoviat2023-10-151-13/+13
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* stm32: expand rcc mux to g4 and h7xoviat2023-10-141-16/+17
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* stm32/rcc: remove unused lse/lsi fields in h7Dario Nieuwenhuis2023-10-151-8/+0
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