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path: root/embassy-stm32/src/rcc/u5.rs
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* stm32: disable HSI48 if not in useBernát Süli2025-12-191-0/+6
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* stm32: disable HSI if not usedBernát Süli2025-12-181-0/+5
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* Source system clock from MSIS before (de)configuring PLLsgoodhoko2025-12-151-0/+10
| | | | Fixes https://github.com/embassy-rs/embassy/issues/5072
* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-061-3/+6
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* Minor cleanupFrank Stevenson2025-07-241-1/+1
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* Improved error checks, and some cleanupFrank Stevenson2025-07-241-33/+39
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* Panic on improper auto-calibration configurationsFrank Stevenson2025-07-241-3/+2
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* Introduce configration options for Pll fast modes.Frank Stevenson2025-07-241-5/+49
| | | | Ensure that the auto calibration is applied to an active clock.
* Make MSI calibration configurabke.Frank Stevenson2025-07-231-34/+67
| | | | Refine detection and handling of shared clock sources between MSIS and MSIK
* Make more accurate table based MSI frequency calculation based on datasheet.Frank Stevenson2025-06-171-4/+49
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* U5: Apply auto-calibration on MSIK and calculate frequencies for detuned LSE ↵Frank Stevenson2025-06-171-3/+31
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* Use modify() for subsequent changes to RCC.cr()Frank Stevenson2025-06-031-3/+3
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* feat(stm32-u5): provide a `const` constructor on `rcc::Config`ROMemories2025-05-211-5/+11
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* stm32: update metapac, cleanup clocks a bit.Dario Nieuwenhuis2025-04-181-4/+0
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* remove Hz from logSteven Friedman2025-04-081-1/+1
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* Update STM32U5 OTG HS clock handlingMarvin Drees2024-12-101-0/+29
| | | | Signed-off-by: Marvin Drees <[email protected]>
* RCC: add lsi and lse clock frequency for STM32U5Christian Enderle2024-11-071-2/+6
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* RCC: added msik for stm32u5Christian Enderle2024-11-071-6/+36
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* fix: STM32U5 RCC fieldselagil2024-11-061-0/+2
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* Fix dma nvic issues on dual core linesAlexandros Liarokapis2024-08-171-0/+1
| | | | | | This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup. Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration. This ensures that each core will only handle the interrupts of the DMA channels that it uses.
* Remove redundant dsi_phy: None from rccJoël Schulz-Ansres2024-05-021-1/+0
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* Add stm32 dsihost driverJoël Schulz-Ansres2024-05-021-0/+3
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* low power for h5eZio Pan2024-04-281-0/+1
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* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-011-1/+6
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* stm32: update metapac.Dario Nieuwenhuis2024-02-261-0/+2
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* stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.Dario Nieuwenhuis2024-02-261-10/+10
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* stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.Dario Nieuwenhuis2024-02-231-346/+281
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* stm32: update metapac.Dario Nieuwenhuis2024-02-101-0/+1
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* stm32: autogenerate clocks struct, enable mux for all chips.Dario Nieuwenhuis2024-02-021-14/+32
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* Fix formatting of commentsTyler Gilbert2024-01-031-4/+4
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* Update u5.rsTyler2024-01-031-10/+8
| | | Update comments on p and q divider values to correctly describe what the clock outputs are used for.
* Update STM32 RCC U5 to support P and Q dividersTyler Gilbert2024-01-031-0/+18
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* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-131-11/+11
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* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-051-6/+3
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* stm32/rcc: merge wl into l4/l5.Dario Nieuwenhuis2023-10-231-1/+1
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* stm32: rename HSI16 -> HSIDario Nieuwenhuis2023-10-221-14/+15
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* stm32: update metapacxoviat2023-10-201-2/+2
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* stm32/rng: add test.Dario Nieuwenhuis2023-10-161-1/+1
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* rcc: ahb/apb -> hclk/pclkxoviat2023-10-151-8/+8
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* stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.Dario Nieuwenhuis2023-10-111-4/+5
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* stm32/rcc: use PLL enums from PAC.Dario Nieuwenhuis2023-10-091-195/+81
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* stm32: u5: implement >55 MHz clock speedsWill Glynn2023-10-051-85/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows STM32U5 devices to operate at 160 MHz. On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster clocks require using PLL1's R output, though PLL1 can serve other functions besides using the R output for the system clock. This commit extracts a public `PllConfig` struct, primarily to place associated constructors on that type, but also with an eye towards enabling the P and Q outputs in a later commit. STM32U5 PLLs have various frequency requirements on each stage: after the `m` prescaler, after the `n` multiplier, and after the `r` divider. This commit implements the associated checks as assertions. This commit fixes clock calculation and PLL register configuration errors in PLL initialization. STM32U5 has a PWR peripheral which can be configured to push Vcore into different voltage ranges. System clocks exceeding 55 MHz require range 2, and system clocks exceeding 110 MHz require range 1. This commit adds `voltage_range` to `Config` and configures PWR as directed. The voltage range implies different performance limits on various clock signals, including inside a PLL. This commit implements voltage range <-> frequency range checks as assertions, and extracts the otherwise-repeated MSIS, HSI16, and HSE initialization into private methods on `Config`. STM32U5 frequencies above 55 MHz require using the PWR EPOD booster. The EPOD booster requires configuring a second `m` term for PLL1, `mboost`, such that it falls in a particular range. (Recall that >50 MHz cannot be reached without PLL1, so there is no scenario where EPOD is needed but PLL1 is not.) This commit configures and enables the EPOD booster automatically as required.
* stm32: use PAC enums for VOS.Dario Nieuwenhuis2023-09-181-10/+10
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* stm32/rcc: convert bus prescalers to pac enumsxoviat2023-09-161-48/+8
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* stm32: add stm32wba support.Dario Nieuwenhuis2023-09-161-1/+1
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* stm32/rcc: rename common to busxoviat2023-08-271-2/+2
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* stm32/rcc: extract and combine ahb/apb prescalersxoviat2023-07-301-71/+8
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* Update stm32-metapac, includes chiptool changes to use real Rust enums now.Dario Nieuwenhuis2023-06-291-1/+1
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* Fix APB clock calculation for several STM32 familiesEric Yanush2023-03-161-2/+2
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* stm32/rcc: fix u5 pll, add hsi48.Dario Nieuwenhuis2023-01-111-8/+22
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