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path: root/embassy-stm32/src/sai/mod.rs
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* allow again to set nodiv independently of master clock dividerRoman Lim2025-12-091-4/+6
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* use try_into and unwrapeverdrone2025-11-151-6/+1
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* add error message and convert to u8everdrone2025-10-231-1/+6
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* allow setting stm32 SAI frame_length to 256everdrone2025-10-221-1/+1
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* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-061-3/+3
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* stm32/afio: make af_num() unavailable in afio chips.Dario Nieuwenhuis2025-09-061-5/+5
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* stm32: peri_v1_bar now enables cfgs peri_v1 and peri_v1_bar.Dario Nieuwenhuis2025-09-051-5/+5
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* stm32/sai: update for new metapac, simplify cfgs.Dario Nieuwenhuis2025-09-051-267/+51
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* fix: buildelagil2025-09-051-2/+2
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* feat: add new_with_table() initializer for ring-buffers and removal of ↵etiennecollin2025-09-051-5/+4
| | | | | | | | | | | | | | | | RegisterUpdaters - It is now possible to pass a linked-list table to the ring-buffer with the `new_with_table()` function or use the `new()` function for a basic ring-buffer setup. - A `simple_ring_buffer_table()` function was added to the read and write ring-buffers to generate the same table as the one created by `new()` in case the user only wants to customize the default table options. - RegisterUpdaters have been removed as the user now has direct access to the table and its items if needed. See: https://github.com/elagil/embassy/pull/1#issuecomment-2891997294
* feat: custom dma configuration using RegisterUpdaters structetiennecollin2025-09-051-2/+3
| | | | | See this PR comment: https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2889283939
* feat: GPDAM linked-list + ringbuffer supportelagil2025-09-051-9/+0
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* Merge branch 'main' into feat-independent-nodivTomaz Maia Suller2025-08-261-4/+4
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| * stm32/sai: fix WB MCKDIVtomaz-suller2025-08-261-4/+4
| | | | | | | | WB MCKDIV has a width of 6 bits (RM0434 Rev 14, p. 1269).
* | stm32/sai: make NODIV independent of MCKDIVtomaz-suller2025-08-261-1/+3
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* fix: stm32 wb saiUlf Lilleengen2025-08-251-28/+22
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* Remove Peripheral trait, rename PeripheralRef->Peri.Dario Nieuwenhuis2025-03-271-38/+33
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* stm32: do not use private constructorHendrik v. Raven2025-02-281-1/+1
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* Allow chips from L5 (sai_v3_2pdm) and H7 (sai_v3_4pdm) families to use ↵noracarmig2025-01-261-6/+6
| | | | external sai sync
* chore: fix buildelagil2025-01-031-22/+22
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* refactor: naming of wait functionselagil2024-11-171-2/+2
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* feat: SAI/ringbuffer add function to wait for any write errorelagil2024-11-171-0/+16
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* fix(SAI): disallow start without initial writeelagil2024-11-161-13/+14
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* fix: flush SAI FIFO on initelagil2024-11-151-2/+4
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* fix: flush SAI FIFO on disableelagil2024-11-151-0/+1
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* stm32: fix ringbugger overrun errors due to bad dma wrap-around behaviorAlexandros Liarokapis2024-10-151-2/+8
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* fix: pull-down clock/data lines for receiveelagil2024-09-101-2/+2
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* feat: add function to check if SAI is mutedelagil2024-08-241-0/+15
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* stm32/gpio: refactor AfTypeJan Špaček2024-06-161-14/+6
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* Add Clone and Copy to Error typesdvdsk2024-06-061-1/+1
| | | | | None of them are `non-exaustative`, they are all small enough to be copy (I estimate none are larger than 4 bytes).
* stm32/rcc: replace generated enable/disable code with runtime infoJan Špaček2024-05-251-3/+3
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* stm32: use private_bounds for sealed traits.Dario Nieuwenhuis2024-03-231-22/+19
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* STM32: SAI: Fix MCKDIV for SAI v3/v4Adam Greig2024-03-191-1/+143
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* stm32: update metapac.Dario Nieuwenhuis2024-02-261-25/+33
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* stm32/dma: add AnyChannel, add support for BDMA on H7.Dario Nieuwenhuis2024-02-241-29/+20
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* stm32: update metapac.Dario Nieuwenhuis2024-01-101-8/+1
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* stm32/sai: fix typo.Dario Nieuwenhuis2023-12-191-3/+3
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* stm32/sai: docs, remove unused enums.Dario Nieuwenhuis2023-12-191-78/+104
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* stm32/sai: remove unused Word trait.Dario Nieuwenhuis2023-12-191-2/+0
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* stm32/sai: deduplicate code for subblocks A/B.Dario Nieuwenhuis2023-12-191-223/+108
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* stm32/sai: remove unimplemented SetConfig.Dario Nieuwenhuis2023-12-191-19/+0
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* stm32: add some docs.Dario Nieuwenhuis2023-12-181-2/+2
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* stm32/sai: fix build on chips with only SAI4 (like stm32h725re), improve ↵Dario Nieuwenhuis2023-11-191-32/+38
| | | | sync config.
* enable clock firstpbert2023-10-121-2/+2
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* STM32: combine RccPeripherals reset() and enable() to reset_and_enable()pbert2023-10-121-27/+27
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* Add some uncontroversial derives to Error typesJames Munns2023-10-061-1/+1
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* stm32: update set_configxoviat2023-10-011-2/+6
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* Issue #1986 fix ci build errorsTyler Gilbert2023-09-301-3/+3
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* issue #1986 separate blocks to prevent unsafe user codeTyler Gilbert2023-09-301-126/+162
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* Issue #1986 add PartialEq to SyncEnable to fix build error on sai_v4Tyler Gilbert2023-09-301-1/+1
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