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* | stm32: update metapacxoviat2023-10-201-8/+1
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* stm32/rcc: refactor and unify f4 into f7.Dario Nieuwenhuis2023-10-181-5/+17
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* stm32/rcc: refactor f7.Dario Nieuwenhuis2023-10-181-1/+17
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* stm32: update metapacxoviat2023-10-171-3/+10
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* stm32/tests: add stm32wl hil.Dario Nieuwenhuis2023-10-171-0/+17
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* stm32: update metapacxoviat2023-10-161-1/+1
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* stm32/rng: add test.Dario Nieuwenhuis2023-10-161-0/+50
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* stm32/rcc: unify L4 and L5.Dario Nieuwenhuis2023-10-161-7/+10
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* stm32/rcc: add better support for L4/L4+ differences.Dario Nieuwenhuis2023-10-161-1/+1
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* stm32/rcc: port L4 to the "flattened" API like h5/h7.Dario Nieuwenhuis2023-10-151-9/+11
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* time: Update examples, tests, and other code to use new Timer::after_x ↵Adam Greig2023-10-155-14/+14
| | | | convenience methods
* stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.Dario Nieuwenhuis2023-10-112-19/+4
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* stm32/rcc: unify L0 and L1.Dario Nieuwenhuis2023-10-111-1/+1
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* stm32/rcc: use more PLL etc enums from PAC.Dario Nieuwenhuis2023-10-111-4/+4
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* Patch tests & examplesGabriel Górski2023-10-091-2/+1
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* stm32/rcc: use PLL enums from PAC.Dario Nieuwenhuis2023-10-091-21/+21
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* h7: enable rtc testMatt Ickstadt2023-10-061-4/+13
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* Remove a few ultra-verbose logs.Dario Nieuwenhuis2023-10-031-1/+1
| | | | | | They're heavily spamming logs for HIL tests, and I don't believe they're valuable now that the thing they helped debug in their young age is now solid and mature.
* stm32/hil: add f2, f3, f7, l49Dario Nieuwenhuis2023-10-032-3/+78
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* tests/stm32: use default clock configxoviat2023-10-021-1/+4
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* tests/stm32: add eth test.Dario Nieuwenhuis2023-10-022-0/+148
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* tests/stm32: add L0, L1, L4, L4+, L5Dario Nieuwenhuis2023-09-261-1/+90
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* stm32/usart: enable fifo mode on usartv4.Dario Nieuwenhuis2023-09-261-16/+26
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* stm32/usart: return error instead of panicking on bad baudrate.Dario Nieuwenhuis2023-09-263-5/+5
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* tests/stm32: centralize pin configuration.Dario Nieuwenhuis2023-09-257-243/+119
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* stm32/low-power: create one critical-section for all time opsxoviat2023-09-211-10/+23
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* stm32/rcc: unify h5 and h7.Dario Nieuwenhuis2023-09-211-3/+26
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* ci: fix testsxoviat2023-09-172-2/+6
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* stm32: fix rtc wakeup timing and add dbgxoviat2023-08-271-2/+4
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* stm32: re-export rtcclocksourcexoviat2023-08-272-2/+4
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* tests/stm32: add stop and cleanpuxoviat2023-08-261-0/+53
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* stm32/can: make latency assertion more lenient.Dario Nieuwenhuis2023-08-201-2/+2
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* tests/stm32: fix rtc testxoviat2023-08-081-10/+6
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* stm32/can: Fix latency measurement in testschemicstry2023-07-311-3/+13
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* Merge remote-tracking branch 'origin/main' into bxcan_timestampchemicstry2023-07-314-12/+92
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| * Set frequency in stm32 SPI examplesbofh2023-07-312-10/+12
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| * Remove unused importsbofh2023-07-302-2/+0
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| * Fix more stm32 SPI examplesbofh2023-07-302-2/+0
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| * Add DAC HIL test with ADCJuliDi2023-07-272-0/+82
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* | stm32/can: implement proper RX timestampschemicstry2023-07-251-3/+10
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* stm32/rcc: use wpan default only for wpanxoviat2023-07-242-2/+10
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* wpan: further optimize mac eventxoviat2023-07-201-14/+9
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* - optimize event to parse opcode only oncexoviat2023-07-191-11/+20
| | | | | - optimze channels - return mut ref for smoltcp rx
* wpan/mac: use lifetimes to control eventsxoviat2023-07-161-12/+20
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* wpan/mac: use slice view to avoid copyxoviat2023-07-161-1/+5
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* wpan: factor mac logic into other modxoviat2023-07-151-3/+3
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* wpan: add mac testxoviat2023-07-153-1/+111
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* rp/gpio: fix is_set_high/is_set_low, expand tests.Dario Nieuwenhuis2023-07-111-2/+34
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* Merge pull request #1578 from schphil/can-splitxoviat2023-07-051-2/+5
|\ | | | | | | stm32 can split method
| * fix stm32 can testPhilipp Scheff2023-07-041-1/+1
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