1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
|
use core::ptr::write_volatile;
use core::sync::atomic::{Ordering, fence};
use super::{FlashSector, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub(crate) unsafe fn lock() {
if !pac::FLASH.nscr().read().lock() {
pac::FLASH.nscr().modify(|r| {
r.set_lock(true);
});
}
}
pub(crate) unsafe fn unlock() {
// TODO: check locked first
while pac::FLASH.nssr().read().bsy() {
#[cfg(feature = "defmt")]
defmt::trace!("busy")
}
// only unlock if locked to begin with
if pac::FLASH.nscr().read().lock() {
pac::FLASH.nskeyr().write_value(0x4567_0123);
pac::FLASH.nskeyr().write_value(0xCDEF_89AB);
}
}
pub(crate) unsafe fn enable_blocking_write() {
assert_eq!(0, WRITE_SIZE % 4);
}
pub(crate) unsafe fn disable_blocking_write() {}
pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
// // We cannot have the write setup sequence in begin_write as it depends on the address
// let bank = if start_address < BANK1_REGION.end() {
// pac::FLASH.bank(0)
// } else {
// pac::FLASH.bank(1)
// };
cortex_m::asm::isb();
cortex_m::asm::dsb();
fence(Ordering::SeqCst);
clear_all_err();
pac::FLASH.nscr().write(|w| {
w.set_pg(true);
// w.set_psize(2); // 32 bits at once
});
let mut res = None;
let mut address = start_address;
// TODO: see write size
for val in buf.chunks(4) {
write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
address += val.len() as u32;
res = Some(blocking_wait_ready().map_err(|e| {
error!("write err");
e
}));
pac::FLASH.nssr().modify(|w| {
if w.eop() {
w.set_eop(true);
}
});
if unwrap!(res).is_err() {
break;
}
}
cortex_m::asm::isb();
cortex_m::asm::dsb();
fence(Ordering::SeqCst);
pac::FLASH.nscr().write(|w| w.set_pg(false));
unwrap!(res)
}
pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
// pac::FLASH.wrp2r_cur().read().wrpsg()
// TODO: write protection check
if pac::FLASH.nscr().read().lock() == true {
error!("flash locked");
}
loop {
let sr = pac::FLASH.nssr().read();
if !sr.bsy() && !sr.dbne() {
break;
}
}
clear_all_err();
pac::FLASH.nscr().modify(|r| {
// TODO: later check bank swap
r.set_bksel(match sector.bank {
crate::flash::FlashBank::Bank1 => stm32_metapac::flash::vals::NscrBksel::B_0X0,
crate::flash::FlashBank::Bank2 => stm32_metapac::flash::vals::NscrBksel::B_0X1,
_ => unreachable!(),
});
r.set_snb(sector.index_in_bank);
r.set_ser(true);
});
pac::FLASH.nscr().modify(|r| {
r.set_strt(true);
});
cortex_m::asm::isb();
cortex_m::asm::dsb();
fence(Ordering::SeqCst);
let ret: Result<(), Error> = blocking_wait_ready().map_err(|e| {
error!("erase err");
e
});
pac::FLASH.nscr().modify(|w| w.set_ser(false));
clear_all_err();
ret
}
pub(crate) unsafe fn clear_all_err() {
pac::FLASH.nssr().modify(|_| {})
}
unsafe fn blocking_wait_ready() -> Result<(), Error> {
loop {
let sr = pac::FLASH.nssr().read();
if !sr.bsy() {
if sr.optchangeerr() {
error!("optchangeerr");
return Err(Error::Prog);
}
if sr.obkwerr() {
error!("obkwerr");
return Err(Error::Seq);
}
if sr.obkerr() {
error!("obkerr");
return Err(Error::Seq);
}
if sr.incerr() {
error!("incerr");
return Err(Error::Unaligned);
}
if sr.strberr() {
error!("strberr");
return Err(Error::Parallelism);
}
if sr.wrperr() {
error!("protected");
return Err(Error::Protected);
}
return Ok(());
}
}
}
|
