Merge pull request #184 from bobmcwhirter/spi_v3

Spi v3

121 files changed, 14862 insertions, 6726 deletions

diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 81bd032c8..65f42b158 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -182,119 +182,119 @@ stm32f479vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_r
 stm32f479vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
 stm32f479zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
 stm32f479zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
-stm32h723ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h723vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h723ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h723zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h725zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h730ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h730ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h730vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h730zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h733vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h733zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h735ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h735ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h735rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h735vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h735zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h742zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h743zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h745zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h747zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h750ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h750vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h750xb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h750zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h753ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h753bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h753ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h753vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h753xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h753zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h755bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h755ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h755xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h755zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h757ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h757bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h757ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h757xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h757zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3lg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7a3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b0ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b0ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b0rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b0vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b0zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
-stm32h7b3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h723ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h723vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h723ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h723zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h733vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h733zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750xb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3lg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
 stm32l412c8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
 stm32l412cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
 stm32l412k8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
@@ -450,6 +450,7 @@ _sdmmc_v2 = []
 _spi = []
 _spi_v1 = []
 _spi_v2 = []
+_spi_v3 = []
 _stm32f4 = []
 _stm32h7 = []
 _stm32l4 = []
diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py
index 3eb570f19..6c931e4a7 100644
--- a/embassy-stm32/gen.py
+++ b/embassy-stm32/gen.py
@@ -119,16 +119,17 @@ for chip in chips.values():
                     f.write(f'impl_rng!({name}, HASH_RNG);')
 
             if block_mod == 'spi':
-                clock = peri['clock']
-                f.write(f'impl_spi!({name}, {clock});')
-                for pin, funcs in af.items():
-                    if pin in pins:
-                        if func := funcs.get(f'{name}_SCK'):
-                            f.write(f'impl_spi_pin!({name}, SckPin, {pin}, {func});')
-                        if func := funcs.get(f'{name}_MOSI'):
-                            f.write(f'impl_spi_pin!({name}, MosiPin, {pin}, {func});')
-                        if func := funcs.get(f'{name}_MISO'):
-                            f.write(f'impl_spi_pin!({name}, MisoPin, {pin}, {func});')
+                if 'clock' in peri:
+                    clock = peri['clock']
+                    f.write(f'impl_spi!({name}, {clock});')
+                    for pin, funcs in af.items():
+                        if pin in pins:
+                            if func := funcs.get(f'{name}_SCK'):
+                                f.write(f'impl_spi_pin!({name}, SckPin, {pin}, {func});')
+                            if func := funcs.get(f'{name}_MOSI'):
+                                f.write(f'impl_spi_pin!({name}, MosiPin, {pin}, {func});')
+                            if func := funcs.get(f'{name}_MISO'):
+                                f.write(f'impl_spi_pin!({name}, MisoPin, {pin}, {func});')
 
             if block_mod == 'gpio':
                 custom_singletons = True
diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs
index 42af348da..ca3190ecd 100644
--- a/embassy-stm32/src/pac/regs.rs
+++ b/embassy-stm32/src/pac/regs.rs
@@ -1,6 +1,6 @@
 #![no_std]
 #![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"]
-pub mod syscfg_h7 {
+pub mod syscfg_l4 {
     use crate::generic::*;
     #[doc = "System configuration controller"]
     #[derive(Copy, Clone)]
@@ -8,8 +8,12 @@ pub mod syscfg_h7 {
     unsafe impl Send for Syscfg {}
     unsafe impl Sync for Syscfg {}
     impl Syscfg {
-        #[doc = "peripheral mode configuration register"]
-        pub fn pmcr(self) -> Reg<regs::Pmcr, RW> {
+        #[doc = "memory remap register"]
+        pub fn memrmp(self) -> Reg<regs::Memrmp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "configuration register 1"]
+        pub fn cfgr1(self) -> Reg<regs::Cfgr1, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
         #[doc = "external interrupt configuration register 1"]
@@ -17,968 +21,1030 @@ pub mod syscfg_h7 {
             assert!(n < 4usize);
             unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
         }
-        #[doc = "compensation cell control/status register"]
-        pub fn cccsr(self) -> Reg<regs::Cccsr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
-        }
-        #[doc = "SYSCFG compensation cell value register"]
-        pub fn ccvr(self) -> Reg<regs::Ccvr, R> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
-        }
-        #[doc = "SYSCFG compensation cell code register"]
-        pub fn cccr(self) -> Reg<regs::Cccr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(40usize)) }
-        }
-        #[doc = "SYSCFG power control register"]
-        pub fn pwrcr(self) -> Reg<regs::Pwrcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(44usize)) }
-        }
-        #[doc = "SYSCFG package register"]
-        pub fn pkgr(self) -> Reg<regs::Pkgr, R> {
-            unsafe { Reg::from_ptr(self.0.add(292usize)) }
-        }
-        #[doc = "SYSCFG user register 0"]
-        pub fn ur0(self) -> Reg<regs::Ur0, R> {
-            unsafe { Reg::from_ptr(self.0.add(768usize)) }
-        }
-        #[doc = "SYSCFG user register 2"]
-        pub fn ur2(self) -> Reg<regs::Ur2, RW> {
-            unsafe { Reg::from_ptr(self.0.add(776usize)) }
-        }
-        #[doc = "SYSCFG user register 3"]
-        pub fn ur3(self) -> Reg<regs::Ur3, RW> {
-            unsafe { Reg::from_ptr(self.0.add(780usize)) }
-        }
-        #[doc = "SYSCFG user register 4"]
-        pub fn ur4(self) -> Reg<regs::Ur4, R> {
-            unsafe { Reg::from_ptr(self.0.add(784usize)) }
-        }
-        #[doc = "SYSCFG user register 5"]
-        pub fn ur5(self) -> Reg<regs::Ur5, R> {
-            unsafe { Reg::from_ptr(self.0.add(788usize)) }
-        }
-        #[doc = "SYSCFG user register 6"]
-        pub fn ur6(self) -> Reg<regs::Ur6, R> {
-            unsafe { Reg::from_ptr(self.0.add(792usize)) }
-        }
-        #[doc = "SYSCFG user register 7"]
-        pub fn ur7(self) -> Reg<regs::Ur7, R> {
-            unsafe { Reg::from_ptr(self.0.add(796usize)) }
-        }
-        #[doc = "SYSCFG user register 8"]
-        pub fn ur8(self) -> Reg<regs::Ur8, R> {
-            unsafe { Reg::from_ptr(self.0.add(800usize)) }
-        }
-        #[doc = "SYSCFG user register 9"]
-        pub fn ur9(self) -> Reg<regs::Ur9, R> {
-            unsafe { Reg::from_ptr(self.0.add(804usize)) }
-        }
-        #[doc = "SYSCFG user register 10"]
-        pub fn ur10(self) -> Reg<regs::Ur10, R> {
-            unsafe { Reg::from_ptr(self.0.add(808usize)) }
-        }
-        #[doc = "SYSCFG user register 11"]
-        pub fn ur11(self) -> Reg<regs::Ur11, R> {
-            unsafe { Reg::from_ptr(self.0.add(812usize)) }
-        }
-        #[doc = "SYSCFG user register 12"]
-        pub fn ur12(self) -> Reg<regs::Ur12, R> {
-            unsafe { Reg::from_ptr(self.0.add(816usize)) }
-        }
-        #[doc = "SYSCFG user register 13"]
-        pub fn ur13(self) -> Reg<regs::Ur13, R> {
-            unsafe { Reg::from_ptr(self.0.add(820usize)) }
-        }
-        #[doc = "SYSCFG user register 14"]
-        pub fn ur14(self) -> Reg<regs::Ur14, RW> {
-            unsafe { Reg::from_ptr(self.0.add(824usize)) }
+        #[doc = "SCSR"]
+        pub fn scsr(self) -> Reg<regs::Scsr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
         }
-        #[doc = "SYSCFG user register 15"]
-        pub fn ur15(self) -> Reg<regs::Ur15, R> {
-            unsafe { Reg::from_ptr(self.0.add(828usize)) }
+        #[doc = "CFGR2"]
+        pub fn cfgr2(self) -> Reg<regs::Cfgr2, RW> {
+            unsafe { Reg::from_ptr(self.0.add(28usize)) }
         }
-        #[doc = "SYSCFG user register 16"]
-        pub fn ur16(self) -> Reg<regs::Ur16, R> {
-            unsafe { Reg::from_ptr(self.0.add(832usize)) }
+        #[doc = "SWPR"]
+        pub fn swpr(self) -> Reg<regs::Swpr, W> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
         }
-        #[doc = "SYSCFG user register 17"]
-        pub fn ur17(self) -> Reg<regs::Ur17, R> {
-            unsafe { Reg::from_ptr(self.0.add(836usize)) }
+        #[doc = "SKR"]
+        pub fn skr(self) -> Reg<regs::Skr, W> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "SYSCFG user register 12"]
+        #[doc = "memory remap register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur12(pub u32);
-        impl Ur12 {
-            #[doc = "Secure mode"]
-            pub const fn secure(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
+        pub struct Memrmp(pub u32);
+        impl Memrmp {
+            #[doc = "Memory mapping selection"]
+            pub const fn mem_mode(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x07;
+                val as u8
+            }
+            #[doc = "Memory mapping selection"]
+            pub fn set_mem_mode(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+            }
+            #[doc = "QUADSPI memory mapping swap"]
+            pub const fn qfs(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "Secure mode"]
-            pub fn set_secure(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "QUADSPI memory mapping swap"]
+            pub fn set_qfs(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Flash Bank mode selection"]
+            pub const fn fb_mode(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Flash Bank mode selection"]
+            pub fn set_fb_mode(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
         }
-        impl Default for Ur12 {
-            fn default() -> Ur12 {
-                Ur12(0)
+        impl Default for Memrmp {
+            fn default() -> Memrmp {
+                Memrmp(0)
             }
         }
-        #[doc = "SYSCFG user register 6"]
+        #[doc = "SWPR"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur6(pub u32);
-        impl Ur6 {
-            #[doc = "Protected area start address for bank 1"]
-            pub const fn pa_beg_1(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x0fff;
-                val as u16
-            }
-            #[doc = "Protected area start address for bank 1"]
-            pub fn set_pa_beg_1(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
-            }
-            #[doc = "Protected area end address for bank 1"]
-            pub const fn pa_end_1(&self) -> u16 {
-                let val = (self.0 >> 16usize) & 0x0fff;
-                val as u16
+        pub struct Swpr(pub u32);
+        impl Swpr {
+            #[doc = "SRAWM2 write protection."]
+            pub fn pwp(&self, n: usize) -> bool {
+                assert!(n < 32usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
             }
-            #[doc = "Protected area end address for bank 1"]
-            pub fn set_pa_end_1(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
+            #[doc = "SRAWM2 write protection."]
+            pub fn set_pwp(&mut self, n: usize, val: bool) {
+                assert!(n < 32usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Ur6 {
-            fn default() -> Ur6 {
-                Ur6(0)
+        impl Default for Swpr {
+            fn default() -> Swpr {
+                Swpr(0)
             }
         }
-        #[doc = "SYSCFG user register 16"]
+        #[doc = "configuration register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur16(pub u32);
-        impl Ur16 {
-            #[doc = "Freeze independent watchdog in Stop mode"]
-            pub const fn fziwdgstp(&self) -> bool {
+        pub struct Cfgr1(pub u32);
+        impl Cfgr1 {
+            #[doc = "Firewall disable"]
+            pub const fn fwdis(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Freeze independent watchdog in Stop mode"]
-            pub fn set_fziwdgstp(&mut self, val: bool) {
+            #[doc = "Firewall disable"]
+            pub fn set_fwdis(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Private key programmed"]
-            pub const fn pkp(&self) -> bool {
+            #[doc = "I/O analog switch voltage booster enable"]
+            pub const fn boosten(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I/O analog switch voltage booster enable"]
+            pub fn set_boosten(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
+            pub const fn i2c_pb6_fmp(&self) -> bool {
                 let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "Private key programmed"]
-            pub fn set_pkp(&mut self, val: bool) {
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
+            pub fn set_i2c_pb6_fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
+            pub const fn i2c_pb7_fmp(&self) -> bool {
+                let val = (self.0 >> 17usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
+            pub fn set_i2c_pb7_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
+            pub const fn i2c_pb8_fmp(&self) -> bool {
+                let val = (self.0 >> 18usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
+            pub fn set_i2c_pb8_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
+            pub const fn i2c_pb9_fmp(&self) -> bool {
+                let val = (self.0 >> 19usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
+            pub fn set_i2c_pb9_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+            }
+            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
+            pub const fn i2c1_fmp(&self) -> bool {
+                let val = (self.0 >> 20usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
+            pub fn set_i2c1_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+            }
+            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
+            pub const fn i2c2_fmp(&self) -> bool {
+                let val = (self.0 >> 21usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
+            pub fn set_i2c2_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+            }
+            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
+            pub const fn i2c3_fmp(&self) -> bool {
+                let val = (self.0 >> 22usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
+            pub fn set_i2c3_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+            }
+            #[doc = "Floating Point Unit interrupts enable bits"]
+            pub const fn fpu_ie(&self) -> u8 {
+                let val = (self.0 >> 26usize) & 0x3f;
+                val as u8
+            }
+            #[doc = "Floating Point Unit interrupts enable bits"]
+            pub fn set_fpu_ie(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize);
+            }
         }
-        impl Default for Ur16 {
-            fn default() -> Ur16 {
-                Ur16(0)
+        impl Default for Cfgr1 {
+            fn default() -> Cfgr1 {
+                Cfgr1(0)
             }
         }
-        #[doc = "SYSCFG user register 3"]
+        #[doc = "external interrupt configuration register 4"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur3(pub u32);
-        impl Ur3 {
-            #[doc = "Boot Address 1"]
-            pub const fn boot_add1(&self) -> u16 {
-                let val = (self.0 >> 16usize) & 0xffff;
-                val as u16
+        pub struct Exticr(pub u32);
+        impl Exticr {
+            #[doc = "EXTI12 configuration bits"]
+            pub fn exti(&self, n: usize) -> u8 {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x0f;
+                val as u8
             }
-            #[doc = "Boot Address 1"]
-            pub fn set_boot_add1(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+            #[doc = "EXTI12 configuration bits"]
+            pub fn set_exti(&mut self, n: usize, val: u8) {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
             }
         }
-        impl Default for Ur3 {
-            fn default() -> Ur3 {
-                Ur3(0)
+        impl Default for Exticr {
+            fn default() -> Exticr {
+                Exticr(0)
             }
         }
-        #[doc = "SYSCFG user register 8"]
+        #[doc = "CFGR2"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur8(pub u32);
-        impl Ur8 {
-            #[doc = "Mass erase protected area disabled for bank 2"]
-            pub const fn mepad_2(&self) -> bool {
+        pub struct Cfgr2(pub u32);
+        impl Cfgr2 {
+            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
+            pub const fn cll(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Mass erase protected area disabled for bank 2"]
-            pub fn set_mepad_2(&mut self, val: bool) {
+            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
+            pub fn set_cll(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Mass erase secured area disabled for bank 2"]
-            pub const fn mesad_2(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
+            #[doc = "SRAM2 parity lock bit"]
+            pub const fn spl(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Mass erase secured area disabled for bank 2"]
-            pub fn set_mesad_2(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "SRAM2 parity lock bit"]
+            pub fn set_spl(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "PVD lock enable bit"]
+            pub const fn pvdl(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "PVD lock enable bit"]
+            pub fn set_pvdl(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "ECC Lock"]
+            pub const fn eccl(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "ECC Lock"]
+            pub fn set_eccl(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "SRAM2 parity error flag"]
+            pub const fn spf(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SRAM2 parity error flag"]
+            pub fn set_spf(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
         }
-        impl Default for Ur8 {
-            fn default() -> Ur8 {
-                Ur8(0)
+        impl Default for Cfgr2 {
+            fn default() -> Cfgr2 {
+                Cfgr2(0)
             }
         }
-        #[doc = "SYSCFG compensation cell value register"]
+        #[doc = "SKR"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ccvr(pub u32);
-        impl Ccvr {
-            #[doc = "NMOS compensation value"]
-            pub const fn ncv(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x0f;
-                val as u8
-            }
-            #[doc = "NMOS compensation value"]
-            pub fn set_ncv(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
-            }
-            #[doc = "PMOS compensation value"]
-            pub const fn pcv(&self) -> u8 {
-                let val = (self.0 >> 4usize) & 0x0f;
+        pub struct Skr(pub u32);
+        impl Skr {
+            #[doc = "SRAM2 write protection key for software erase"]
+            pub const fn key(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
                 val as u8
             }
-            #[doc = "PMOS compensation value"]
-            pub fn set_pcv(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+            #[doc = "SRAM2 write protection key for software erase"]
+            pub fn set_key(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
             }
         }
-        impl Default for Ccvr {
-            fn default() -> Ccvr {
-                Ccvr(0)
+        impl Default for Skr {
+            fn default() -> Skr {
+                Skr(0)
             }
         }
-        #[doc = "SYSCFG user register 11"]
+        #[doc = "SCSR"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur11(pub u32);
-        impl Ur11 {
-            #[doc = "Secured area end address for bank 2"]
-            pub const fn sa_end_2(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x0fff;
-                val as u16
+        pub struct Scsr(pub u32);
+        impl Scsr {
+            #[doc = "SRAM2 Erase"]
+            pub const fn sram2er(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Secured area end address for bank 2"]
-            pub fn set_sa_end_2(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+            #[doc = "SRAM2 Erase"]
+            pub fn set_sram2er(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Independent Watchdog 1 mode"]
-            pub const fn iwdg1m(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
+            #[doc = "SRAM2 busy by erase operation"]
+            pub const fn sram2bsy(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Independent Watchdog 1 mode"]
-            pub fn set_iwdg1m(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "SRAM2 busy by erase operation"]
+            pub fn set_sram2bsy(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
         }
-        impl Default for Ur11 {
-            fn default() -> Ur11 {
-                Ur11(0)
+        impl Default for Scsr {
+            fn default() -> Scsr {
+                Scsr(0)
             }
         }
-        #[doc = "SYSCFG user register 9"]
+    }
+}
+pub mod sdmmc_v2 {
+    use crate::generic::*;
+    #[doc = "SDMMC"]
+    #[derive(Copy, Clone)]
+    pub struct Sdmmc(pub *mut u8);
+    unsafe impl Send for Sdmmc {}
+    unsafe impl Sync for Sdmmc {}
+    impl Sdmmc {
+        #[doc = "SDMMC power control register"]
+        pub fn power(self) -> Reg<regs::Power, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
+        pub fn clkcr(self) -> Reg<regs::Clkcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
+        pub fn argr(self) -> Reg<regs::Argr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."]
+        pub fn cmdr(self) -> Reg<regs::Cmdr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "SDMMC command response register"]
+        pub fn respcmdr(self) -> Reg<regs::Respcmdr, R> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
+        pub fn respr(self, n: usize) -> Reg<regs::Resp1r, R> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) }
+        }
+        #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
+        pub fn dtimer(self) -> Reg<regs::Dtimer, RW> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        }
+        #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
+        pub fn dlenr(self) -> Reg<regs::Dlenr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(40usize)) }
+        }
+        #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."]
+        pub fn dctrl(self) -> Reg<regs::Dctrl, RW> {
+            unsafe { Reg::from_ptr(self.0.add(44usize)) }
+        }
+        #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
+        pub fn dcntr(self) -> Reg<regs::Dcntr, R> {
+            unsafe { Reg::from_ptr(self.0.add(48usize)) }
+        }
+        #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
+        pub fn star(self) -> Reg<regs::Star, R> {
+            unsafe { Reg::from_ptr(self.0.add(52usize)) }
+        }
+        #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
+        pub fn icr(self) -> Reg<regs::Icr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(56usize)) }
+        }
+        #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."]
+        pub fn maskr(self) -> Reg<regs::Maskr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(60usize)) }
+        }
+        #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
+        pub fn acktimer(self) -> Reg<regs::Acktimer, RW> {
+            unsafe { Reg::from_ptr(self.0.add(64usize)) }
+        }
+        #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
+        pub fn idmactrlr(self) -> Reg<regs::Idmactrlr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(80usize)) }
+        }
+        #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
+        pub fn idmabsizer(self) -> Reg<regs::Idmabsizer, RW> {
+            unsafe { Reg::from_ptr(self.0.add(84usize)) }
+        }
+        #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
+        pub fn idmabase0r(self) -> Reg<regs::Idmabase0r, RW> {
+            unsafe { Reg::from_ptr(self.0.add(88usize)) }
+        }
+        #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
+        pub fn idmabase1r(self) -> Reg<regs::Idmabase1r, RW> {
+            unsafe { Reg::from_ptr(self.0.add(92usize)) }
+        }
+        #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
+        pub fn fifor(self) -> Reg<regs::Fifor, RW> {
+            unsafe { Reg::from_ptr(self.0.add(128usize)) }
+        }
+        #[doc = "SDMMC IP version register"]
+        pub fn ver(self) -> Reg<regs::Ver, R> {
+            unsafe { Reg::from_ptr(self.0.add(1012usize)) }
+        }
+        #[doc = "SDMMC IP identification register"]
+        pub fn id(self) -> Reg<regs::Id, R> {
+            unsafe { Reg::from_ptr(self.0.add(1016usize)) }
+        }
+    }
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur9(pub u32);
-        impl Ur9 {
-            #[doc = "Write protection for flash bank 2"]
-            pub const fn wrpn_2(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Write protection for flash bank 2"]
-            pub fn set_wrpn_2(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
-            }
-            #[doc = "Protected area start address for bank 2"]
-            pub const fn pa_beg_2(&self) -> u16 {
-                let val = (self.0 >> 16usize) & 0x0fff;
-                val as u16
+        pub struct Idmabase1r(pub u32);
+        impl Idmabase1r {
+            #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0]
+are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
+            pub const fn idmabase1(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "Protected area start address for bank 2"]
-            pub fn set_pa_beg_2(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
+            #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0]
+are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
+            pub fn set_idmabase1(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Ur9 {
-            fn default() -> Ur9 {
-                Ur9(0)
+        impl Default for Idmabase1r {
+            fn default() -> Idmabase1r {
+                Idmabase1r(0)
             }
         }
-        #[doc = "SYSCFG power control register"]
+        #[doc = "SDMMC command response register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pwrcr(pub u32);
-        impl Pwrcr {
-            #[doc = "Overdrive enable"]
-            pub const fn oden(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x0f;
+        pub struct Respcmdr(pub u32);
+        impl Respcmdr {
+            #[doc = "Response command index"]
+            pub const fn respcmd(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x3f;
                 val as u8
             }
-            #[doc = "Overdrive enable"]
-            pub fn set_oden(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+            #[doc = "Response command index"]
+            pub fn set_respcmd(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
             }
         }
-        impl Default for Pwrcr {
-            fn default() -> Pwrcr {
-                Pwrcr(0)
+        impl Default for Respcmdr {
+            fn default() -> Respcmdr {
+                Respcmdr(0)
             }
         }
-        #[doc = "SYSCFG user register 15"]
+        #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur15(pub u32);
-        impl Ur15 {
-            #[doc = "Freeze independent watchdog in Standby mode"]
-            pub const fn fziwdgstb(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
-                val != 0
+        pub struct Dcntr(pub u32);
+        impl Dcntr {
+            #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
+            pub const fn datacount(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0x01ff_ffff;
+                val as u32
             }
-            #[doc = "Freeze independent watchdog in Standby mode"]
-            pub fn set_fziwdgstb(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
+            pub fn set_datacount(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
             }
         }
-        impl Default for Ur15 {
-            fn default() -> Ur15 {
-                Ur15(0)
+        impl Default for Dcntr {
+            fn default() -> Dcntr {
+                Dcntr(0)
             }
         }
-        #[doc = "SYSCFG compensation cell code register"]
+        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cccr(pub u32);
-        impl Cccr {
-            #[doc = "NMOS compensation code"]
-            pub const fn ncc(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x0f;
-                val as u8
-            }
-            #[doc = "NMOS compensation code"]
-            pub fn set_ncc(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
-            }
-            #[doc = "PMOS compensation code"]
-            pub const fn pcc(&self) -> u8 {
-                let val = (self.0 >> 4usize) & 0x0f;
-                val as u8
+        pub struct Resp4r(pub u32);
+        impl Resp4r {
+            #[doc = "see Table404."]
+            pub const fn cardstatus4(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "PMOS compensation code"]
-            pub fn set_pcc(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+            #[doc = "see Table404."]
+            pub fn set_cardstatus4(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Cccr {
-            fn default() -> Cccr {
-                Cccr(0)
+        impl Default for Resp4r {
+            fn default() -> Resp4r {
+                Resp4r(0)
             }
         }
-        #[doc = "SYSCFG user register 2"]
+        #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur2(pub u32);
-        impl Ur2 {
-            #[doc = "BOR_LVL Brownout Reset Threshold Level"]
-            pub const fn borh(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x03;
-                val as u8
-            }
-            #[doc = "BOR_LVL Brownout Reset Threshold Level"]
-            pub fn set_borh(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
-            }
-            #[doc = "Boot Address 0"]
-            pub const fn boot_add0(&self) -> u16 {
-                let val = (self.0 >> 16usize) & 0xffff;
-                val as u16
+        pub struct Acktimer(pub u32);
+        impl Acktimer {
+            #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
+            pub const fn acktime(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0x01ff_ffff;
+                val as u32
             }
-            #[doc = "Boot Address 0"]
-            pub fn set_boot_add0(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+            #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
+            pub fn set_acktime(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
             }
         }
-        impl Default for Ur2 {
-            fn default() -> Ur2 {
-                Ur2(0)
+        impl Default for Acktimer {
+            fn default() -> Acktimer {
+                Acktimer(0)
             }
         }
-        #[doc = "SYSCFG user register 14"]
+        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur14(pub u32);
-        impl Ur14 {
-            #[doc = "D1 Stop Reset"]
-            pub const fn d1stprst(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
+        pub struct Resp2r(pub u32);
+        impl Resp2r {
+            #[doc = "see Table404."]
+            pub const fn cardstatus2(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "D1 Stop Reset"]
-            pub fn set_d1stprst(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "see Table404."]
+            pub fn set_cardstatus2(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Ur14 {
-            fn default() -> Ur14 {
-                Ur14(0)
+        impl Default for Resp2r {
+            fn default() -> Resp2r {
+                Resp2r(0)
             }
         }
-        #[doc = "SYSCFG user register 0"]
+        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur0(pub u32);
-        impl Ur0 {
-            #[doc = "Bank Swap"]
-            pub const fn bks(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Bank Swap"]
-            pub fn set_bks(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Readout protection"]
-            pub const fn rdp(&self) -> u8 {
-                let val = (self.0 >> 16usize) & 0xff;
-                val as u8
+        pub struct Resp1r(pub u32);
+        impl Resp1r {
+            #[doc = "see Table 432"]
+            pub const fn cardstatus1(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "Readout protection"]
-            pub fn set_rdp(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+            #[doc = "see Table 432"]
+            pub fn set_cardstatus1(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Ur0 {
-            fn default() -> Ur0 {
-                Ur0(0)
+        impl Default for Resp1r {
+            fn default() -> Resp1r {
+                Resp1r(0)
             }
         }
-        #[doc = "external interrupt configuration register 2"]
+        #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Exticr(pub u32);
-        impl Exticr {
-            #[doc = "EXTI x configuration (x = 4 to 7)"]
-            pub fn exti(&self, n: usize) -> u8 {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x0f;
-                val as u8
+        pub struct Idmabase0r(pub u32);
+        impl Idmabase0r {
+            #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0]
+are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
+            pub const fn idmabase0(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "EXTI x configuration (x = 4 to 7)"]
-            pub fn set_exti(&mut self, n: usize, val: u8) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
+            #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0]
+are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
+            pub fn set_idmabase0(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Exticr {
-            fn default() -> Exticr {
-                Exticr(0)
+        impl Default for Idmabase0r {
+            fn default() -> Idmabase0r {
+                Idmabase0r(0)
             }
         }
-        #[doc = "peripheral mode configuration register"]
+        #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pmcr(pub u32);
-        impl Pmcr {
-            #[doc = "I2C1 Fm+"]
-            pub const fn i2c1fmp(&self) -> bool {
+        pub struct Icr(pub u32);
+        impl Icr {
+            #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
+            pub const fn ccrcfailc(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "I2C1 Fm+"]
-            pub fn set_i2c1fmp(&mut self, val: bool) {
+            #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
+            pub fn set_ccrcfailc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "I2C2 Fm+"]
-            pub const fn i2c2fmp(&self) -> bool {
+            #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
+            pub const fn dcrcfailc(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "I2C2 Fm+"]
-            pub fn set_i2c2fmp(&mut self, val: bool) {
+            #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
+            pub fn set_dcrcfailc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "I2C3 Fm+"]
-            pub const fn i2c3fmp(&self) -> bool {
+            #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
+            pub const fn ctimeoutc(&self) -> bool {
                 let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "I2C3 Fm+"]
-            pub fn set_i2c3fmp(&mut self, val: bool) {
+            #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
+            pub fn set_ctimeoutc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "I2C4 Fm+"]
-            pub const fn i2c4fmp(&self) -> bool {
+            #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
+            pub const fn dtimeoutc(&self) -> bool {
                 let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "I2C4 Fm+"]
-            pub fn set_i2c4fmp(&mut self, val: bool) {
+            #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
+            pub fn set_dtimeoutc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-            #[doc = "PB(6) Fm+"]
-            pub const fn pb6fmp(&self) -> bool {
+            #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
+            pub const fn txunderrc(&self) -> bool {
                 let val = (self.0 >> 4usize) & 0x01;
                 val != 0
             }
-            #[doc = "PB(6) Fm+"]
-            pub fn set_pb6fmp(&mut self, val: bool) {
+            #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
+            pub fn set_txunderrc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "PB(7) Fast Mode Plus"]
-            pub const fn pb7fmp(&self) -> bool {
+            #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
+            pub const fn rxoverrc(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "PB(7) Fast Mode Plus"]
-            pub fn set_pb7fmp(&mut self, val: bool) {
+            #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
+            pub fn set_rxoverrc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "PB(8) Fast Mode Plus"]
-            pub const fn pb8fmp(&self) -> bool {
+            #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
+            pub const fn cmdrendc(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "PB(8) Fast Mode Plus"]
-            pub fn set_pb8fmp(&mut self, val: bool) {
+            #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
+            pub fn set_cmdrendc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "PB(9) Fm+"]
-            pub const fn pb9fmp(&self) -> bool {
+            #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
+            pub const fn cmdsentc(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "PB(9) Fm+"]
-            pub fn set_pb9fmp(&mut self, val: bool) {
+            #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
+            pub fn set_cmdsentc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Booster Enable"]
-            pub const fn booste(&self) -> bool {
+            #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
+            pub const fn dataendc(&self) -> bool {
                 let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "Booster Enable"]
-            pub fn set_booste(&mut self, val: bool) {
+            #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
+            pub fn set_dataendc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Analog switch supply voltage selection"]
-            pub const fn boostvddsel(&self) -> bool {
+            #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
+            pub const fn dholdc(&self) -> bool {
                 let val = (self.0 >> 9usize) & 0x01;
                 val != 0
             }
-            #[doc = "Analog switch supply voltage selection"]
-            pub fn set_boostvddsel(&mut self, val: bool) {
+            #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
+            pub fn set_dholdc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
             }
-            #[doc = "Ethernet PHY Interface Selection"]
-            pub const fn epis(&self) -> u8 {
-                let val = (self.0 >> 21usize) & 0x07;
-                val as u8
+            #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
+            pub const fn dbckendc(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
+                val != 0
             }
-            #[doc = "Ethernet PHY Interface Selection"]
-            pub fn set_epis(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize);
+            #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
+            pub fn set_dbckendc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
             }
-            #[doc = "PA0 Switch Open"]
-            pub const fn pa0so(&self) -> bool {
+            #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
+            pub const fn dabortc(&self) -> bool {
+                let val = (self.0 >> 11usize) & 0x01;
+                val != 0
+            }
+            #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
+            pub fn set_dabortc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+            }
+            #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
+            pub const fn busyd0endc(&self) -> bool {
+                let val = (self.0 >> 21usize) & 0x01;
+                val != 0
+            }
+            #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
+            pub fn set_busyd0endc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+            }
+            #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
+            pub const fn sdioitc(&self) -> bool {
+                let val = (self.0 >> 22usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
+            pub fn set_sdioitc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+            }
+            #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
+            pub const fn ackfailc(&self) -> bool {
+                let val = (self.0 >> 23usize) & 0x01;
+                val != 0
+            }
+            #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
+            pub fn set_ackfailc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+            }
+            #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
+            pub const fn acktimeoutc(&self) -> bool {
                 let val = (self.0 >> 24usize) & 0x01;
                 val != 0
             }
-            #[doc = "PA0 Switch Open"]
-            pub fn set_pa0so(&mut self, val: bool) {
+            #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
+            pub fn set_acktimeoutc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
             }
-            #[doc = "PA1 Switch Open"]
-            pub const fn pa1so(&self) -> bool {
+            #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
+            pub const fn vswendc(&self) -> bool {
                 let val = (self.0 >> 25usize) & 0x01;
                 val != 0
             }
-            #[doc = "PA1 Switch Open"]
-            pub fn set_pa1so(&mut self, val: bool) {
+            #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
+            pub fn set_vswendc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
             }
-            #[doc = "PC2 Switch Open"]
-            pub const fn pc2so(&self) -> bool {
+            #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
+            pub const fn ckstopc(&self) -> bool {
                 let val = (self.0 >> 26usize) & 0x01;
                 val != 0
             }
-            #[doc = "PC2 Switch Open"]
-            pub fn set_pc2so(&mut self, val: bool) {
+            #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
+            pub fn set_ckstopc(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
             }
-            #[doc = "PC3 Switch Open"]
-            pub const fn pc3so(&self) -> bool {
+            #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
+            pub const fn idmatec(&self) -> bool {
                 let val = (self.0 >> 27usize) & 0x01;
                 val != 0
             }
-            #[doc = "PC3 Switch Open"]
-            pub fn set_pc3so(&mut self, val: bool) {
+            #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
+            pub fn set_idmatec(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
             }
-        }
-        impl Default for Pmcr {
-            fn default() -> Pmcr {
-                Pmcr(0)
-            }
-        }
-        #[doc = "SYSCFG user register 5"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur5(pub u32);
-        impl Ur5 {
-            #[doc = "Mass erase secured area disabled for bank 1"]
-            pub const fn mesad_1(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
+            #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
+            pub const fn idmabtcc(&self) -> bool {
+                let val = (self.0 >> 28usize) & 0x01;
                 val != 0
             }
-            #[doc = "Mass erase secured area disabled for bank 1"]
-            pub fn set_mesad_1(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Write protection for flash bank 1"]
-            pub const fn wrpn_1(&self) -> u8 {
-                let val = (self.0 >> 16usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Write protection for flash bank 1"]
-            pub fn set_wrpn_1(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+            #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
+            pub fn set_idmabtcc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
             }
         }
-        impl Default for Ur5 {
-            fn default() -> Ur5 {
-                Ur5(0)
+        impl Default for Icr {
+            fn default() -> Icr {
+                Icr(0)
             }
         }
-        #[doc = "SYSCFG user register 7"]
+        #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur7(pub u32);
-        impl Ur7 {
-            #[doc = "Secured area start address for bank 1"]
-            pub const fn sa_beg_1(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x0fff;
+        pub struct Clkcr(pub u32);
+        impl Clkcr {
+            #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."]
+            pub const fn clkdiv(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x03ff;
                 val as u16
             }
-            #[doc = "Secured area start address for bank 1"]
-            pub fn set_sa_beg_1(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
-            }
-            #[doc = "Secured area end address for bank 1"]
-            pub const fn sa_end_1(&self) -> u16 {
-                let val = (self.0 >> 16usize) & 0x0fff;
-                val as u16
+            #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."]
+            pub fn set_clkdiv(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
             }
-            #[doc = "Secured area end address for bank 1"]
-            pub fn set_sa_end_1(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
+            #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
+            pub const fn pwrsav(&self) -> bool {
+                let val = (self.0 >> 12usize) & 0x01;
+                val != 0
             }
-        }
-        impl Default for Ur7 {
-            fn default() -> Ur7 {
-                Ur7(0)
+            #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
+            pub fn set_pwrsav(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
             }
-        }
-        #[doc = "SYSCFG user register 13"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur13(pub u32);
-        impl Ur13 {
-            #[doc = "Secured DTCM RAM Size"]
-            pub const fn sdrs(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x03;
+            #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
+            pub const fn widbus(&self) -> u8 {
+                let val = (self.0 >> 14usize) & 0x03;
                 val as u8
             }
-            #[doc = "Secured DTCM RAM Size"]
-            pub fn set_sdrs(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+            #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
+            pub fn set_widbus(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
             }
-            #[doc = "D1 Standby reset"]
-            pub const fn d1sbrst(&self) -> bool {
+            #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
+            pub const fn negedge(&self) -> bool {
                 let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "D1 Standby reset"]
-            pub fn set_d1sbrst(&mut self, val: bool) {
+            #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
+            pub fn set_negedge(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
-        }
-        impl Default for Ur13 {
-            fn default() -> Ur13 {
-                Ur13(0)
+            #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
+            pub const fn hwfc_en(&self) -> bool {
+                let val = (self.0 >> 17usize) & 0x01;
+                val != 0
             }
-        }
-        #[doc = "SYSCFG user register 4"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur4(pub u32);
-        impl Ur4 {
-            #[doc = "Mass Erase Protected Area Disabled for bank 1"]
-            pub const fn mepad_1(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
+            #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
+            pub fn set_hwfc_en(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+            }
+            #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
+            pub const fn ddr(&self) -> bool {
+                let val = (self.0 >> 18usize) & 0x01;
                 val != 0
             }
-            #[doc = "Mass Erase Protected Area Disabled for bank 1"]
-            pub fn set_mepad_1(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
+            pub fn set_ddr(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+            }
+            #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
+            pub const fn busspeed(&self) -> bool {
+                let val = (self.0 >> 19usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
+            pub fn set_busspeed(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+            }
+            #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
+            pub const fn selclkrx(&self) -> u8 {
+                let val = (self.0 >> 20usize) & 0x03;
+                val as u8
+            }
+            #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
+            pub fn set_selclkrx(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
             }
         }
-        impl Default for Ur4 {
-            fn default() -> Ur4 {
-                Ur4(0)
+        impl Default for Clkcr {
+            fn default() -> Clkcr {
+                Clkcr(0)
             }
         }
-        #[doc = "SYSCFG user register 10"]
+        #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur10(pub u32);
-        impl Ur10 {
-            #[doc = "Protected area end address for bank 2"]
-            pub const fn pa_end_2(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x0fff;
-                val as u16
+        pub struct Idmactrlr(pub u32);
+        impl Idmactrlr {
+            #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
+            pub const fn idmaen(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Protected area end address for bank 2"]
-            pub fn set_pa_end_2(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+            #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
+            pub fn set_idmaen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Secured area start address for bank 2"]
-            pub const fn sa_beg_2(&self) -> u16 {
-                let val = (self.0 >> 16usize) & 0x0fff;
-                val as u16
+            #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
+            pub const fn idmabmode(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
             }
-            #[doc = "Secured area start address for bank 2"]
-            pub fn set_sa_beg_2(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
+            #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
+            pub fn set_idmabmode(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
+            pub const fn idmabact(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
+            pub fn set_idmabact(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
         }
-        impl Default for Ur10 {
-            fn default() -> Ur10 {
-                Ur10(0)
+        impl Default for Idmactrlr {
+            fn default() -> Idmactrlr {
+                Idmactrlr(0)
             }
         }
-        #[doc = "SYSCFG user register 17"]
+        #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ur17(pub u32);
-        impl Ur17 {
-            #[doc = "I/O high speed / low voltage"]
-            pub const fn io_hslv(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
+        pub struct Dlenr(pub u32);
+        impl Dlenr {
+            #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
+            pub const fn datalength(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0x01ff_ffff;
+                val as u32
             }
-            #[doc = "I/O high speed / low voltage"]
-            pub fn set_io_hslv(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
+            pub fn set_datalength(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
             }
         }
-        impl Default for Ur17 {
-            fn default() -> Ur17 {
-                Ur17(0)
+        impl Default for Dlenr {
+            fn default() -> Dlenr {
+                Dlenr(0)
             }
         }
-        #[doc = "SYSCFG package register"]
+        #[doc = "SDMMC IP version register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pkgr(pub u32);
-        impl Pkgr {
-            #[doc = "Package"]
-            pub const fn pkg(&self) -> u8 {
+        pub struct Ver(pub u32);
+        impl Ver {
+            #[doc = "IP minor revision number."]
+            pub const fn minrev(&self) -> u8 {
                 let val = (self.0 >> 0usize) & 0x0f;
                 val as u8
             }
-            #[doc = "Package"]
-            pub fn set_pkg(&mut self, val: u8) {
+            #[doc = "IP minor revision number."]
+            pub fn set_minrev(&mut self, val: u8) {
                 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
             }
+            #[doc = "IP major revision number."]
+            pub const fn majrev(&self) -> u8 {
+                let val = (self.0 >> 4usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "IP major revision number."]
+            pub fn set_majrev(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+            }
         }
-        impl Default for Pkgr {
-            fn default() -> Pkgr {
-                Pkgr(0)
+        impl Default for Ver {
+            fn default() -> Ver {
+                Ver(0)
             }
         }
-        #[doc = "compensation cell control/status register"]
+        #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cccsr(pub u32);
-        impl Cccsr {
-            #[doc = "enable"]
-            pub const fn en(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
+        pub struct Argr(pub u32);
+        impl Argr {
+            #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
+            pub const fn cmdarg(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "enable"]
-            pub fn set_en(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
+            pub fn set_cmdarg(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
-            #[doc = "Code selection"]
-            pub const fn cs(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
+        }
+        impl Default for Argr {
+            fn default() -> Argr {
+                Argr(0)
             }
-            #[doc = "Code selection"]
-            pub fn set_cs(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+        }
+        #[doc = "SDMMC IP identification register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Id(pub u32);
+        impl Id {
+            #[doc = "SDMMC IP identification."]
+            pub const fn ip_id(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "Compensation cell ready flag"]
-            pub const fn ready(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
+            #[doc = "SDMMC IP identification."]
+            pub fn set_ip_id(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
-            #[doc = "Compensation cell ready flag"]
-            pub fn set_ready(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+        }
+        impl Default for Id {
+            fn default() -> Id {
+                Id(0)
             }
-            #[doc = "High-speed at low-voltage"]
-            pub const fn hslv(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
-                val != 0
+        }
+        #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Fifor(pub u32);
+        impl Fifor {
+            #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
+            pub const fn fifodata(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "High-speed at low-voltage"]
-            pub fn set_hslv(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
+            pub fn set_fifodata(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Cccsr {
-            fn default() -> Cccsr {
-                Cccsr(0)
+        impl Default for Fifor {
+            fn default() -> Fifor {
+                Fifor(0)
             }
         }
-    }
-}
-pub mod sdmmc_v2 {
-    use crate::generic::*;
-    #[doc = "SDMMC"]
-    #[derive(Copy, Clone)]
-    pub struct Sdmmc(pub *mut u8);
-    unsafe impl Send for Sdmmc {}
-    unsafe impl Sync for Sdmmc {}
-    impl Sdmmc {
-        #[doc = "SDMMC power control register"]
-        pub fn power(self) -> Reg<regs::Power, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
-        pub fn clkcr(self) -> Reg<regs::Clkcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
-        pub fn argr(self) -> Reg<regs::Argr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."]
-        pub fn cmdr(self) -> Reg<regs::Cmdr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "SDMMC command response register"]
-        pub fn respcmdr(self) -> Reg<regs::Respcmdr, R> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
-        pub fn respr(self, n: usize) -> Reg<regs::Resp1r, R> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) }
-        }
         #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
-        pub fn dtimer(self) -> Reg<regs::Dtimer, RW> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
-        }
-        #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
-        pub fn dlenr(self) -> Reg<regs::Dlenr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(40usize)) }
-        }
-        #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."]
-        pub fn dctrl(self) -> Reg<regs::Dctrl, RW> {
-            unsafe { Reg::from_ptr(self.0.add(44usize)) }
-        }
-        #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
-        pub fn dcntr(self) -> Reg<regs::Dcntr, R> {
-            unsafe { Reg::from_ptr(self.0.add(48usize)) }
-        }
-        #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
-        pub fn star(self) -> Reg<regs::Star, R> {
-            unsafe { Reg::from_ptr(self.0.add(52usize)) }
-        }
-        #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
-        pub fn icr(self) -> Reg<regs::Icr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(56usize)) }
-        }
-        #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."]
-        pub fn maskr(self) -> Reg<regs::Maskr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(60usize)) }
-        }
-        #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
-        pub fn acktimer(self) -> Reg<regs::Acktimer, RW> {
-            unsafe { Reg::from_ptr(self.0.add(64usize)) }
-        }
-        #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
-        pub fn idmactrlr(self) -> Reg<regs::Idmactrlr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(80usize)) }
-        }
-        #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
-        pub fn idmabsizer(self) -> Reg<regs::Idmabsizer, RW> {
-            unsafe { Reg::from_ptr(self.0.add(84usize)) }
-        }
-        #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
-        pub fn idmabase0r(self) -> Reg<regs::Idmabase0r, RW> {
-            unsafe { Reg::from_ptr(self.0.add(88usize)) }
-        }
-        #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
-        pub fn idmabase1r(self) -> Reg<regs::Idmabase1r, RW> {
-            unsafe { Reg::from_ptr(self.0.add(92usize)) }
-        }
-        #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
-        pub fn fifor(self) -> Reg<regs::Fifor, RW> {
-            unsafe { Reg::from_ptr(self.0.add(128usize)) }
-        }
-        #[doc = "SDMMC IP version register"]
-        pub fn ver(self) -> Reg<regs::Ver, R> {
-            unsafe { Reg::from_ptr(self.0.add(1012usize)) }
-        }
-        #[doc = "SDMMC IP identification register"]
-        pub fn id(self) -> Reg<regs::Id, R> {
-            unsafe { Reg::from_ptr(self.0.add(1016usize)) }
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Resp4r(pub u32);
-        impl Resp4r {
-            #[doc = "see Table404."]
-            pub const fn cardstatus4(&self) -> u32 {
+        pub struct Dtimer(pub u32);
+        impl Dtimer {
+            #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
+            pub const fn datatime(&self) -> u32 {
                 let val = (self.0 >> 0usize) & 0xffff_ffff;
                 val as u32
             }
-            #[doc = "see Table404."]
-            pub fn set_cardstatus4(&mut self, val: u32) {
+            #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
+            pub fn set_datatime(&mut self, val: u32) {
                 self.0 =
                     (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Resp4r {
-            fn default() -> Resp4r {
-                Resp4r(0)
+        impl Default for Dtimer {
+            fn default() -> Dtimer {
+                Dtimer(0)
             }
         }
         #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
@@ -1300,132 +1366,6 @@ pub mod sdmmc_v2 {
                 Power(0)
             }
         }
-        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Resp1r(pub u32);
-        impl Resp1r {
-            #[doc = "see Table 432"]
-            pub const fn cardstatus1(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "see Table 432"]
-            pub fn set_cardstatus1(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Resp1r {
-            fn default() -> Resp1r {
-                Resp1r(0)
-            }
-        }
-        #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Idmabase0r(pub u32);
-        impl Idmabase0r {
-            #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0]
-are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
-            pub const fn idmabase0(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0]
-are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
-            pub fn set_idmabase0(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Idmabase0r {
-            fn default() -> Idmabase0r {
-                Idmabase0r(0)
-            }
-        }
-        #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dcntr(pub u32);
-        impl Dcntr {
-            #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
-            pub const fn datacount(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0x01ff_ffff;
-                val as u32
-            }
-            #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
-            pub fn set_datacount(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
-            }
-        }
-        impl Default for Dcntr {
-            fn default() -> Dcntr {
-                Dcntr(0)
-            }
-        }
-        #[doc = "SDMMC command response register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Respcmdr(pub u32);
-        impl Respcmdr {
-            #[doc = "Response command index"]
-            pub const fn respcmd(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x3f;
-                val as u8
-            }
-            #[doc = "Response command index"]
-            pub fn set_respcmd(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
-            }
-        }
-        impl Default for Respcmdr {
-            fn default() -> Respcmdr {
-                Respcmdr(0)
-            }
-        }
-        #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Idmabsizer(pub u32);
-        impl Idmabsizer {
-            #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
-            pub const fn idmabndt(&self) -> u8 {
-                let val = (self.0 >> 5usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
-            pub fn set_idmabndt(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize);
-            }
-        }
-        impl Default for Idmabsizer {
-            fn default() -> Idmabsizer {
-                Idmabsizer(0)
-            }
-        }
-        #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Argr(pub u32);
-        impl Argr {
-            #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
-            pub const fn cmdarg(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
-            pub fn set_cmdarg(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Argr {
-            fn default() -> Argr {
-                Argr(0)
-            }
-        }
         #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -1536,50 +1476,6 @@ are always 0 and read only). This register can be written by firmware when DPSM
                 Cmdr(0)
             }
         }
-        #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Idmabase1r(pub u32);
-        impl Idmabase1r {
-            #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0]
-are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
-            pub const fn idmabase1(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0]
-are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
-            pub fn set_idmabase1(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Idmabase1r {
-            fn default() -> Idmabase1r {
-                Idmabase1r(0)
-            }
-        }
-        #[doc = "SDMMC IP identification register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Id(pub u32);
-        impl Id {
-            #[doc = "SDMMC IP identification."]
-            pub const fn ip_id(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "SDMMC IP identification."]
-            pub fn set_ip_id(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Id {
-            fn default() -> Id {
-                Id(0)
-            }
-        }
         #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -1681,139 +1577,6 @@ are always 0 and read only). This register can be written by firmware when DPSM
                 Dctrl(0)
             }
         }
-        #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dlenr(pub u32);
-        impl Dlenr {
-            #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
-            pub const fn datalength(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0x01ff_ffff;
-                val as u32
-            }
-            #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
-            pub fn set_datalength(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
-            }
-        }
-        impl Default for Dlenr {
-            fn default() -> Dlenr {
-                Dlenr(0)
-            }
-        }
-        #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Clkcr(pub u32);
-        impl Clkcr {
-            #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."]
-            pub const fn clkdiv(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x03ff;
-                val as u16
-            }
-            #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."]
-            pub fn set_clkdiv(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
-            }
-            #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
-            pub const fn pwrsav(&self) -> bool {
-                let val = (self.0 >> 12usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
-            pub fn set_pwrsav(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
-            }
-            #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
-            pub const fn widbus(&self) -> u8 {
-                let val = (self.0 >> 14usize) & 0x03;
-                val as u8
-            }
-            #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
-            pub fn set_widbus(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
-            }
-            #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
-            pub const fn negedge(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
-                val != 0
-            }
-            #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
-            pub fn set_negedge(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
-            }
-            #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
-            pub const fn hwfc_en(&self) -> bool {
-                let val = (self.0 >> 17usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
-            pub fn set_hwfc_en(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
-            }
-            #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
-            pub const fn ddr(&self) -> bool {
-                let val = (self.0 >> 18usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
-            pub fn set_ddr(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
-            }
-            #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
-            pub const fn busspeed(&self) -> bool {
-                let val = (self.0 >> 19usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
-            pub fn set_busspeed(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
-            }
-            #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
-            pub const fn selclkrx(&self) -> u8 {
-                let val = (self.0 >> 20usize) & 0x03;
-                val as u8
-            }
-            #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
-            pub fn set_selclkrx(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
-            }
-        }
-        impl Default for Clkcr {
-            fn default() -> Clkcr {
-                Clkcr(0)
-            }
-        }
-        #[doc = "SDMMC IP version register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ver(pub u32);
-        impl Ver {
-            #[doc = "IP minor revision number."]
-            pub const fn minrev(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x0f;
-                val as u8
-            }
-            #[doc = "IP minor revision number."]
-            pub fn set_minrev(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
-            }
-            #[doc = "IP major revision number."]
-            pub const fn majrev(&self) -> u8 {
-                let val = (self.0 >> 4usize) & 0x0f;
-                val as u8
-            }
-            #[doc = "IP major revision number."]
-            pub fn set_majrev(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
-            }
-        }
-        impl Default for Ver {
-            fn default() -> Ver {
-                Ver(0)
-            }
-        }
         #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -1835,27 +1598,6 @@ are always 0 and read only). This register can be written by firmware when DPSM
                 Resp3r(0)
             }
         }
-        #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Acktimer(pub u32);
-        impl Acktimer {
-            #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
-            pub const fn acktime(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0x01ff_ffff;
-                val as u32
-            }
-            #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
-            pub fn set_acktime(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
-            }
-        }
-        impl Default for Acktimer {
-            fn default() -> Acktimer {
-                Acktimer(0)
-            }
-        }
         #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -2074,2511 +1816,751 @@ are always 0 and read only). This register can be written by firmware when DPSM
                 Maskr(0)
             }
         }
-        #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Fifor(pub u32);
-        impl Fifor {
-            #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
-            pub const fn fifodata(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
-            pub fn set_fifodata(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Fifor {
-            fn default() -> Fifor {
-                Fifor(0)
-            }
-        }
-        #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Resp2r(pub u32);
-        impl Resp2r {
-            #[doc = "see Table404."]
-            pub const fn cardstatus2(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "see Table404."]
-            pub fn set_cardstatus2(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Resp2r {
-            fn default() -> Resp2r {
-                Resp2r(0)
-            }
-        }
-        #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Idmactrlr(pub u32);
-        impl Idmactrlr {
-            #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
-            pub const fn idmaen(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
-            pub fn set_idmaen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
-            pub const fn idmabmode(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
-            pub fn set_idmabmode(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
-            pub const fn idmabact(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
-            pub fn set_idmabact(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-        }
-        impl Default for Idmactrlr {
-            fn default() -> Idmactrlr {
-                Idmactrlr(0)
-            }
-        }
-        #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Icr(pub u32);
-        impl Icr {
-            #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
-            pub const fn ccrcfailc(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
-            pub fn set_ccrcfailc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
-            pub const fn dcrcfailc(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
-            pub fn set_dcrcfailc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
-            pub const fn ctimeoutc(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
-            pub fn set_ctimeoutc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
-            pub const fn dtimeoutc(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
-            pub fn set_dtimeoutc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
-            }
-            #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
-            pub const fn txunderrc(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
-                val != 0
-            }
-            #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
-            pub fn set_txunderrc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
-            }
-            #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
-            pub const fn rxoverrc(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
-            pub fn set_rxoverrc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
-            pub const fn cmdrendc(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
-            pub fn set_cmdrendc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
-            pub const fn cmdsentc(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
-            pub fn set_cmdsentc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
-            }
-            #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
-            pub const fn dataendc(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
-            pub fn set_dataendc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-            #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
-            pub const fn dholdc(&self) -> bool {
-                let val = (self.0 >> 9usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
-            pub fn set_dholdc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
-            }
-            #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
-            pub const fn dbckendc(&self) -> bool {
-                let val = (self.0 >> 10usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
-            pub fn set_dbckendc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
-            }
-            #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
-            pub const fn dabortc(&self) -> bool {
-                let val = (self.0 >> 11usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
-            pub fn set_dabortc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
-            }
-            #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
-            pub const fn busyd0endc(&self) -> bool {
-                let val = (self.0 >> 21usize) & 0x01;
-                val != 0
-            }
-            #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
-            pub fn set_busyd0endc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
-            }
-            #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
-            pub const fn sdioitc(&self) -> bool {
-                let val = (self.0 >> 22usize) & 0x01;
-                val != 0
-            }
-            #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
-            pub fn set_sdioitc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
-            }
-            #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
-            pub const fn ackfailc(&self) -> bool {
-                let val = (self.0 >> 23usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
-            pub fn set_ackfailc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
-            }
-            #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
-            pub const fn acktimeoutc(&self) -> bool {
-                let val = (self.0 >> 24usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
-            pub fn set_acktimeoutc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
-            }
-            #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
-            pub const fn vswendc(&self) -> bool {
-                let val = (self.0 >> 25usize) & 0x01;
-                val != 0
-            }
-            #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
-            pub fn set_vswendc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
-            }
-            #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
-            pub const fn ckstopc(&self) -> bool {
-                let val = (self.0 >> 26usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
-            pub fn set_ckstopc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
-            }
-            #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
-            pub const fn idmatec(&self) -> bool {
-                let val = (self.0 >> 27usize) & 0x01;
-                val != 0
-            }
-            #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
-            pub fn set_idmatec(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
-            }
-            #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
-            pub const fn idmabtcc(&self) -> bool {
-                let val = (self.0 >> 28usize) & 0x01;
-                val != 0
-            }
-            #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
-            pub fn set_idmabtcc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
-            }
-        }
-        impl Default for Icr {
-            fn default() -> Icr {
-                Icr(0)
-            }
-        }
-        #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dtimer(pub u32);
-        impl Dtimer {
-            #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
-            pub const fn datatime(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
-            pub fn set_datatime(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Dtimer {
-            fn default() -> Dtimer {
-                Dtimer(0)
-            }
-        }
-    }
-}
-pub mod syscfg_f4 {
-    use crate::generic::*;
-    #[doc = "System configuration controller"]
-    #[derive(Copy, Clone)]
-    pub struct Syscfg(pub *mut u8);
-    unsafe impl Send for Syscfg {}
-    unsafe impl Sync for Syscfg {}
-    impl Syscfg {
-        #[doc = "memory remap register"]
-        pub fn memrm(self) -> Reg<regs::Memrm, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "peripheral mode configuration register"]
-        pub fn pmc(self) -> Reg<regs::Pmc, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "external interrupt configuration register"]
-        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
-        }
-        #[doc = "Compensation cell control register"]
-        pub fn cmpcr(self) -> Reg<regs::Cmpcr, R> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "peripheral mode configuration register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pmc(pub u32);
-        impl Pmc {
-            #[doc = "ADC1DC2"]
-            pub const fn adc1dc2(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ADC1DC2"]
-            pub fn set_adc1dc2(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
-            }
-            #[doc = "ADC2DC2"]
-            pub const fn adc2dc2(&self) -> bool {
-                let val = (self.0 >> 17usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ADC2DC2"]
-            pub fn set_adc2dc2(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
-            }
-            #[doc = "ADC3DC2"]
-            pub const fn adc3dc2(&self) -> bool {
-                let val = (self.0 >> 18usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ADC3DC2"]
-            pub fn set_adc3dc2(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
-            }
-            #[doc = "Ethernet PHY interface selection"]
-            pub const fn mii_rmii_sel(&self) -> bool {
-                let val = (self.0 >> 23usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Ethernet PHY interface selection"]
-            pub fn set_mii_rmii_sel(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
-            }
-        }
-        impl Default for Pmc {
-            fn default() -> Pmc {
-                Pmc(0)
-            }
-        }
-        #[doc = "memory remap register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Memrm(pub u32);
-        impl Memrm {
-            #[doc = "Memory mapping selection"]
-            pub const fn mem_mode(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x07;
-                val as u8
-            }
-            #[doc = "Memory mapping selection"]
-            pub fn set_mem_mode(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
-            }
-            #[doc = "Flash bank mode selection"]
-            pub const fn fb_mode(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Flash bank mode selection"]
-            pub fn set_fb_mode(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-            #[doc = "FMC memory mapping swap"]
-            pub const fn swp_fmc(&self) -> u8 {
-                let val = (self.0 >> 10usize) & 0x03;
-                val as u8
-            }
-            #[doc = "FMC memory mapping swap"]
-            pub fn set_swp_fmc(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
-            }
-        }
-        impl Default for Memrm {
-            fn default() -> Memrm {
-                Memrm(0)
-            }
-        }
-        #[doc = "Compensation cell control register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cmpcr(pub u32);
-        impl Cmpcr {
-            #[doc = "Compensation cell power-down"]
-            pub const fn cmp_pd(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Compensation cell power-down"]
-            pub fn set_cmp_pd(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "READY"]
-            pub const fn ready(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "READY"]
-            pub fn set_ready(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-        }
-        impl Default for Cmpcr {
-            fn default() -> Cmpcr {
-                Cmpcr(0)
-            }
-        }
-        #[doc = "external interrupt configuration register"]
+        #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Exticr(pub u32);
-        impl Exticr {
-            #[doc = "EXTI x configuration"]
-            pub fn exti(&self, n: usize) -> u8 {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x0f;
+        pub struct Idmabsizer(pub u32);
+        impl Idmabsizer {
+            #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
+            pub const fn idmabndt(&self) -> u8 {
+                let val = (self.0 >> 5usize) & 0xff;
                 val as u8
             }
-            #[doc = "EXTI x configuration"]
-            pub fn set_exti(&mut self, n: usize, val: u8) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
+            #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
+            pub fn set_idmabndt(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize);
             }
         }
-        impl Default for Exticr {
-            fn default() -> Exticr {
-                Exticr(0)
+        impl Default for Idmabsizer {
+            fn default() -> Idmabsizer {
+                Idmabsizer(0)
             }
         }
     }
 }
-pub mod timer_v1 {
+pub mod spi_v1 {
     use crate::generic::*;
-    #[doc = "Advanced-timers"]
-    #[derive(Copy, Clone)]
-    pub struct TimAdv(pub *mut u8);
-    unsafe impl Send for TimAdv {}
-    unsafe impl Sync for TimAdv {}
-    impl TimAdv {
-        #[doc = "control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2Adv, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "slave mode control register"]
-        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "DMA/Interrupt enable register"]
-        pub fn dier(self) -> Reg<regs::DierAdv, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::SrAdv, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "event generation register"]
-        pub fn egr(self) -> Reg<regs::EgrAdv, W> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-        #[doc = "capture/compare mode register 1 (input mode)"]
-        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
-        }
-        #[doc = "capture/compare mode register 1 (output mode)"]
-        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
-        }
-        #[doc = "capture/compare enable register"]
-        pub fn ccer(self) -> Reg<regs::CcerAdv, RW> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
-        }
-        #[doc = "counter"]
-        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
-        }
-        #[doc = "prescaler"]
-        pub fn psc(self) -> Reg<regs::Psc, RW> {
-            unsafe { Reg::from_ptr(self.0.add(40usize)) }
-        }
-        #[doc = "auto-reload register"]
-        pub fn arr(self) -> Reg<regs::Arr16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(44usize)) }
-        }
-        #[doc = "repetition counter register"]
-        pub fn rcr(self) -> Reg<regs::Rcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(48usize)) }
-        }
-        #[doc = "capture/compare register"]
-        pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
-        }
-        #[doc = "break and dead-time register"]
-        pub fn bdtr(self) -> Reg<regs::Bdtr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(68usize)) }
-        }
-        #[doc = "DMA control register"]
-        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(72usize)) }
-        }
-        #[doc = "DMA address for full transfer"]
-        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
-            unsafe { Reg::from_ptr(self.0.add(76usize)) }
-        }
-    }
-    #[doc = "General purpose 16-bit timer"]
-    #[derive(Copy, Clone)]
-    pub struct TimGp16(pub *mut u8);
-    unsafe impl Send for TimGp16 {}
-    unsafe impl Sync for TimGp16 {}
-    impl TimGp16 {
-        #[doc = "control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2Gp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "slave mode control register"]
-        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "DMA/Interrupt enable register"]
-        pub fn dier(self) -> Reg<regs::DierGp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::SrGp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "event generation register"]
-        pub fn egr(self) -> Reg<regs::EgrGp, W> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-        #[doc = "capture/compare mode register 1 (input mode)"]
-        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
-        }
-        #[doc = "capture/compare mode register 1 (output mode)"]
-        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
-        }
-        #[doc = "capture/compare enable register"]
-        pub fn ccer(self) -> Reg<regs::CcerGp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
-        }
-        #[doc = "counter"]
-        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
-        }
-        #[doc = "prescaler"]
-        pub fn psc(self) -> Reg<regs::Psc, RW> {
-            unsafe { Reg::from_ptr(self.0.add(40usize)) }
-        }
-        #[doc = "auto-reload register"]
-        pub fn arr(self) -> Reg<regs::Arr16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(44usize)) }
-        }
-        #[doc = "capture/compare register"]
-        pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
-        }
-        #[doc = "DMA control register"]
-        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(72usize)) }
-        }
-        #[doc = "DMA address for full transfer"]
-        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
-            unsafe { Reg::from_ptr(self.0.add(76usize)) }
-        }
-    }
-    #[doc = "Basic timer"]
+    #[doc = "Serial peripheral interface"]
     #[derive(Copy, Clone)]
-    pub struct TimBasic(pub *mut u8);
-    unsafe impl Send for TimBasic {}
-    unsafe impl Sync for TimBasic {}
-    impl TimBasic {
+    pub struct Spi(pub *mut u8);
+    unsafe impl Send for Spi {}
+    unsafe impl Sync for Spi {}
+    impl Spi {
         #[doc = "control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1Basic, RW> {
+        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
         #[doc = "control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2Basic, RW> {
+        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "DMA/Interrupt enable register"]
-        pub fn dier(self) -> Reg<regs::DierBasic, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
         #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::SrBasic, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "event generation register"]
-        pub fn egr(self) -> Reg<regs::EgrBasic, W> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-        #[doc = "counter"]
-        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
-        }
-        #[doc = "prescaler"]
-        pub fn psc(self) -> Reg<regs::Psc, RW> {
-            unsafe { Reg::from_ptr(self.0.add(40usize)) }
-        }
-        #[doc = "auto-reload register"]
-        pub fn arr(self) -> Reg<regs::Arr16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(44usize)) }
-        }
-    }
-    #[doc = "General purpose 32-bit timer"]
-    #[derive(Copy, Clone)]
-    pub struct TimGp32(pub *mut u8);
-    unsafe impl Send for TimGp32 {}
-    unsafe impl Sync for TimGp32 {}
-    impl TimGp32 {
-        #[doc = "control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2Gp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "slave mode control register"]
-        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
+        pub fn sr(self) -> Reg<regs::Sr, RW> {
             unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
-        #[doc = "DMA/Interrupt enable register"]
-        pub fn dier(self) -> Reg<regs::DierGp, RW> {
+        #[doc = "data register"]
+        pub fn dr(self) -> Reg<regs::Dr, RW> {
             unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::SrGp, RW> {
+        #[doc = "CRC polynomial register"]
+        pub fn crcpr(self) -> Reg<regs::Crcpr, RW> {
             unsafe { Reg::from_ptr(self.0.add(16usize)) }
         }
-        #[doc = "event generation register"]
-        pub fn egr(self) -> Reg<regs::EgrGp, W> {
+        #[doc = "RX CRC register"]
+        pub fn rxcrcr(self) -> Reg<regs::Rxcrcr, R> {
             unsafe { Reg::from_ptr(self.0.add(20usize)) }
         }
-        #[doc = "capture/compare mode register 1 (input mode)"]
-        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
-        }
-        #[doc = "capture/compare mode register 1 (output mode)"]
-        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
-        }
-        #[doc = "capture/compare enable register"]
-        pub fn ccer(self) -> Reg<regs::CcerGp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
-        }
-        #[doc = "counter"]
-        pub fn cnt(self) -> Reg<regs::Cnt32, RW> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
-        }
-        #[doc = "prescaler"]
-        pub fn psc(self) -> Reg<regs::Psc, RW> {
-            unsafe { Reg::from_ptr(self.0.add(40usize)) }
-        }
-        #[doc = "auto-reload register"]
-        pub fn arr(self) -> Reg<regs::Arr32, RW> {
-            unsafe { Reg::from_ptr(self.0.add(44usize)) }
-        }
-        #[doc = "capture/compare register"]
-        pub fn ccr(self, n: usize) -> Reg<regs::Ccr32, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
-        }
-        #[doc = "DMA control register"]
-        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(72usize)) }
-        }
-        #[doc = "DMA address for full transfer"]
-        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
-            unsafe { Reg::from_ptr(self.0.add(76usize)) }
+        #[doc = "TX CRC register"]
+        pub fn txcrcr(self) -> Reg<regs::Txcrcr, R> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
         }
     }
     pub mod vals {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ocpe(pub u8);
-        impl Ocpe {
-            #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Msm(pub u8);
-        impl Msm {
-            #[doc = "No action"]
-            pub const NOSYNC: Self = Self(0);
-            #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
-            pub const SYNC: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ocm(pub u8);
-        impl Ocm {
-            #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
-            pub const FROZEN: Self = Self(0);
-            #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
-            pub const ACTIVEONMATCH: Self = Self(0x01);
-            #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
-            pub const INACTIVEONMATCH: Self = Self(0x02);
-            #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
-            pub const TOGGLE: Self = Self(0x03);
-            #[doc = "OCyREF is forced low"]
-            pub const FORCEINACTIVE: Self = Self(0x04);
-            #[doc = "OCyREF is forced high"]
-            pub const FORCEACTIVE: Self = Self(0x05);
-            #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
-            pub const PWMMODE1: Self = Self(0x06);
-            #[doc = "Inversely to PwmMode1"]
-            pub const PWMMODE2: Self = Self(0x07);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mms(pub u8);
-        impl Mms {
-            #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
-            pub const RESET: Self = Self(0);
-            #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
-            pub const ENABLE: Self = Self(0x01);
-            #[doc = "The update event is selected as trigger output"]
-            pub const UPDATE: Self = Self(0x02);
-            #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
-            pub const COMPAREPULSE: Self = Self(0x03);
-            #[doc = "OC1REF signal is used as trigger output"]
-            pub const COMPAREOC1: Self = Self(0x04);
-            #[doc = "OC2REF signal is used as trigger output"]
-            pub const COMPAREOC2: Self = Self(0x05);
-            #[doc = "OC3REF signal is used as trigger output"]
-            pub const COMPAREOC3: Self = Self(0x06);
-            #[doc = "OC4REF signal is used as trigger output"]
-            pub const COMPAREOC4: Self = Self(0x07);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Arpe(pub u8);
-        impl Arpe {
-            #[doc = "TIMx_APRR register is not buffered"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "TIMx_APRR register is buffered"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct CcmrOutputCcs(pub u8);
-        impl CcmrOutputCcs {
-            #[doc = "CCx channel is configured as output"]
-            pub const OUTPUT: Self = Self(0);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ckd(pub u8);
-        impl Ckd {
-            #[doc = "t_DTS = t_CK_INT"]
-            pub const DIV1: Self = Self(0);
-            #[doc = "t_DTS = 2 × t_CK_INT"]
-            pub const DIV2: Self = Self(0x01);
-            #[doc = "t_DTS = 4 × t_CK_INT"]
-            pub const DIV4: Self = Self(0x02);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Urs(pub u8);
-        impl Urs {
-            #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
-            pub const ANYEVENT: Self = Self(0);
-            #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
-            pub const COUNTERONLY: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Etps(pub u8);
-        impl Etps {
-            #[doc = "Prescaler OFF"]
-            pub const DIV1: Self = Self(0);
-            #[doc = "ETRP frequency divided by 2"]
-            pub const DIV2: Self = Self(0x01);
-            #[doc = "ETRP frequency divided by 4"]
-            pub const DIV4: Self = Self(0x02);
-            #[doc = "ETRP frequency divided by 8"]
-            pub const DIV8: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ece(pub u8);
-        impl Ece {
-            #[doc = "External clock mode 2 disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dir(pub u8);
-        impl Dir {
-            #[doc = "Counter used as upcounter"]
-            pub const UP: Self = Self(0);
-            #[doc = "Counter used as downcounter"]
-            pub const DOWN: Self = Self(0x01);
+        pub struct Bidimode(pub u8);
+        impl Bidimode {
+            #[doc = "2-line unidirectional data mode selected"]
+            pub const UNIDIRECTIONAL: Self = Self(0);
+            #[doc = "1-line bidirectional data mode selected"]
+            pub const BIDIRECTIONAL: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Sms(pub u8);
-        impl Sms {
-            #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
-            pub const ENCODER_MODE_1: Self = Self(0x01);
-            #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
-            pub const ENCODER_MODE_2: Self = Self(0x02);
-            #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
-            pub const ENCODER_MODE_3: Self = Self(0x03);
-            #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
-            pub const RESET_MODE: Self = Self(0x04);
-            #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
-            pub const GATED_MODE: Self = Self(0x05);
-            #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
-            pub const TRIGGER_MODE: Self = Self(0x06);
-            #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
-            pub const EXT_CLOCK_MODE: Self = Self(0x07);
+        pub struct Cpha(pub u8);
+        impl Cpha {
+            #[doc = "The first clock transition is the first data capture edge"]
+            pub const FIRSTEDGE: Self = Self(0);
+            #[doc = "The second clock transition is the first data capture edge"]
+            pub const SECONDEDGE: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ossi(pub u8);
-        impl Ossi {
-            #[doc = "When inactive, OC/OCN outputs are disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "When inactive, OC/OCN outputs are forced to idle level"]
-            pub const IDLELEVEL: Self = Self(0x01);
+        pub struct Frf(pub u8);
+        impl Frf {
+            #[doc = "SPI Motorola mode"]
+            pub const MOTOROLA: Self = Self(0);
+            #[doc = "SPI TI mode"]
+            pub const TI: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Etp(pub u8);
-        impl Etp {
-            #[doc = "ETR is noninverted, active at high level or rising edge"]
-            pub const NOTINVERTED: Self = Self(0);
-            #[doc = "ETR is inverted, active at low level or falling edge"]
-            pub const INVERTED: Self = Self(0x01);
+        pub struct Iscfg(pub u8);
+        impl Iscfg {
+            #[doc = "Slave - transmit"]
+            pub const SLAVETX: Self = Self(0);
+            #[doc = "Slave - receive"]
+            pub const SLAVERX: Self = Self(0x01);
+            #[doc = "Master - transmit"]
+            pub const MASTERTX: Self = Self(0x02);
+            #[doc = "Master - receive"]
+            pub const MASTERRX: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ts(pub u8);
-        impl Ts {
-            #[doc = "Internal Trigger 0 (ITR0)"]
-            pub const ITR0: Self = Self(0);
-            #[doc = "Internal Trigger 1 (ITR1)"]
-            pub const ITR1: Self = Self(0x01);
-            #[doc = "Internal Trigger 2 (ITR2)"]
-            pub const ITR2: Self = Self(0x02);
-            #[doc = "TI1 Edge Detector (TI1F_ED)"]
-            pub const TI1F_ED: Self = Self(0x04);
-            #[doc = "Filtered Timer Input 1 (TI1FP1)"]
-            pub const TI1FP1: Self = Self(0x05);
-            #[doc = "Filtered Timer Input 2 (TI2FP2)"]
-            pub const TI2FP2: Self = Self(0x06);
-            #[doc = "External Trigger input (ETRF)"]
-            pub const ETRF: Self = Self(0x07);
+        pub struct Rxonly(pub u8);
+        impl Rxonly {
+            #[doc = "Full duplex (Transmit and receive)"]
+            pub const FULLDUPLEX: Self = Self(0);
+            #[doc = "Output disabled (Receive-only mode)"]
+            pub const OUTPUTDISABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ccds(pub u8);
-        impl Ccds {
-            #[doc = "CCx DMA request sent when CCx event occurs"]
-            pub const ONCOMPARE: Self = Self(0);
-            #[doc = "CCx DMA request sent when update event occurs"]
-            pub const ONUPDATE: Self = Self(0x01);
+        pub struct Bidioe(pub u8);
+        impl Bidioe {
+            #[doc = "Output disabled (receive-only mode)"]
+            pub const OUTPUTDISABLED: Self = Self(0);
+            #[doc = "Output enabled (transmit-only mode)"]
+            pub const OUTPUTENABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cms(pub u8);
-        impl Cms {
-            #[doc = "The counter counts up or down depending on the direction bit"]
-            pub const EDGEALIGNED: Self = Self(0);
-            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
-            pub const CENTERALIGNED1: Self = Self(0x01);
-            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
-            pub const CENTERALIGNED2: Self = Self(0x02);
-            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
-            pub const CENTERALIGNED3: Self = Self(0x03);
+        pub struct Br(pub u8);
+        impl Br {
+            #[doc = "f_PCLK / 2"]
+            pub const DIV2: Self = Self(0);
+            #[doc = "f_PCLK / 4"]
+            pub const DIV4: Self = Self(0x01);
+            #[doc = "f_PCLK / 8"]
+            pub const DIV8: Self = Self(0x02);
+            #[doc = "f_PCLK / 16"]
+            pub const DIV16: Self = Self(0x03);
+            #[doc = "f_PCLK / 32"]
+            pub const DIV32: Self = Self(0x04);
+            #[doc = "f_PCLK / 64"]
+            pub const DIV64: Self = Self(0x05);
+            #[doc = "f_PCLK / 128"]
+            pub const DIV128: Self = Self(0x06);
+            #[doc = "f_PCLK / 256"]
+            pub const DIV256: Self = Self(0x07);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Tis(pub u8);
-        impl Tis {
-            #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
-            pub const NORMAL: Self = Self(0);
-            #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
-            pub const XOR: Self = Self(0x01);
+        pub struct Cpol(pub u8);
+        impl Cpol {
+            #[doc = "CK to 0 when idle"]
+            pub const IDLELOW: Self = Self(0);
+            #[doc = "CK to 1 when idle"]
+            pub const IDLEHIGH: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct CcmrInputCcs(pub u8);
-        impl CcmrInputCcs {
-            #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
-            pub const TI4: Self = Self(0x01);
-            #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
-            pub const TI3: Self = Self(0x02);
-            #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
-            pub const TRC: Self = Self(0x03);
+        pub struct Mstr(pub u8);
+        impl Mstr {
+            #[doc = "Slave configuration"]
+            pub const SLAVE: Self = Self(0);
+            #[doc = "Master configuration"]
+            pub const MASTER: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Etf(pub u8);
-        impl Etf {
-            #[doc = "No filter, sampling is done at fDTS"]
-            pub const NOFILTER: Self = Self(0);
-            #[doc = "fSAMPLING=fCK_INT, N=2"]
-            pub const FCK_INT_N2: Self = Self(0x01);
-            #[doc = "fSAMPLING=fCK_INT, N=4"]
-            pub const FCK_INT_N4: Self = Self(0x02);
-            #[doc = "fSAMPLING=fCK_INT, N=8"]
-            pub const FCK_INT_N8: Self = Self(0x03);
-            #[doc = "fSAMPLING=fDTS/2, N=6"]
-            pub const FDTS_DIV2_N6: Self = Self(0x04);
-            #[doc = "fSAMPLING=fDTS/2, N=8"]
-            pub const FDTS_DIV2_N8: Self = Self(0x05);
-            #[doc = "fSAMPLING=fDTS/4, N=6"]
-            pub const FDTS_DIV4_N6: Self = Self(0x06);
-            #[doc = "fSAMPLING=fDTS/4, N=8"]
-            pub const FDTS_DIV4_N8: Self = Self(0x07);
-            #[doc = "fSAMPLING=fDTS/8, N=6"]
-            pub const FDTS_DIV8_N6: Self = Self(0x08);
-            #[doc = "fSAMPLING=fDTS/8, N=8"]
-            pub const FDTS_DIV8_N8: Self = Self(0x09);
-            #[doc = "fSAMPLING=fDTS/16, N=5"]
-            pub const FDTS_DIV16_N5: Self = Self(0x0a);
-            #[doc = "fSAMPLING=fDTS/16, N=6"]
-            pub const FDTS_DIV16_N6: Self = Self(0x0b);
-            #[doc = "fSAMPLING=fDTS/16, N=8"]
-            pub const FDTS_DIV16_N8: Self = Self(0x0c);
-            #[doc = "fSAMPLING=fDTS/32, N=5"]
-            pub const FDTS_DIV32_N5: Self = Self(0x0d);
-            #[doc = "fSAMPLING=fDTS/32, N=6"]
-            pub const FDTS_DIV32_N6: Self = Self(0x0e);
-            #[doc = "fSAMPLING=fDTS/32, N=8"]
-            pub const FDTS_DIV32_N8: Self = Self(0x0f);
+        pub struct Frer(pub u8);
+        impl Frer {
+            #[doc = "No frame format error"]
+            pub const NOERROR: Self = Self(0);
+            #[doc = "A frame format error occurred"]
+            pub const ERROR: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ossr(pub u8);
-        impl Ossr {
-            #[doc = "When inactive, OC/OCN outputs are disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"]
-            pub const IDLELEVEL: Self = Self(0x01);
+        pub struct Lsbfirst(pub u8);
+        impl Lsbfirst {
+            #[doc = "Data is transmitted/received with the MSB first"]
+            pub const MSBFIRST: Self = Self(0);
+            #[doc = "Data is transmitted/received with the LSB first"]
+            pub const LSBFIRST: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Icf(pub u8);
-        impl Icf {
-            #[doc = "No filter, sampling is done at fDTS"]
-            pub const NOFILTER: Self = Self(0);
-            #[doc = "fSAMPLING=fCK_INT, N=2"]
-            pub const FCK_INT_N2: Self = Self(0x01);
-            #[doc = "fSAMPLING=fCK_INT, N=4"]
-            pub const FCK_INT_N4: Self = Self(0x02);
-            #[doc = "fSAMPLING=fCK_INT, N=8"]
-            pub const FCK_INT_N8: Self = Self(0x03);
-            #[doc = "fSAMPLING=fDTS/2, N=6"]
-            pub const FDTS_DIV2_N6: Self = Self(0x04);
-            #[doc = "fSAMPLING=fDTS/2, N=8"]
-            pub const FDTS_DIV2_N8: Self = Self(0x05);
-            #[doc = "fSAMPLING=fDTS/4, N=6"]
-            pub const FDTS_DIV4_N6: Self = Self(0x06);
-            #[doc = "fSAMPLING=fDTS/4, N=8"]
-            pub const FDTS_DIV4_N8: Self = Self(0x07);
-            #[doc = "fSAMPLING=fDTS/8, N=6"]
-            pub const FDTS_DIV8_N6: Self = Self(0x08);
-            #[doc = "fSAMPLING=fDTS/8, N=8"]
-            pub const FDTS_DIV8_N8: Self = Self(0x09);
-            #[doc = "fSAMPLING=fDTS/16, N=5"]
-            pub const FDTS_DIV16_N5: Self = Self(0x0a);
-            #[doc = "fSAMPLING=fDTS/16, N=6"]
-            pub const FDTS_DIV16_N6: Self = Self(0x0b);
-            #[doc = "fSAMPLING=fDTS/16, N=8"]
-            pub const FDTS_DIV16_N8: Self = Self(0x0c);
-            #[doc = "fSAMPLING=fDTS/32, N=5"]
-            pub const FDTS_DIV32_N5: Self = Self(0x0d);
-            #[doc = "fSAMPLING=fDTS/32, N=6"]
-            pub const FDTS_DIV32_N6: Self = Self(0x0e);
-            #[doc = "fSAMPLING=fDTS/32, N=8"]
-            pub const FDTS_DIV32_N8: Self = Self(0x0f);
+        pub struct Dff(pub u8);
+        impl Dff {
+            #[doc = "8-bit data frame format is selected for transmission/reception"]
+            pub const EIGHTBIT: Self = Self(0);
+            #[doc = "16-bit data frame format is selected for transmission/reception"]
+            pub const SIXTEENBIT: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Opm(pub u8);
-        impl Opm {
-            #[doc = "Counter is not stopped at update event"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
-            pub const ENABLED: Self = Self(0x01);
+        pub struct Crcnext(pub u8);
+        impl Crcnext {
+            #[doc = "Next transmit value is from Tx buffer"]
+            pub const TXBUFFER: Self = Self(0);
+            #[doc = "Next transmit value is from Tx CRC register"]
+            pub const CRC: Self = Self(0x01);
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "slave mode control register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Smcr(pub u32);
-        impl Smcr {
-            #[doc = "Slave mode selection"]
-            pub const fn sms(&self) -> super::vals::Sms {
-                let val = (self.0 >> 0usize) & 0x07;
-                super::vals::Sms(val as u8)
-            }
-            #[doc = "Slave mode selection"]
-            pub fn set_sms(&mut self, val: super::vals::Sms) {
-                self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
-            }
-            #[doc = "Trigger selection"]
-            pub const fn ts(&self) -> super::vals::Ts {
-                let val = (self.0 >> 4usize) & 0x07;
-                super::vals::Ts(val as u8)
-            }
-            #[doc = "Trigger selection"]
-            pub fn set_ts(&mut self, val: super::vals::Ts) {
-                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
-            }
-            #[doc = "Master/Slave mode"]
-            pub const fn msm(&self) -> super::vals::Msm {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Msm(val as u8)
-            }
-            #[doc = "Master/Slave mode"]
-            pub fn set_msm(&mut self, val: super::vals::Msm) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
-            #[doc = "External trigger filter"]
-            pub const fn etf(&self) -> super::vals::Etf {
-                let val = (self.0 >> 8usize) & 0x0f;
-                super::vals::Etf(val as u8)
-            }
-            #[doc = "External trigger filter"]
-            pub fn set_etf(&mut self, val: super::vals::Etf) {
-                self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
-            }
-            #[doc = "External trigger prescaler"]
-            pub const fn etps(&self) -> super::vals::Etps {
-                let val = (self.0 >> 12usize) & 0x03;
-                super::vals::Etps(val as u8)
-            }
-            #[doc = "External trigger prescaler"]
-            pub fn set_etps(&mut self, val: super::vals::Etps) {
-                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
-            }
-            #[doc = "External clock enable"]
-            pub const fn ece(&self) -> super::vals::Ece {
-                let val = (self.0 >> 14usize) & 0x01;
-                super::vals::Ece(val as u8)
-            }
-            #[doc = "External clock enable"]
-            pub fn set_ece(&mut self, val: super::vals::Ece) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
-            }
-            #[doc = "External trigger polarity"]
-            pub const fn etp(&self) -> super::vals::Etp {
-                let val = (self.0 >> 15usize) & 0x01;
-                super::vals::Etp(val as u8)
-            }
-            #[doc = "External trigger polarity"]
-            pub fn set_etp(&mut self, val: super::vals::Etp) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
-            }
-        }
-        impl Default for Smcr {
-            fn default() -> Smcr {
-                Smcr(0)
-            }
-        }
-        #[doc = "event generation register"]
+        #[doc = "control register 2"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct EgrGp(pub u32);
-        impl EgrGp {
-            #[doc = "Update generation"]
-            pub const fn ug(&self) -> bool {
+        pub struct Cr2(pub u32);
+        impl Cr2 {
+            #[doc = "Rx buffer DMA enable"]
+            pub const fn rxdmaen(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Update generation"]
-            pub fn set_ug(&mut self, val: bool) {
+            #[doc = "Rx buffer DMA enable"]
+            pub fn set_rxdmaen(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn ccg(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn set_ccg(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub const fn comg(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub fn set_comg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Trigger generation"]
-            pub const fn tg(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Trigger generation"]
-            pub fn set_tg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Break generation"]
-            pub const fn bg(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
+            #[doc = "Tx buffer DMA enable"]
+            pub const fn txdmaen(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Break generation"]
-            pub fn set_bg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
-            }
-        }
-        impl Default for EgrGp {
-            fn default() -> EgrGp {
-                EgrGp(0)
-            }
-        }
-        #[doc = "auto-reload register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Arr16(pub u32);
-        impl Arr16 {
-            #[doc = "Auto-reload value"]
-            pub const fn arr(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "Auto-reload value"]
-            pub fn set_arr(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
-        }
-        impl Default for Arr16 {
-            fn default() -> Arr16 {
-                Arr16(0)
-            }
-        }
-        #[doc = "capture/compare mode register 1 (input mode)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct CcmrInput(pub u32);
-        impl CcmrInput {
-            #[doc = "Capture/Compare 1 selection"]
-            pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
-                assert!(n < 2usize);
-                let offs = 0usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::CcmrInputCcs(val as u8)
-            }
-            #[doc = "Capture/Compare 1 selection"]
-            pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
-                assert!(n < 2usize);
-                let offs = 0usize + n * 8usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-            #[doc = "Input capture 1 prescaler"]
-            pub fn icpsc(&self, n: usize) -> u8 {
-                assert!(n < 2usize);
-                let offs = 2usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x03;
-                val as u8
-            }
-            #[doc = "Input capture 1 prescaler"]
-            pub fn set_icpsc(&mut self, n: usize, val: u8) {
-                assert!(n < 2usize);
-                let offs = 2usize + n * 8usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
-            }
-            #[doc = "Input capture 1 filter"]
-            pub fn icf(&self, n: usize) -> super::vals::Icf {
-                assert!(n < 2usize);
-                let offs = 4usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x0f;
-                super::vals::Icf(val as u8)
-            }
-            #[doc = "Input capture 1 filter"]
-            pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) {
-                assert!(n < 2usize);
-                let offs = 4usize + n * 8usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
-            }
-        }
-        impl Default for CcmrInput {
-            fn default() -> CcmrInput {
-                CcmrInput(0)
-            }
-        }
-        #[doc = "repetition counter register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Rcr(pub u32);
-        impl Rcr {
-            #[doc = "Repetition counter value"]
-            pub const fn rep(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Repetition counter value"]
-            pub fn set_rep(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
-            }
-        }
-        impl Default for Rcr {
-            fn default() -> Rcr {
-                Rcr(0)
-            }
-        }
-        #[doc = "capture/compare register 1"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ccr32(pub u32);
-        impl Ccr32 {
-            #[doc = "Capture/Compare 1 value"]
-            pub const fn ccr(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "Capture/Compare 1 value"]
-            pub fn set_ccr(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Ccr32 {
-            fn default() -> Ccr32 {
-                Ccr32(0)
+            #[doc = "Tx buffer DMA enable"]
+            pub fn set_txdmaen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-        }
-        #[doc = "status register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrGp(pub u32);
-        impl SrGp {
-            #[doc = "Update interrupt flag"]
-            pub const fn uif(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
+            #[doc = "SS output enable"]
+            pub const fn ssoe(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Update interrupt flag"]
-            pub fn set_uif(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "SS output enable"]
+            pub fn set_ssoe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Capture/compare 1 interrupt flag"]
-            pub fn ccif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
+            #[doc = "Frame format"]
+            pub const fn frf(&self) -> super::vals::Frf {
+                let val = (self.0 >> 4usize) & 0x01;
+                super::vals::Frf(val as u8)
             }
-            #[doc = "Capture/compare 1 interrupt flag"]
-            pub fn set_ccif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Frame format"]
+            pub fn set_frf(&mut self, val: super::vals::Frf) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
             }
-            #[doc = "COM interrupt flag"]
-            pub const fn comif(&self) -> bool {
+            #[doc = "Error interrupt enable"]
+            pub const fn errie(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "COM interrupt flag"]
-            pub fn set_comif(&mut self, val: bool) {
+            #[doc = "Error interrupt enable"]
+            pub fn set_errie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Trigger interrupt flag"]
-            pub const fn tif(&self) -> bool {
+            #[doc = "RX buffer not empty interrupt enable"]
+            pub const fn rxneie(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Trigger interrupt flag"]
-            pub fn set_tif(&mut self, val: bool) {
+            #[doc = "RX buffer not empty interrupt enable"]
+            pub fn set_rxneie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Break interrupt flag"]
-            pub const fn bif(&self) -> bool {
+            #[doc = "Tx buffer empty interrupt enable"]
+            pub const fn txeie(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Break interrupt flag"]
-            pub fn set_bif(&mut self, val: bool) {
+            #[doc = "Tx buffer empty interrupt enable"]
+            pub fn set_txeie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Capture/Compare 1 overcapture flag"]
-            pub fn ccof(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 overcapture flag"]
-            pub fn set_ccof(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for SrGp {
-            fn default() -> SrGp {
-                SrGp(0)
-            }
-        }
-        #[doc = "control register 1"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr1Basic(pub u32);
-        impl Cr1Basic {
-            #[doc = "Counter enable"]
-            pub const fn cen(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Counter enable"]
-            pub fn set_cen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Update disable"]
-            pub const fn udis(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update disable"]
-            pub fn set_udis(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "Update request source"]
-            pub const fn urs(&self) -> super::vals::Urs {
-                let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Urs(val as u8)
-            }
-            #[doc = "Update request source"]
-            pub fn set_urs(&mut self, val: super::vals::Urs) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
-            }
-            #[doc = "One-pulse mode"]
-            pub const fn opm(&self) -> super::vals::Opm {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Opm(val as u8)
-            }
-            #[doc = "One-pulse mode"]
-            pub fn set_opm(&mut self, val: super::vals::Opm) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Auto-reload preload enable"]
-            pub const fn arpe(&self) -> super::vals::Arpe {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Arpe(val as u8)
-            }
-            #[doc = "Auto-reload preload enable"]
-            pub fn set_arpe(&mut self, val: super::vals::Arpe) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
         }
-        impl Default for Cr1Basic {
-            fn default() -> Cr1Basic {
-                Cr1Basic(0)
-            }
-        }
-        #[doc = "control register 2"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2Adv(pub u32);
-        impl Cr2Adv {
-            #[doc = "Capture/compare preloaded control"]
-            pub const fn ccpc(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/compare preloaded control"]
-            pub fn set_ccpc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Capture/compare control update selection"]
-            pub const fn ccus(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/compare control update selection"]
-            pub fn set_ccus(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Capture/compare DMA selection"]
-            pub const fn ccds(&self) -> super::vals::Ccds {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Ccds(val as u8)
-            }
-            #[doc = "Capture/compare DMA selection"]
-            pub fn set_ccds(&mut self, val: super::vals::Ccds) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Master mode selection"]
-            pub const fn mms(&self) -> super::vals::Mms {
-                let val = (self.0 >> 4usize) & 0x07;
-                super::vals::Mms(val as u8)
-            }
-            #[doc = "Master mode selection"]
-            pub fn set_mms(&mut self, val: super::vals::Mms) {
-                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
-            }
-            #[doc = "TI1 selection"]
-            pub const fn ti1s(&self) -> super::vals::Tis {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Tis(val as u8)
-            }
-            #[doc = "TI1 selection"]
-            pub fn set_ti1s(&mut self, val: super::vals::Tis) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
-            #[doc = "Output Idle state 1"]
-            pub fn ois(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 8usize + n * 2usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Output Idle state 1"]
-            pub fn set_ois(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 8usize + n * 2usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Output Idle state 1"]
-            pub const fn ois1n(&self) -> bool {
-                let val = (self.0 >> 9usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Output Idle state 1"]
-            pub fn set_ois1n(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
-            }
-            #[doc = "Output Idle state 2"]
-            pub const fn ois2n(&self) -> bool {
-                let val = (self.0 >> 11usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Output Idle state 2"]
-            pub fn set_ois2n(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
-            }
-            #[doc = "Output Idle state 3"]
-            pub const fn ois3n(&self) -> bool {
-                let val = (self.0 >> 13usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Output Idle state 3"]
-            pub fn set_ois3n(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
-            }
-        }
-        impl Default for Cr2Adv {
-            fn default() -> Cr2Adv {
-                Cr2Adv(0)
-            }
-        }
-        #[doc = "control register 2"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2Gp(pub u32);
-        impl Cr2Gp {
-            #[doc = "Capture/compare DMA selection"]
-            pub const fn ccds(&self) -> super::vals::Ccds {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Ccds(val as u8)
-            }
-            #[doc = "Capture/compare DMA selection"]
-            pub fn set_ccds(&mut self, val: super::vals::Ccds) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Master mode selection"]
-            pub const fn mms(&self) -> super::vals::Mms {
-                let val = (self.0 >> 4usize) & 0x07;
-                super::vals::Mms(val as u8)
-            }
-            #[doc = "Master mode selection"]
-            pub fn set_mms(&mut self, val: super::vals::Mms) {
-                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
-            }
-            #[doc = "TI1 selection"]
-            pub const fn ti1s(&self) -> super::vals::Tis {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Tis(val as u8)
-            }
-            #[doc = "TI1 selection"]
-            pub fn set_ti1s(&mut self, val: super::vals::Tis) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
-        }
-        impl Default for Cr2Gp {
-            fn default() -> Cr2Gp {
-                Cr2Gp(0)
+        impl Default for Cr2 {
+            fn default() -> Cr2 {
+                Cr2(0)
             }
         }
-        #[doc = "capture/compare register 1"]
+        #[doc = "TX CRC register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ccr16(pub u32);
-        impl Ccr16 {
-            #[doc = "Capture/Compare 1 value"]
-            pub const fn ccr(&self) -> u16 {
+        pub struct Txcrcr(pub u32);
+        impl Txcrcr {
+            #[doc = "Tx CRC register"]
+            pub const fn tx_crc(&self) -> u16 {
                 let val = (self.0 >> 0usize) & 0xffff;
                 val as u16
             }
-            #[doc = "Capture/Compare 1 value"]
-            pub fn set_ccr(&mut self, val: u16) {
+            #[doc = "Tx CRC register"]
+            pub fn set_tx_crc(&mut self, val: u16) {
                 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Ccr16 {
-            fn default() -> Ccr16 {
-                Ccr16(0)
-            }
-        }
-        #[doc = "DMA/Interrupt enable register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct DierBasic(pub u32);
-        impl DierBasic {
-            #[doc = "Update interrupt enable"]
-            pub const fn uie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update interrupt enable"]
-            pub fn set_uie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Update DMA request enable"]
-            pub const fn ude(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update DMA request enable"]
-            pub fn set_ude(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-        }
-        impl Default for DierBasic {
-            fn default() -> DierBasic {
-                DierBasic(0)
-            }
-        }
-        #[doc = "counter"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cnt32(pub u32);
-        impl Cnt32 {
-            #[doc = "counter value"]
-            pub const fn cnt(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "counter value"]
-            pub fn set_cnt(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
-        }
-        impl Default for Cnt32 {
-            fn default() -> Cnt32 {
-                Cnt32(0)
+        impl Default for Txcrcr {
+            fn default() -> Txcrcr {
+                Txcrcr(0)
             }
         }
-        #[doc = "capture/compare mode register 2 (output mode)"]
+        #[doc = "data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct CcmrOutput(pub u32);
-        impl CcmrOutput {
-            #[doc = "Capture/Compare 3 selection"]
-            pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs {
-                assert!(n < 2usize);
-                let offs = 0usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::CcmrOutputCcs(val as u8)
-            }
-            #[doc = "Capture/Compare 3 selection"]
-            pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) {
-                assert!(n < 2usize);
-                let offs = 0usize + n * 8usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-            #[doc = "Output compare 3 fast enable"]
-            pub fn ocfe(&self, n: usize) -> bool {
-                assert!(n < 2usize);
-                let offs = 2usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Output compare 3 fast enable"]
-            pub fn set_ocfe(&mut self, n: usize, val: bool) {
-                assert!(n < 2usize);
-                let offs = 2usize + n * 8usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Output compare 3 preload enable"]
-            pub fn ocpe(&self, n: usize) -> super::vals::Ocpe {
-                assert!(n < 2usize);
-                let offs = 3usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Ocpe(val as u8)
-            }
-            #[doc = "Output compare 3 preload enable"]
-            pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) {
-                assert!(n < 2usize);
-                let offs = 3usize + n * 8usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-            #[doc = "Output compare 3 mode"]
-            pub fn ocm(&self, n: usize) -> super::vals::Ocm {
-                assert!(n < 2usize);
-                let offs = 4usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x07;
-                super::vals::Ocm(val as u8)
-            }
-            #[doc = "Output compare 3 mode"]
-            pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) {
-                assert!(n < 2usize);
-                let offs = 4usize + n * 8usize;
-                self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs);
-            }
-            #[doc = "Output compare 3 clear enable"]
-            pub fn occe(&self, n: usize) -> bool {
-                assert!(n < 2usize);
-                let offs = 7usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
+        pub struct Dr(pub u32);
+        impl Dr {
+            #[doc = "Data register"]
+            pub const fn dr(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
             }
-            #[doc = "Output compare 3 clear enable"]
-            pub fn set_occe(&mut self, n: usize, val: bool) {
-                assert!(n < 2usize);
-                let offs = 7usize + n * 8usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Data register"]
+            pub fn set_dr(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for CcmrOutput {
-            fn default() -> CcmrOutput {
-                CcmrOutput(0)
+        impl Default for Dr {
+            fn default() -> Dr {
+                Dr(0)
             }
         }
-        #[doc = "control register 1"]
+        #[doc = "status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr1Gp(pub u32);
-        impl Cr1Gp {
-            #[doc = "Counter enable"]
-            pub const fn cen(&self) -> bool {
+        pub struct Sr(pub u32);
+        impl Sr {
+            #[doc = "Receive buffer not empty"]
+            pub const fn rxne(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Counter enable"]
-            pub fn set_cen(&mut self, val: bool) {
+            #[doc = "Receive buffer not empty"]
+            pub fn set_rxne(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Update disable"]
-            pub const fn udis(&self) -> bool {
+            #[doc = "Transmit buffer empty"]
+            pub const fn txe(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Update disable"]
-            pub fn set_udis(&mut self, val: bool) {
+            #[doc = "Transmit buffer empty"]
+            pub fn set_txe(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Update request source"]
-            pub const fn urs(&self) -> super::vals::Urs {
-                let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Urs(val as u8)
-            }
-            #[doc = "Update request source"]
-            pub fn set_urs(&mut self, val: super::vals::Urs) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
-            }
-            #[doc = "One-pulse mode"]
-            pub const fn opm(&self) -> super::vals::Opm {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Opm(val as u8)
-            }
-            #[doc = "One-pulse mode"]
-            pub fn set_opm(&mut self, val: super::vals::Opm) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Direction"]
-            pub const fn dir(&self) -> super::vals::Dir {
+            #[doc = "CRC error flag"]
+            pub const fn crcerr(&self) -> bool {
                 let val = (self.0 >> 4usize) & 0x01;
-                super::vals::Dir(val as u8)
-            }
-            #[doc = "Direction"]
-            pub fn set_dir(&mut self, val: super::vals::Dir) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
-            }
-            #[doc = "Center-aligned mode selection"]
-            pub const fn cms(&self) -> super::vals::Cms {
-                let val = (self.0 >> 5usize) & 0x03;
-                super::vals::Cms(val as u8)
-            }
-            #[doc = "Center-aligned mode selection"]
-            pub fn set_cms(&mut self, val: super::vals::Cms) {
-                self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize);
-            }
-            #[doc = "Auto-reload preload enable"]
-            pub const fn arpe(&self) -> super::vals::Arpe {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Arpe(val as u8)
-            }
-            #[doc = "Auto-reload preload enable"]
-            pub fn set_arpe(&mut self, val: super::vals::Arpe) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
-            #[doc = "Clock division"]
-            pub const fn ckd(&self) -> super::vals::Ckd {
-                let val = (self.0 >> 8usize) & 0x03;
-                super::vals::Ckd(val as u8)
-            }
-            #[doc = "Clock division"]
-            pub fn set_ckd(&mut self, val: super::vals::Ckd) {
-                self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
-            }
-        }
-        impl Default for Cr1Gp {
-            fn default() -> Cr1Gp {
-                Cr1Gp(0)
-            }
-        }
-        #[doc = "status register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrAdv(pub u32);
-        impl SrAdv {
-            #[doc = "Update interrupt flag"]
-            pub const fn uif(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Update interrupt flag"]
-            pub fn set_uif(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Capture/compare 1 interrupt flag"]
-            pub fn ccif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/compare 1 interrupt flag"]
-            pub fn set_ccif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "CRC error flag"]
+            pub fn set_crcerr(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "COM interrupt flag"]
-            pub const fn comif(&self) -> bool {
+            #[doc = "Mode fault"]
+            pub const fn modf(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "COM interrupt flag"]
-            pub fn set_comif(&mut self, val: bool) {
+            #[doc = "Mode fault"]
+            pub fn set_modf(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Trigger interrupt flag"]
-            pub const fn tif(&self) -> bool {
+            #[doc = "Overrun flag"]
+            pub const fn ovr(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Trigger interrupt flag"]
-            pub fn set_tif(&mut self, val: bool) {
+            #[doc = "Overrun flag"]
+            pub fn set_ovr(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Break interrupt flag"]
-            pub const fn bif(&self) -> bool {
+            #[doc = "Busy flag"]
+            pub const fn bsy(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Break interrupt flag"]
-            pub fn set_bif(&mut self, val: bool) {
+            #[doc = "Busy flag"]
+            pub fn set_bsy(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Capture/Compare 1 overcapture flag"]
-            pub fn ccof(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 overcapture flag"]
-            pub fn set_ccof(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for SrAdv {
-            fn default() -> SrAdv {
-                SrAdv(0)
-            }
-        }
-        #[doc = "control register 2"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2Basic(pub u32);
-        impl Cr2Basic {
-            #[doc = "Master mode selection"]
-            pub const fn mms(&self) -> super::vals::Mms {
-                let val = (self.0 >> 4usize) & 0x07;
-                super::vals::Mms(val as u8)
-            }
-            #[doc = "Master mode selection"]
-            pub fn set_mms(&mut self, val: super::vals::Mms) {
-                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
-            }
-        }
-        impl Default for Cr2Basic {
-            fn default() -> Cr2Basic {
-                Cr2Basic(0)
-            }
-        }
-        #[doc = "capture/compare enable register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct CcerAdv(pub u32);
-        impl CcerAdv {
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn cce(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn set_cce(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccp(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccp(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare 1 complementary output enable"]
-            pub fn ccne(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 2usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 complementary output enable"]
-            pub fn set_ccne(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 2usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccnp(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "TI frame format error"]
+            pub const fn fre(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccnp(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "TI frame format error"]
+            pub fn set_fre(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
         }
-        impl Default for CcerAdv {
-            fn default() -> CcerAdv {
-                CcerAdv(0)
+        impl Default for Sr {
+            fn default() -> Sr {
+                Sr(0)
             }
         }
-        #[doc = "DMA control register"]
+        #[doc = "control register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dcr(pub u32);
-        impl Dcr {
-            #[doc = "DMA base address"]
-            pub const fn dba(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x1f;
-                val as u8
-            }
-            #[doc = "DMA base address"]
-            pub fn set_dba(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
-            }
-            #[doc = "DMA burst length"]
-            pub const fn dbl(&self) -> u8 {
-                let val = (self.0 >> 8usize) & 0x1f;
-                val as u8
-            }
-            #[doc = "DMA burst length"]
-            pub fn set_dbl(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+        pub struct Cr1(pub u32);
+        impl Cr1 {
+            #[doc = "Clock phase"]
+            pub const fn cpha(&self) -> super::vals::Cpha {
+                let val = (self.0 >> 0usize) & 0x01;
+                super::vals::Cpha(val as u8)
             }
-        }
-        impl Default for Dcr {
-            fn default() -> Dcr {
-                Dcr(0)
+            #[doc = "Clock phase"]
+            pub fn set_cpha(&mut self, val: super::vals::Cpha) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
             }
-        }
-        #[doc = "DMA/Interrupt enable register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct DierAdv(pub u32);
-        impl DierAdv {
-            #[doc = "Update interrupt enable"]
-            pub const fn uie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
+            #[doc = "Clock polarity"]
+            pub const fn cpol(&self) -> super::vals::Cpol {
+                let val = (self.0 >> 1usize) & 0x01;
+                super::vals::Cpol(val as u8)
             }
-            #[doc = "Update interrupt enable"]
-            pub fn set_uie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Clock polarity"]
+            pub fn set_cpol(&mut self, val: super::vals::Cpol) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
             }
-            #[doc = "Capture/Compare 1 interrupt enable"]
-            pub fn ccie(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
+            #[doc = "Master selection"]
+            pub const fn mstr(&self) -> super::vals::Mstr {
+                let val = (self.0 >> 2usize) & 0x01;
+                super::vals::Mstr(val as u8)
             }
-            #[doc = "Capture/Compare 1 interrupt enable"]
-            pub fn set_ccie(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Master selection"]
+            pub fn set_mstr(&mut self, val: super::vals::Mstr) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
             }
-            #[doc = "COM interrupt enable"]
-            pub const fn comie(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
+            #[doc = "Baud rate control"]
+            pub const fn br(&self) -> super::vals::Br {
+                let val = (self.0 >> 3usize) & 0x07;
+                super::vals::Br(val as u8)
             }
-            #[doc = "COM interrupt enable"]
-            pub fn set_comie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            #[doc = "Baud rate control"]
+            pub fn set_br(&mut self, val: super::vals::Br) {
+                self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
             }
-            #[doc = "Trigger interrupt enable"]
-            pub const fn tie(&self) -> bool {
+            #[doc = "SPI enable"]
+            pub const fn spe(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Trigger interrupt enable"]
-            pub fn set_tie(&mut self, val: bool) {
+            #[doc = "SPI enable"]
+            pub fn set_spe(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Break interrupt enable"]
-            pub const fn bie(&self) -> bool {
+            #[doc = "Frame format"]
+            pub const fn lsbfirst(&self) -> super::vals::Lsbfirst {
                 let val = (self.0 >> 7usize) & 0x01;
-                val != 0
+                super::vals::Lsbfirst(val as u8)
             }
-            #[doc = "Break interrupt enable"]
-            pub fn set_bie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            #[doc = "Frame format"]
+            pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
             }
-            #[doc = "Update DMA request enable"]
-            pub const fn ude(&self) -> bool {
+            #[doc = "Internal slave select"]
+            pub const fn ssi(&self) -> bool {
                 let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "Update DMA request enable"]
-            pub fn set_ude(&mut self, val: bool) {
+            #[doc = "Internal slave select"]
+            pub fn set_ssi(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Capture/Compare 1 DMA request enable"]
-            pub fn ccde(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 DMA request enable"]
-            pub fn set_ccde(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "COM DMA request enable"]
-            pub const fn comde(&self) -> bool {
-                let val = (self.0 >> 13usize) & 0x01;
-                val != 0
-            }
-            #[doc = "COM DMA request enable"]
-            pub fn set_comde(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
-            }
-            #[doc = "Trigger DMA request enable"]
-            pub const fn tde(&self) -> bool {
-                let val = (self.0 >> 14usize) & 0x01;
+            #[doc = "Software slave management"]
+            pub const fn ssm(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
                 val != 0
             }
-            #[doc = "Trigger DMA request enable"]
-            pub fn set_tde(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
-            }
-        }
-        impl Default for DierAdv {
-            fn default() -> DierAdv {
-                DierAdv(0)
-            }
-        }
-        #[doc = "break and dead-time register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Bdtr(pub u32);
-        impl Bdtr {
-            #[doc = "Dead-time generator setup"]
-            pub const fn dtg(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Dead-time generator setup"]
-            pub fn set_dtg(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
-            }
-            #[doc = "Lock configuration"]
-            pub const fn lock(&self) -> u8 {
-                let val = (self.0 >> 8usize) & 0x03;
-                val as u8
-            }
-            #[doc = "Lock configuration"]
-            pub fn set_lock(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
+            #[doc = "Software slave management"]
+            pub fn set_ssm(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
             }
-            #[doc = "Off-state selection for Idle mode"]
-            pub const fn ossi(&self) -> super::vals::Ossi {
+            #[doc = "Receive only"]
+            pub const fn rxonly(&self) -> super::vals::Rxonly {
                 let val = (self.0 >> 10usize) & 0x01;
-                super::vals::Ossi(val as u8)
+                super::vals::Rxonly(val as u8)
             }
-            #[doc = "Off-state selection for Idle mode"]
-            pub fn set_ossi(&mut self, val: super::vals::Ossi) {
+            #[doc = "Receive only"]
+            pub fn set_rxonly(&mut self, val: super::vals::Rxonly) {
                 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
             }
-            #[doc = "Off-state selection for Run mode"]
-            pub const fn ossr(&self) -> super::vals::Ossr {
+            #[doc = "Data frame format"]
+            pub const fn dff(&self) -> super::vals::Dff {
                 let val = (self.0 >> 11usize) & 0x01;
-                super::vals::Ossr(val as u8)
+                super::vals::Dff(val as u8)
             }
-            #[doc = "Off-state selection for Run mode"]
-            pub fn set_ossr(&mut self, val: super::vals::Ossr) {
+            #[doc = "Data frame format"]
+            pub fn set_dff(&mut self, val: super::vals::Dff) {
                 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
             }
-            #[doc = "Break enable"]
-            pub const fn bke(&self) -> bool {
+            #[doc = "CRC transfer next"]
+            pub const fn crcnext(&self) -> super::vals::Crcnext {
                 let val = (self.0 >> 12usize) & 0x01;
-                val != 0
+                super::vals::Crcnext(val as u8)
             }
-            #[doc = "Break enable"]
-            pub fn set_bke(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+            #[doc = "CRC transfer next"]
+            pub fn set_crcnext(&mut self, val: super::vals::Crcnext) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
             }
-            #[doc = "Break polarity"]
-            pub const fn bkp(&self) -> bool {
+            #[doc = "Hardware CRC calculation enable"]
+            pub const fn crcen(&self) -> bool {
                 let val = (self.0 >> 13usize) & 0x01;
                 val != 0
             }
-            #[doc = "Break polarity"]
-            pub fn set_bkp(&mut self, val: bool) {
+            #[doc = "Hardware CRC calculation enable"]
+            pub fn set_crcen(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
             }
-            #[doc = "Automatic output enable"]
-            pub const fn aoe(&self) -> bool {
+            #[doc = "Output enable in bidirectional mode"]
+            pub const fn bidioe(&self) -> super::vals::Bidioe {
                 let val = (self.0 >> 14usize) & 0x01;
-                val != 0
+                super::vals::Bidioe(val as u8)
             }
-            #[doc = "Automatic output enable"]
-            pub fn set_aoe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            #[doc = "Output enable in bidirectional mode"]
+            pub fn set_bidioe(&mut self, val: super::vals::Bidioe) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
             }
-            #[doc = "Main output enable"]
-            pub const fn moe(&self) -> bool {
+            #[doc = "Bidirectional data mode enable"]
+            pub const fn bidimode(&self) -> super::vals::Bidimode {
                 let val = (self.0 >> 15usize) & 0x01;
-                val != 0
+                super::vals::Bidimode(val as u8)
             }
-            #[doc = "Main output enable"]
-            pub fn set_moe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+            #[doc = "Bidirectional data mode enable"]
+            pub fn set_bidimode(&mut self, val: super::vals::Bidimode) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
             }
         }
-        impl Default for Bdtr {
-            fn default() -> Bdtr {
-                Bdtr(0)
+        impl Default for Cr1 {
+            fn default() -> Cr1 {
+                Cr1(0)
             }
         }
-        #[doc = "event generation register"]
+        #[doc = "RX CRC register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct EgrAdv(pub u32);
-        impl EgrAdv {
-            #[doc = "Update generation"]
-            pub const fn ug(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update generation"]
-            pub fn set_ug(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn ccg(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn set_ccg(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub const fn comg(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub fn set_comg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Trigger generation"]
-            pub const fn tg(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Trigger generation"]
-            pub fn set_tg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Break generation"]
-            pub const fn bg(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
+        pub struct Rxcrcr(pub u32);
+        impl Rxcrcr {
+            #[doc = "Rx CRC register"]
+            pub const fn rx_crc(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
             }
-            #[doc = "Break generation"]
-            pub fn set_bg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            #[doc = "Rx CRC register"]
+            pub fn set_rx_crc(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for EgrAdv {
-            fn default() -> EgrAdv {
-                EgrAdv(0)
+        impl Default for Rxcrcr {
+            fn default() -> Rxcrcr {
+                Rxcrcr(0)
             }
         }
-        #[doc = "status register"]
+        #[doc = "CRC polynomial register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrBasic(pub u32);
-        impl SrBasic {
-            #[doc = "Update interrupt flag"]
-            pub const fn uif(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
+        pub struct Crcpr(pub u32);
+        impl Crcpr {
+            #[doc = "CRC polynomial register"]
+            pub const fn crcpoly(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
             }
-            #[doc = "Update interrupt flag"]
-            pub fn set_uif(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "CRC polynomial register"]
+            pub fn set_crcpoly(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for SrBasic {
-            fn default() -> SrBasic {
-                SrBasic(0)
+        impl Default for Crcpr {
+            fn default() -> Crcpr {
+                Crcpr(0)
             }
         }
-        #[doc = "auto-reload register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Arr32(pub u32);
-        impl Arr32 {
-            #[doc = "Auto-reload value"]
-            pub const fn arr(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
-            }
-            #[doc = "Auto-reload value"]
-            pub fn set_arr(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
-            }
+    }
+}
+pub mod gpio_v2 {
+    use crate::generic::*;
+    #[doc = "General-purpose I/Os"]
+    #[derive(Copy, Clone)]
+    pub struct Gpio(pub *mut u8);
+    unsafe impl Send for Gpio {}
+    unsafe impl Sync for Gpio {}
+    impl Gpio {
+        #[doc = "GPIO port mode register"]
+        pub fn moder(self) -> Reg<regs::Moder, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        impl Default for Arr32 {
-            fn default() -> Arr32 {
-                Arr32(0)
-            }
+        #[doc = "GPIO port output type register"]
+        pub fn otyper(self) -> Reg<regs::Otyper, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "counter"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cnt16(pub u32);
-        impl Cnt16 {
-            #[doc = "counter value"]
-            pub const fn cnt(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "counter value"]
-            pub fn set_cnt(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
+        #[doc = "GPIO port output speed register"]
+        pub fn ospeedr(self) -> Reg<regs::Ospeedr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
-        impl Default for Cnt16 {
-            fn default() -> Cnt16 {
-                Cnt16(0)
-            }
+        #[doc = "GPIO port pull-up/pull-down register"]
+        pub fn pupdr(self) -> Reg<regs::Pupdr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
-        #[doc = "DMA/Interrupt enable register"]
+        #[doc = "GPIO port input data register"]
+        pub fn idr(self) -> Reg<regs::Idr, R> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "GPIO port output data register"]
+        pub fn odr(self) -> Reg<regs::Odr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "GPIO port bit set/reset register"]
+        pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        }
+        #[doc = "GPIO port configuration lock register"]
+        pub fn lckr(self) -> Reg<regs::Lckr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(28usize)) }
+        }
+        #[doc = "GPIO alternate function register (low, high)"]
+        pub fn afr(self, n: usize) -> Reg<regs::Afr, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) }
+        }
+    }
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "GPIO port mode register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct DierGp(pub u32);
-        impl DierGp {
-            #[doc = "Update interrupt enable"]
-            pub const fn uie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update interrupt enable"]
-            pub fn set_uie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Capture/Compare 1 interrupt enable"]
-            pub fn ccie(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 interrupt enable"]
-            pub fn set_ccie(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Trigger interrupt enable"]
-            pub const fn tie(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Trigger interrupt enable"]
-            pub fn set_tie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Update DMA request enable"]
-            pub const fn ude(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update DMA request enable"]
-            pub fn set_ude(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-            #[doc = "Capture/Compare 1 DMA request enable"]
-            pub fn ccde(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 DMA request enable"]
-            pub fn set_ccde(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Trigger DMA request enable"]
-            pub const fn tde(&self) -> bool {
-                let val = (self.0 >> 14usize) & 0x01;
-                val != 0
+        pub struct Moder(pub u32);
+        impl Moder {
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn moder(&self, n: usize) -> super::vals::Moder {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Moder(val as u8)
             }
-            #[doc = "Trigger DMA request enable"]
-            pub fn set_tde(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
             }
         }
-        impl Default for DierGp {
-            fn default() -> DierGp {
-                DierGp(0)
+        impl Default for Moder {
+            fn default() -> Moder {
+                Moder(0)
             }
         }
-        #[doc = "prescaler"]
+        #[doc = "GPIO port output type register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Psc(pub u32);
-        impl Psc {
-            #[doc = "Prescaler value"]
-            pub const fn psc(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
+        pub struct Otyper(pub u32);
+        impl Otyper {
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn ot(&self, n: usize) -> super::vals::Ot {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Ot(val as u8)
             }
-            #[doc = "Prescaler value"]
-            pub fn set_psc(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
         }
-        impl Default for Psc {
-            fn default() -> Psc {
-                Psc(0)
+        impl Default for Otyper {
+            fn default() -> Otyper {
+                Otyper(0)
             }
         }
-        #[doc = "event generation register"]
+        #[doc = "GPIO alternate function register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct EgrBasic(pub u32);
-        impl EgrBasic {
-            #[doc = "Update generation"]
-            pub const fn ug(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
+        pub struct Afr(pub u32);
+        impl Afr {
+            #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
+            pub fn afr(&self, n: usize) -> super::vals::Afr {
+                assert!(n < 8usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x0f;
+                super::vals::Afr(val as u8)
             }
-            #[doc = "Update generation"]
-            pub fn set_ug(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
+            pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) {
+                assert!(n < 8usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
             }
         }
-        impl Default for EgrBasic {
-            fn default() -> EgrBasic {
-                EgrBasic(0)
+        impl Default for Afr {
+            fn default() -> Afr {
+                Afr(0)
             }
         }
-        #[doc = "DMA address for full transfer"]
+        #[doc = "GPIO port output data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dmar(pub u32);
-        impl Dmar {
-            #[doc = "DMA register for burst accesses"]
-            pub const fn dmab(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
+        pub struct Odr(pub u32);
+        impl Odr {
+            #[doc = "Port output data (y = 0..15)"]
+            pub fn odr(&self, n: usize) -> super::vals::Odr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Odr(val as u8)
             }
-            #[doc = "DMA register for burst accesses"]
-            pub fn set_dmab(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "Port output data (y = 0..15)"]
+            pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
         }
-        impl Default for Dmar {
-            fn default() -> Dmar {
-                Dmar(0)
+        impl Default for Odr {
+            fn default() -> Odr {
+                Odr(0)
             }
         }
-        #[doc = "capture/compare enable register"]
+        #[doc = "GPIO port pull-up/pull-down register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct CcerGp(pub u32);
-        impl CcerGp {
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn cce(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn set_cce(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccp(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccp(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccnp(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
+        pub struct Pupdr(pub u32);
+        impl Pupdr {
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn pupdr(&self, n: usize) -> super::vals::Pupdr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Pupdr(val as u8)
             }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccnp(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
             }
         }
-        impl Default for CcerGp {
-            fn default() -> CcerGp {
-                CcerGp(0)
+        impl Default for Pupdr {
+            fn default() -> Pupdr {
+                Pupdr(0)
             }
         }
-    }
-}
-pub mod gpio_v1 {
-    use crate::generic::*;
-    #[doc = "General purpose I/O"]
-    #[derive(Copy, Clone)]
-    pub struct Gpio(pub *mut u8);
-    unsafe impl Send for Gpio {}
-    unsafe impl Sync for Gpio {}
-    impl Gpio {
-        #[doc = "Port configuration register low (GPIOn_CRL)"]
-        pub fn cr(self, n: usize) -> Reg<regs::Cr, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
-        }
-        #[doc = "Port input data register (GPIOn_IDR)"]
-        pub fn idr(self) -> Reg<regs::Idr, R> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "Port output data register (GPIOn_ODR)"]
-        pub fn odr(self) -> Reg<regs::Odr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
-        pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "Port bit reset register (GPIOn_BRR)"]
-        pub fn brr(self) -> Reg<regs::Brr, W> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-        #[doc = "Port configuration lock register"]
-        pub fn lckr(self) -> Reg<regs::Lckr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "Port input data register (GPIOn_IDR)"]
+        #[doc = "GPIO port input data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
         pub struct Idr(pub u32);
         impl Idr {
-            #[doc = "Port input data"]
+            #[doc = "Port input data (y = 0..15)"]
             pub fn idr(&self, n: usize) -> super::vals::Idr {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 super::vals::Idr(val as u8)
             }
-            #[doc = "Port input data"]
+            #[doc = "Port input data (y = 0..15)"]
             pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 1usize;
@@ -4590,80 +2572,65 @@ pub mod gpio_v1 {
                 Idr(0)
             }
         }
-        #[doc = "Port bit reset register (GPIOn_BRR)"]
+        #[doc = "GPIO port configuration lock register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Brr(pub u32);
-        impl Brr {
-            #[doc = "Reset bit"]
-            pub fn br(&self, n: usize) -> bool {
+        pub struct Lckr(pub u32);
+        impl Lckr {
+            #[doc = "Port x lock bit y (y= 0..15)"]
+            pub fn lck(&self, n: usize) -> super::vals::Lck {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
-                val != 0
+                super::vals::Lck(val as u8)
             }
-            #[doc = "Reset bit"]
-            pub fn set_br(&mut self, n: usize, val: bool) {
+            #[doc = "Port x lock bit y (y= 0..15)"]
+            pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for Brr {
-            fn default() -> Brr {
-                Brr(0)
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
-        }
-        #[doc = "Port output data register (GPIOn_ODR)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Odr(pub u32);
-        impl Odr {
-            #[doc = "Port output data"]
-            pub fn odr(&self, n: usize) -> super::vals::Odr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Odr(val as u8)
+            #[doc = "Port x lock bit y (y= 0..15)"]
+            pub const fn lckk(&self) -> super::vals::Lckk {
+                let val = (self.0 >> 16usize) & 0x01;
+                super::vals::Lckk(val as u8)
             }
-            #[doc = "Port output data"]
-            pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "Port x lock bit y (y= 0..15)"]
+            pub fn set_lckk(&mut self, val: super::vals::Lckk) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
             }
         }
-        impl Default for Odr {
-            fn default() -> Odr {
-                Odr(0)
+        impl Default for Lckr {
+            fn default() -> Lckr {
+                Lckr(0)
             }
         }
-        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
+        #[doc = "GPIO port bit set/reset register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
         pub struct Bsrr(pub u32);
         impl Bsrr {
-            #[doc = "Set bit"]
+            #[doc = "Port x set bit y (y= 0..15)"]
             pub fn bs(&self, n: usize) -> bool {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Set bit"]
+            #[doc = "Port x set bit y (y= 0..15)"]
             pub fn set_bs(&mut self, n: usize, val: bool) {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Reset bit"]
+            #[doc = "Port x set bit y (y= 0..15)"]
             pub fn br(&self, n: usize) -> bool {
                 assert!(n < 16usize);
                 let offs = 16usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Reset bit"]
+            #[doc = "Port x set bit y (y= 0..15)"]
             pub fn set_br(&mut self, n: usize, val: bool) {
                 assert!(n < 16usize);
                 let offs = 16usize + n * 1usize;
@@ -4675,74 +2642,28 @@ pub mod gpio_v1 {
                 Bsrr(0)
             }
         }
-        #[doc = "Port configuration register (GPIOn_CRx)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr(pub u32);
-        impl Cr {
-            #[doc = "Port n mode bits"]
-            pub fn mode(&self, n: usize) -> super::vals::Mode {
-                assert!(n < 8usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Mode(val as u8)
-            }
-            #[doc = "Port n mode bits"]
-            pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
-                assert!(n < 8usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-            #[doc = "Port n configuration bits"]
-            pub fn cnf(&self, n: usize) -> super::vals::Cnf {
-                assert!(n < 8usize);
-                let offs = 2usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Cnf(val as u8)
-            }
-            #[doc = "Port n configuration bits"]
-            pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) {
-                assert!(n < 8usize);
-                let offs = 2usize + n * 4usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-        }
-        impl Default for Cr {
-            fn default() -> Cr {
-                Cr(0)
-            }
-        }
-        #[doc = "Port configuration lock register"]
+        #[doc = "GPIO port output speed register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Lckr(pub u32);
-        impl Lckr {
-            #[doc = "Port A Lock bit"]
-            pub fn lck(&self, n: usize) -> super::vals::Lck {
+        pub struct Ospeedr(pub u32);
+        impl Ospeedr {
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
                 assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Lck(val as u8)
+                let offs = 0usize + n * 2usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Ospeedr(val as u8)
             }
-            #[doc = "Port A Lock bit"]
-            pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
                 assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-            #[doc = "Lock key"]
-            pub const fn lckk(&self) -> super::vals::Lckk {
-                let val = (self.0 >> 16usize) & 0x01;
-                super::vals::Lckk(val as u8)
-            }
-            #[doc = "Lock key"]
-            pub fn set_lckk(&mut self, val: super::vals::Lckk) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
+                let offs = 0usize + n * 2usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
             }
         }
-        impl Default for Lckr {
-            fn default() -> Lckr {
-                Lckr(0)
+        impl Default for Ospeedr {
+            fn default() -> Ospeedr {
+                Ospeedr(0)
             }
         }
     }
@@ -4759,43 +2680,19 @@ pub mod gpio_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Idr(pub u8);
-        impl Idr {
-            #[doc = "Input is logic low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Input is logic high"]
-            pub const HIGH: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Odr(pub u8);
-        impl Odr {
-            #[doc = "Set output to logic low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Set output to logic high"]
-            pub const HIGH: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Brw(pub u8);
         impl Brw {
-            #[doc = "No action on the corresponding ODx bit"]
-            pub const NOACTION: Self = Self(0);
-            #[doc = "Reset the ODx bit"]
+            #[doc = "Resets the corresponding ODRx bit"]
             pub const RESET: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cnf(pub u8);
-        impl Cnf {
-            #[doc = "Analog mode / Push-Pull mode"]
+        pub struct Ot(pub u8);
+        impl Ot {
+            #[doc = "Output push-pull (reset state)"]
             pub const PUSHPULL: Self = Self(0);
-            #[doc = "Floating input (reset state) / Open Drain-Mode"]
+            #[doc = "Output open-drain"]
             pub const OPENDRAIN: Self = Self(0x01);
-            #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"]
-            pub const ALTPUSHPULL: Self = Self(0x02);
-            #[doc = "Alternate Function Open-Drain Mode"]
-            pub const ALTOPENDRAIN: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -4808,95 +2705,212 @@ pub mod gpio_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Moder(pub u8);
+        impl Moder {
+            #[doc = "Input mode (reset state)"]
+            pub const INPUT: Self = Self(0);
+            #[doc = "General purpose output mode"]
+            pub const OUTPUT: Self = Self(0x01);
+            #[doc = "Alternate function mode"]
+            pub const ALTERNATE: Self = Self(0x02);
+            #[doc = "Analog mode"]
+            pub const ANALOG: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Bsw(pub u8);
         impl Bsw {
-            #[doc = "No action on the corresponding ODx bit"]
-            pub const NOACTION: Self = Self(0);
             #[doc = "Sets the corresponding ODRx bit"]
             pub const SET: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mode(pub u8);
-        impl Mode {
-            #[doc = "Input mode (reset state)"]
-            pub const INPUT: Self = Self(0);
-            #[doc = "Output mode 10 MHz"]
-            pub const OUTPUT: Self = Self(0x01);
-            #[doc = "Output mode 2 MHz"]
-            pub const OUTPUT2: Self = Self(0x02);
-            #[doc = "Output mode 50 MHz"]
-            pub const OUTPUT50: Self = Self(0x03);
+        pub struct Pupdr(pub u8);
+        impl Pupdr {
+            #[doc = "No pull-up, pull-down"]
+            pub const FLOATING: Self = Self(0);
+            #[doc = "Pull-up"]
+            pub const PULLUP: Self = Self(0x01);
+            #[doc = "Pull-down"]
+            pub const PULLDOWN: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ospeedr(pub u8);
+        impl Ospeedr {
+            #[doc = "Low speed"]
+            pub const LOWSPEED: Self = Self(0);
+            #[doc = "Medium speed"]
+            pub const MEDIUMSPEED: Self = Self(0x01);
+            #[doc = "High speed"]
+            pub const HIGHSPEED: Self = Self(0x02);
+            #[doc = "Very high speed"]
+            pub const VERYHIGHSPEED: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Idr(pub u8);
+        impl Idr {
+            #[doc = "Input is logic low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Input is logic high"]
+            pub const HIGH: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Afr(pub u8);
+        impl Afr {
+            #[doc = "AF0"]
+            pub const AF0: Self = Self(0);
+            #[doc = "AF1"]
+            pub const AF1: Self = Self(0x01);
+            #[doc = "AF2"]
+            pub const AF2: Self = Self(0x02);
+            #[doc = "AF3"]
+            pub const AF3: Self = Self(0x03);
+            #[doc = "AF4"]
+            pub const AF4: Self = Self(0x04);
+            #[doc = "AF5"]
+            pub const AF5: Self = Self(0x05);
+            #[doc = "AF6"]
+            pub const AF6: Self = Self(0x06);
+            #[doc = "AF7"]
+            pub const AF7: Self = Self(0x07);
+            #[doc = "AF8"]
+            pub const AF8: Self = Self(0x08);
+            #[doc = "AF9"]
+            pub const AF9: Self = Self(0x09);
+            #[doc = "AF10"]
+            pub const AF10: Self = Self(0x0a);
+            #[doc = "AF11"]
+            pub const AF11: Self = Self(0x0b);
+            #[doc = "AF12"]
+            pub const AF12: Self = Self(0x0c);
+            #[doc = "AF13"]
+            pub const AF13: Self = Self(0x0d);
+            #[doc = "AF14"]
+            pub const AF14: Self = Self(0x0e);
+            #[doc = "AF15"]
+            pub const AF15: Self = Self(0x0f);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Odr(pub u8);
+        impl Odr {
+            #[doc = "Set output to logic low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Set output to logic high"]
+            pub const HIGH: Self = Self(0x01);
         }
     }
 }
-pub mod generic {
-    use core::marker::PhantomData;
-    #[derive(Copy, Clone)]
-    pub struct RW;
-    #[derive(Copy, Clone)]
-    pub struct R;
-    #[derive(Copy, Clone)]
-    pub struct W;
-    mod sealed {
-        use super::*;
-        pub trait Access {}
-        impl Access for R {}
-        impl Access for W {}
-        impl Access for RW {}
-    }
-    pub trait Access: sealed::Access + Copy {}
-    impl Access for R {}
-    impl Access for W {}
-    impl Access for RW {}
-    pub trait Read: Access {}
-    impl Read for RW {}
-    impl Read for R {}
-    pub trait Write: Access {}
-    impl Write for RW {}
-    impl Write for W {}
+pub mod rng_v1 {
+    use crate::generic::*;
+    #[doc = "Random number generator"]
     #[derive(Copy, Clone)]
-    pub struct Reg<T: Copy, A: Access> {
-        ptr: *mut u8,
-        phantom: PhantomData<*mut (T, A)>,
-    }
-    unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
-    unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
-    impl<T: Copy, A: Access> Reg<T, A> {
-        pub fn from_ptr(ptr: *mut u8) -> Self {
-            Self {
-                ptr,
-                phantom: PhantomData,
-            }
+    pub struct Rng(pub *mut u8);
+    unsafe impl Send for Rng {}
+    unsafe impl Sync for Rng {}
+    impl Rng {
+        #[doc = "control register"]
+        pub fn cr(self) -> Reg<regs::Cr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        pub fn ptr(&self) -> *mut T {
-            self.ptr as _
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::Sr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-    }
-    impl<T: Copy, A: Read> Reg<T, A> {
-        pub unsafe fn read(&self) -> T {
-            (self.ptr as *mut T).read_volatile()
+        #[doc = "data register"]
+        pub fn dr(self) -> Reg<u32, R> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
     }
-    impl<T: Copy, A: Write> Reg<T, A> {
-        pub unsafe fn write_value(&self, val: T) {
-            (self.ptr as *mut T).write_volatile(val)
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "control register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr(pub u32);
+        impl Cr {
+            #[doc = "Random number generator enable"]
+            pub const fn rngen(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Random number generator enable"]
+            pub fn set_rngen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "Interrupt enable"]
+            pub const fn ie(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Interrupt enable"]
+            pub fn set_ie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
         }
-    }
-    impl<T: Default + Copy, A: Write> Reg<T, A> {
-        pub unsafe fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
-            let mut val = Default::default();
-            let res = f(&mut val);
-            self.write_value(val);
-            res
+        impl Default for Cr {
+            fn default() -> Cr {
+                Cr(0)
+            }
         }
-    }
-    impl<T: Copy, A: Read + Write> Reg<T, A> {
-        pub unsafe fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
-            let mut val = self.read();
-            let res = f(&mut val);
-            self.write_value(val);
-            res
+        #[doc = "status register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Sr(pub u32);
+        impl Sr {
+            #[doc = "Data ready"]
+            pub const fn drdy(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Data ready"]
+            pub fn set_drdy(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Clock error current status"]
+            pub const fn cecs(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Clock error current status"]
+            pub fn set_cecs(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Seed error current status"]
+            pub const fn secs(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Seed error current status"]
+            pub fn set_secs(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "Clock error interrupt status"]
+            pub const fn ceis(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Clock error interrupt status"]
+            pub fn set_ceis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Seed error interrupt status"]
+            pub const fn seis(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Seed error interrupt status"]
+            pub fn set_seis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+        }
+        impl Default for Sr {
+            fn default() -> Sr {
+                Sr(0)
+            }
         }
     }
 }
@@ -4947,69 +2961,6 @@ pub mod dma_v1 {
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ifcr(pub u32);
-        impl Ifcr {
-            #[doc = "Channel 1 Global interrupt clear"]
-            pub fn cgif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Channel 1 Global interrupt clear"]
-            pub fn set_cgif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Channel 1 Transfer Complete clear"]
-            pub fn ctcif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 1usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Channel 1 Transfer Complete clear"]
-            pub fn set_ctcif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 1usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Channel 1 Half Transfer clear"]
-            pub fn chtif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 2usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Channel 1 Half Transfer clear"]
-            pub fn set_chtif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 2usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Channel 1 Transfer Error clear"]
-            pub fn cteif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 3usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Channel 1 Transfer Error clear"]
-            pub fn set_cteif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 3usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for Ifcr {
-            fn default() -> Ifcr {
-                Ifcr(0)
-            }
-        }
         #[doc = "DMA interrupt status register (DMA_ISR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -5073,26 +3024,6 @@ pub mod dma_v1 {
                 Isr(0)
             }
         }
-        #[doc = "DMA channel 1 number of data register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ndtr(pub u32);
-        impl Ndtr {
-            #[doc = "Number of data to transfer"]
-            pub const fn ndt(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "Number of data to transfer"]
-            pub fn set_ndt(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
-        }
-        impl Default for Ndtr {
-            fn default() -> Ndtr {
-                Ndtr(0)
-            }
-        }
         #[doc = "DMA channel configuration register (DMA_CCR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -5212,355 +3143,87 @@ pub mod dma_v1 {
                 Cr(0)
             }
         }
-    }
-    pub mod vals {
-        use crate::generic::*;
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Memmem(pub u8);
-        impl Memmem {
-            #[doc = "Memory to memory mode disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Memory to memory mode enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Circ(pub u8);
-        impl Circ {
-            #[doc = "Circular buffer disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Circular buffer enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Inc(pub u8);
-        impl Inc {
-            #[doc = "Increment mode disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Increment mode enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dir(pub u8);
-        impl Dir {
-            #[doc = "Read from peripheral"]
-            pub const FROMPERIPHERAL: Self = Self(0);
-            #[doc = "Read from memory"]
-            pub const FROMMEMORY: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Size(pub u8);
-        impl Size {
-            #[doc = "8-bit size"]
-            pub const BITS8: Self = Self(0);
-            #[doc = "16-bit size"]
-            pub const BITS16: Self = Self(0x01);
-            #[doc = "32-bit size"]
-            pub const BITS32: Self = Self(0x02);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pl(pub u8);
-        impl Pl {
-            #[doc = "Low priority"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Medium priority"]
-            pub const MEDIUM: Self = Self(0x01);
-            #[doc = "High priority"]
-            pub const HIGH: Self = Self(0x02);
-            #[doc = "Very high priority"]
-            pub const VERYHIGH: Self = Self(0x03);
-        }
-    }
-}
-pub mod gpio_v2 {
-    use crate::generic::*;
-    #[doc = "General-purpose I/Os"]
-    #[derive(Copy, Clone)]
-    pub struct Gpio(pub *mut u8);
-    unsafe impl Send for Gpio {}
-    unsafe impl Sync for Gpio {}
-    impl Gpio {
-        #[doc = "GPIO port mode register"]
-        pub fn moder(self) -> Reg<regs::Moder, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "GPIO port output type register"]
-        pub fn otyper(self) -> Reg<regs::Otyper, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "GPIO port output speed register"]
-        pub fn ospeedr(self) -> Reg<regs::Ospeedr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "GPIO port pull-up/pull-down register"]
-        pub fn pupdr(self) -> Reg<regs::Pupdr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "GPIO port input data register"]
-        pub fn idr(self) -> Reg<regs::Idr, R> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "GPIO port output data register"]
-        pub fn odr(self) -> Reg<regs::Odr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-        #[doc = "GPIO port bit set/reset register"]
-        pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
-        }
-        #[doc = "GPIO port configuration lock register"]
-        pub fn lckr(self) -> Reg<regs::Lckr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(28usize)) }
-        }
-        #[doc = "GPIO alternate function register (low, high)"]
-        pub fn afr(self, n: usize) -> Reg<regs::Afr, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) }
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "GPIO port input data register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Idr(pub u32);
-        impl Idr {
-            #[doc = "Port input data (y = 0..15)"]
-            pub fn idr(&self, n: usize) -> super::vals::Idr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Idr(val as u8)
-            }
-            #[doc = "Port input data (y = 0..15)"]
-            pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for Idr {
-            fn default() -> Idr {
-                Idr(0)
-            }
-        }
-        #[doc = "GPIO port pull-up/pull-down register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pupdr(pub u32);
-        impl Pupdr {
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn pupdr(&self, n: usize) -> super::vals::Pupdr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Pupdr(val as u8)
-            }
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-        }
-        impl Default for Pupdr {
-            fn default() -> Pupdr {
-                Pupdr(0)
-            }
-        }
-        #[doc = "GPIO port output type register"]
+        #[doc = "DMA channel 1 number of data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Otyper(pub u32);
-        impl Otyper {
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn ot(&self, n: usize) -> super::vals::Ot {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Ot(val as u8)
+        pub struct Ndtr(pub u32);
+        impl Ndtr {
+            #[doc = "Number of data to transfer"]
+            pub const fn ndt(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
             }
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "Number of data to transfer"]
+            pub fn set_ndt(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Otyper {
-            fn default() -> Otyper {
-                Otyper(0)
+        impl Default for Ndtr {
+            fn default() -> Ndtr {
+                Ndtr(0)
             }
         }
-        #[doc = "GPIO port bit set/reset register"]
+        #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Bsrr(pub u32);
-        impl Bsrr {
-            #[doc = "Port x set bit y (y= 0..15)"]
-            pub fn bs(&self, n: usize) -> bool {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+        pub struct Ifcr(pub u32);
+        impl Ifcr {
+            #[doc = "Channel 1 Global interrupt clear"]
+            pub fn cgif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 0usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Port x set bit y (y= 0..15)"]
-            pub fn set_bs(&mut self, n: usize, val: bool) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Channel 1 Global interrupt clear"]
+            pub fn set_cgif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 0usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Port x set bit y (y= 0..15)"]
-            pub fn br(&self, n: usize) -> bool {
-                assert!(n < 16usize);
-                let offs = 16usize + n * 1usize;
+            #[doc = "Channel 1 Transfer Complete clear"]
+            pub fn ctcif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 1usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Port x set bit y (y= 0..15)"]
-            pub fn set_br(&mut self, n: usize, val: bool) {
-                assert!(n < 16usize);
-                let offs = 16usize + n * 1usize;
+            #[doc = "Channel 1 Transfer Complete clear"]
+            pub fn set_ctcif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 1usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-        }
-        impl Default for Bsrr {
-            fn default() -> Bsrr {
-                Bsrr(0)
-            }
-        }
-        #[doc = "GPIO port configuration lock register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Lckr(pub u32);
-        impl Lckr {
-            #[doc = "Port x lock bit y (y= 0..15)"]
-            pub fn lck(&self, n: usize) -> super::vals::Lck {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Channel 1 Half Transfer clear"]
+            pub fn chtif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 2usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
-                super::vals::Lck(val as u8)
-            }
-            #[doc = "Port x lock bit y (y= 0..15)"]
-            pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-            #[doc = "Port x lock bit y (y= 0..15)"]
-            pub const fn lckk(&self) -> super::vals::Lckk {
-                let val = (self.0 >> 16usize) & 0x01;
-                super::vals::Lckk(val as u8)
-            }
-            #[doc = "Port x lock bit y (y= 0..15)"]
-            pub fn set_lckk(&mut self, val: super::vals::Lckk) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
-            }
-        }
-        impl Default for Lckr {
-            fn default() -> Lckr {
-                Lckr(0)
-            }
-        }
-        #[doc = "GPIO port mode register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Moder(pub u32);
-        impl Moder {
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn moder(&self, n: usize) -> super::vals::Moder {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Moder(val as u8)
-            }
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+                val != 0
             }
-        }
-        impl Default for Moder {
-            fn default() -> Moder {
-                Moder(0)
+            #[doc = "Channel 1 Half Transfer clear"]
+            pub fn set_chtif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 2usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-        }
-        #[doc = "GPIO port output data register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Odr(pub u32);
-        impl Odr {
-            #[doc = "Port output data (y = 0..15)"]
-            pub fn odr(&self, n: usize) -> super::vals::Odr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Channel 1 Transfer Error clear"]
+            pub fn cteif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 3usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
-                super::vals::Odr(val as u8)
-            }
-            #[doc = "Port output data (y = 0..15)"]
-            pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for Odr {
-            fn default() -> Odr {
-                Odr(0)
-            }
-        }
-        #[doc = "GPIO alternate function register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Afr(pub u32);
-        impl Afr {
-            #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
-            pub fn afr(&self, n: usize) -> super::vals::Afr {
-                assert!(n < 8usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x0f;
-                super::vals::Afr(val as u8)
-            }
-            #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
-            pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) {
-                assert!(n < 8usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
-            }
-        }
-        impl Default for Afr {
-            fn default() -> Afr {
-                Afr(0)
-            }
-        }
-        #[doc = "GPIO port output speed register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ospeedr(pub u32);
-        impl Ospeedr {
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Ospeedr(val as u8)
+                val != 0
             }
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            #[doc = "Channel 1 Transfer Error clear"]
+            pub fn set_cteif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 3usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Ospeedr {
-            fn default() -> Ospeedr {
-                Ospeedr(0)
+        impl Default for Ifcr {
+            fn default() -> Ifcr {
+                Ifcr(0)
             }
         }
     }
@@ -5568,1269 +3231,1922 @@ pub mod gpio_v2 {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Idr(pub u8);
-        impl Idr {
-            #[doc = "Input is logic low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Input is logic high"]
-            pub const HIGH: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Bsw(pub u8);
-        impl Bsw {
-            #[doc = "Sets the corresponding ODRx bit"]
-            pub const SET: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lckk(pub u8);
-        impl Lckk {
-            #[doc = "Port configuration lock key not active"]
-            pub const NOTACTIVE: Self = Self(0);
-            #[doc = "Port configuration lock key active"]
-            pub const ACTIVE: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lck(pub u8);
-        impl Lck {
-            #[doc = "Port configuration not locked"]
-            pub const UNLOCKED: Self = Self(0);
-            #[doc = "Port configuration locked"]
-            pub const LOCKED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Brw(pub u8);
-        impl Brw {
-            #[doc = "Resets the corresponding ODRx bit"]
-            pub const RESET: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ospeedr(pub u8);
-        impl Ospeedr {
-            #[doc = "Low speed"]
-            pub const LOWSPEED: Self = Self(0);
-            #[doc = "Medium speed"]
-            pub const MEDIUMSPEED: Self = Self(0x01);
-            #[doc = "High speed"]
-            pub const HIGHSPEED: Self = Self(0x02);
-            #[doc = "Very high speed"]
-            pub const VERYHIGHSPEED: Self = Self(0x03);
+        pub struct Dir(pub u8);
+        impl Dir {
+            #[doc = "Read from peripheral"]
+            pub const FROMPERIPHERAL: Self = Self(0);
+            #[doc = "Read from memory"]
+            pub const FROMMEMORY: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ot(pub u8);
-        impl Ot {
-            #[doc = "Output push-pull (reset state)"]
-            pub const PUSHPULL: Self = Self(0);
-            #[doc = "Output open-drain"]
-            pub const OPENDRAIN: Self = Self(0x01);
+        pub struct Inc(pub u8);
+        impl Inc {
+            #[doc = "Increment mode disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Increment mode enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Afr(pub u8);
-        impl Afr {
-            #[doc = "AF0"]
-            pub const AF0: Self = Self(0);
-            #[doc = "AF1"]
-            pub const AF1: Self = Self(0x01);
-            #[doc = "AF2"]
-            pub const AF2: Self = Self(0x02);
-            #[doc = "AF3"]
-            pub const AF3: Self = Self(0x03);
-            #[doc = "AF4"]
-            pub const AF4: Self = Self(0x04);
-            #[doc = "AF5"]
-            pub const AF5: Self = Self(0x05);
-            #[doc = "AF6"]
-            pub const AF6: Self = Self(0x06);
-            #[doc = "AF7"]
-            pub const AF7: Self = Self(0x07);
-            #[doc = "AF8"]
-            pub const AF8: Self = Self(0x08);
-            #[doc = "AF9"]
-            pub const AF9: Self = Self(0x09);
-            #[doc = "AF10"]
-            pub const AF10: Self = Self(0x0a);
-            #[doc = "AF11"]
-            pub const AF11: Self = Self(0x0b);
-            #[doc = "AF12"]
-            pub const AF12: Self = Self(0x0c);
-            #[doc = "AF13"]
-            pub const AF13: Self = Self(0x0d);
-            #[doc = "AF14"]
-            pub const AF14: Self = Self(0x0e);
-            #[doc = "AF15"]
-            pub const AF15: Self = Self(0x0f);
+        pub struct Circ(pub u8);
+        impl Circ {
+            #[doc = "Circular buffer disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Circular buffer enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Moder(pub u8);
-        impl Moder {
-            #[doc = "Input mode (reset state)"]
-            pub const INPUT: Self = Self(0);
-            #[doc = "General purpose output mode"]
-            pub const OUTPUT: Self = Self(0x01);
-            #[doc = "Alternate function mode"]
-            pub const ALTERNATE: Self = Self(0x02);
-            #[doc = "Analog mode"]
-            pub const ANALOG: Self = Self(0x03);
+        pub struct Pl(pub u8);
+        impl Pl {
+            #[doc = "Low priority"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Medium priority"]
+            pub const MEDIUM: Self = Self(0x01);
+            #[doc = "High priority"]
+            pub const HIGH: Self = Self(0x02);
+            #[doc = "Very high priority"]
+            pub const VERYHIGH: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Odr(pub u8);
-        impl Odr {
-            #[doc = "Set output to logic low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Set output to logic high"]
-            pub const HIGH: Self = Self(0x01);
+        pub struct Memmem(pub u8);
+        impl Memmem {
+            #[doc = "Memory to memory mode disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Memory to memory mode enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pupdr(pub u8);
-        impl Pupdr {
-            #[doc = "No pull-up, pull-down"]
-            pub const FLOATING: Self = Self(0);
-            #[doc = "Pull-up"]
-            pub const PULLUP: Self = Self(0x01);
-            #[doc = "Pull-down"]
-            pub const PULLDOWN: Self = Self(0x02);
+        pub struct Size(pub u8);
+        impl Size {
+            #[doc = "8-bit size"]
+            pub const BITS8: Self = Self(0);
+            #[doc = "16-bit size"]
+            pub const BITS16: Self = Self(0x01);
+            #[doc = "32-bit size"]
+            pub const BITS32: Self = Self(0x02);
         }
     }
 }
-pub mod exti_v1 {
+pub mod syscfg_f4 {
     use crate::generic::*;
-    #[doc = "External interrupt/event controller"]
+    #[doc = "System configuration controller"]
     #[derive(Copy, Clone)]
-    pub struct Exti(pub *mut u8);
-    unsafe impl Send for Exti {}
-    unsafe impl Sync for Exti {}
-    impl Exti {
-        #[doc = "Interrupt mask register (EXTI_IMR)"]
-        pub fn imr(self) -> Reg<regs::Imr, RW> {
+    pub struct Syscfg(pub *mut u8);
+    unsafe impl Send for Syscfg {}
+    unsafe impl Sync for Syscfg {}
+    impl Syscfg {
+        #[doc = "memory remap register"]
+        pub fn memrm(self) -> Reg<regs::Memrm, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        #[doc = "Event mask register (EXTI_EMR)"]
-        pub fn emr(self) -> Reg<regs::Emr, RW> {
+        #[doc = "peripheral mode configuration register"]
+        pub fn pmc(self) -> Reg<regs::Pmc, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
-        pub fn rtsr(self) -> Reg<regs::Rtsr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
-        pub fn ftsr(self) -> Reg<regs::Ftsr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "Software interrupt event register (EXTI_SWIER)"]
-        pub fn swier(self) -> Reg<regs::Swier, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        #[doc = "external interrupt configuration register"]
+        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
         }
-        #[doc = "Pending register (EXTI_PR)"]
-        pub fn pr(self) -> Reg<regs::Pr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        #[doc = "Compensation cell control register"]
+        pub fn cmpcr(self) -> Reg<regs::Cmpcr, R> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
+        #[doc = "peripheral mode configuration register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Rtsr(pub u32);
-        impl Rtsr {
-            #[doc = "Rising trigger event configuration of line 0"]
-            pub fn tr(&self, n: usize) -> super::vals::Tr {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Tr(val as u8)
+        pub struct Pmc(pub u32);
+        impl Pmc {
+            #[doc = "ADC1DC2"]
+            pub const fn adc1dc2(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
+                val != 0
             }
-            #[doc = "Rising trigger event configuration of line 0"]
-            pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "ADC1DC2"]
+            pub fn set_adc1dc2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
-        }
-        impl Default for Rtsr {
-            fn default() -> Rtsr {
-                Rtsr(0)
+            #[doc = "ADC2DC2"]
+            pub const fn adc2dc2(&self) -> bool {
+                let val = (self.0 >> 17usize) & 0x01;
+                val != 0
             }
-        }
-        #[doc = "Interrupt mask register (EXTI_IMR)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Imr(pub u32);
-        impl Imr {
-            #[doc = "Interrupt Mask on line 0"]
-            pub fn mr(&self, n: usize) -> super::vals::Mr {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Mr(val as u8)
+            #[doc = "ADC2DC2"]
+            pub fn set_adc2dc2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
             }
-            #[doc = "Interrupt Mask on line 0"]
-            pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "ADC3DC2"]
+            pub const fn adc3dc2(&self) -> bool {
+                let val = (self.0 >> 18usize) & 0x01;
+                val != 0
             }
-        }
-        impl Default for Imr {
-            fn default() -> Imr {
-                Imr(0)
+            #[doc = "ADC3DC2"]
+            pub fn set_adc3dc2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
             }
-        }
-        #[doc = "Software interrupt event register (EXTI_SWIER)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Swier(pub u32);
-        impl Swier {
-            #[doc = "Software Interrupt on line 0"]
-            pub fn swier(&self, n: usize) -> bool {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Ethernet PHY interface selection"]
+            pub const fn mii_rmii_sel(&self) -> bool {
+                let val = (self.0 >> 23usize) & 0x01;
                 val != 0
             }
-            #[doc = "Software Interrupt on line 0"]
-            pub fn set_swier(&mut self, n: usize, val: bool) {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Ethernet PHY interface selection"]
+            pub fn set_mii_rmii_sel(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
             }
         }
-        impl Default for Swier {
-            fn default() -> Swier {
-                Swier(0)
+        impl Default for Pmc {
+            fn default() -> Pmc {
+                Pmc(0)
             }
         }
-        #[doc = "Event mask register (EXTI_EMR)"]
+        #[doc = "external interrupt configuration register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Emr(pub u32);
-        impl Emr {
-            #[doc = "Event Mask on line 0"]
-            pub fn mr(&self, n: usize) -> super::vals::Mr {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Mr(val as u8)
+        pub struct Exticr(pub u32);
+        impl Exticr {
+            #[doc = "EXTI x configuration"]
+            pub fn exti(&self, n: usize) -> u8 {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x0f;
+                val as u8
             }
-            #[doc = "Event Mask on line 0"]
-            pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "EXTI x configuration"]
+            pub fn set_exti(&mut self, n: usize, val: u8) {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
             }
         }
-        impl Default for Emr {
-            fn default() -> Emr {
-                Emr(0)
+        impl Default for Exticr {
+            fn default() -> Exticr {
+                Exticr(0)
             }
         }
-        #[doc = "Pending register (EXTI_PR)"]
+        #[doc = "Compensation cell control register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pr(pub u32);
-        impl Pr {
-            #[doc = "Pending bit 0"]
-            pub fn pr(&self, n: usize) -> bool {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
+        pub struct Cmpcr(pub u32);
+        impl Cmpcr {
+            #[doc = "Compensation cell power-down"]
+            pub const fn cmp_pd(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Pending bit 0"]
-            pub fn set_pr(&mut self, n: usize, val: bool) {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Compensation cell power-down"]
+            pub fn set_cmp_pd(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "READY"]
+            pub const fn ready(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "READY"]
+            pub fn set_ready(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
         }
-        impl Default for Pr {
-            fn default() -> Pr {
-                Pr(0)
+        impl Default for Cmpcr {
+            fn default() -> Cmpcr {
+                Cmpcr(0)
             }
         }
-        #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
+        #[doc = "memory remap register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ftsr(pub u32);
-        impl Ftsr {
-            #[doc = "Falling trigger event configuration of line 0"]
-            pub fn tr(&self, n: usize) -> super::vals::Tr {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Tr(val as u8)
+        pub struct Memrm(pub u32);
+        impl Memrm {
+            #[doc = "Memory mapping selection"]
+            pub const fn mem_mode(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x07;
+                val as u8
             }
-            #[doc = "Falling trigger event configuration of line 0"]
-            pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "Memory mapping selection"]
+            pub fn set_mem_mode(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
             }
-        }
-        impl Default for Ftsr {
-            fn default() -> Ftsr {
-                Ftsr(0)
+            #[doc = "Flash bank mode selection"]
+            pub const fn fb_mode(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Flash bank mode selection"]
+            pub fn set_fb_mode(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "FMC memory mapping swap"]
+            pub const fn swp_fmc(&self) -> u8 {
+                let val = (self.0 >> 10usize) & 0x03;
+                val as u8
+            }
+            #[doc = "FMC memory mapping swap"]
+            pub fn set_swp_fmc(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
             }
         }
-    }
-    pub mod vals {
-        use crate::generic::*;
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Prw(pub u8);
-        impl Prw {
-            #[doc = "Clears pending bit"]
-            pub const CLEAR: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Prr(pub u8);
-        impl Prr {
-            #[doc = "No trigger request occurred"]
-            pub const NOTPENDING: Self = Self(0);
-            #[doc = "Selected trigger request occurred"]
-            pub const PENDING: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Tr(pub u8);
-        impl Tr {
-            #[doc = "Falling edge trigger is disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Falling edge trigger is enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mr(pub u8);
-        impl Mr {
-            #[doc = "Interrupt request line is masked"]
-            pub const MASKED: Self = Self(0);
-            #[doc = "Interrupt request line is unmasked"]
-            pub const UNMASKED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Swierw(pub u8);
-        impl Swierw {
-            #[doc = "Generates an interrupt request"]
-            pub const PEND: Self = Self(0x01);
+        impl Default for Memrm {
+            fn default() -> Memrm {
+                Memrm(0)
+            }
         }
     }
 }
-pub mod usart_v1 {
+pub mod syscfg_h7 {
     use crate::generic::*;
-    #[doc = "Universal synchronous asynchronous receiver transmitter"]
+    #[doc = "System configuration controller"]
     #[derive(Copy, Clone)]
-    pub struct Usart(pub *mut u8);
-    unsafe impl Send for Usart {}
-    unsafe impl Sync for Usart {}
-    impl Usart {
-        #[doc = "Status register"]
-        pub fn sr(self) -> Reg<regs::Sr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "Data register"]
-        pub fn dr(self) -> Reg<regs::Dr, RW> {
+    pub struct Syscfg(pub *mut u8);
+    unsafe impl Send for Syscfg {}
+    unsafe impl Sync for Syscfg {}
+    impl Syscfg {
+        #[doc = "peripheral mode configuration register"]
+        pub fn pmcr(self) -> Reg<regs::Pmcr, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "Baud rate register"]
-        pub fn brr(self) -> Reg<regs::Brr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        #[doc = "external interrupt configuration register 1"]
+        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
         }
-        #[doc = "Control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        #[doc = "compensation cell control/status register"]
+        pub fn cccsr(self) -> Reg<regs::Cccsr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
         }
-        #[doc = "Control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2Usart, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        #[doc = "SYSCFG compensation cell value register"]
+        pub fn ccvr(self) -> Reg<regs::Ccvr, R> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
         }
-        #[doc = "Control register 3"]
-        pub fn cr3(self) -> Reg<regs::Cr3Usart, RW> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        #[doc = "SYSCFG compensation cell code register"]
+        pub fn cccr(self) -> Reg<regs::Cccr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(40usize)) }
         }
-        #[doc = "Guard time and prescaler register"]
-        pub fn gtpr(self) -> Reg<regs::Gtpr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        #[doc = "SYSCFG power control register"]
+        pub fn pwrcr(self) -> Reg<regs::Pwrcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(44usize)) }
         }
-    }
-    #[doc = "Universal asynchronous receiver transmitter"]
-    #[derive(Copy, Clone)]
-    pub struct Uart(pub *mut u8);
-    unsafe impl Send for Uart {}
-    unsafe impl Sync for Uart {}
-    impl Uart {
-        #[doc = "Status register"]
-        pub fn sr(self) -> Reg<regs::Sr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        #[doc = "SYSCFG package register"]
+        pub fn pkgr(self) -> Reg<regs::Pkgr, R> {
+            unsafe { Reg::from_ptr(self.0.add(292usize)) }
         }
-        #[doc = "Data register"]
-        pub fn dr(self) -> Reg<regs::Dr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        #[doc = "SYSCFG user register 0"]
+        pub fn ur0(self) -> Reg<regs::Ur0, R> {
+            unsafe { Reg::from_ptr(self.0.add(768usize)) }
         }
-        #[doc = "Baud rate register"]
-        pub fn brr(self) -> Reg<regs::Brr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        #[doc = "SYSCFG user register 2"]
+        pub fn ur2(self) -> Reg<regs::Ur2, RW> {
+            unsafe { Reg::from_ptr(self.0.add(776usize)) }
         }
-        #[doc = "Control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        #[doc = "SYSCFG user register 3"]
+        pub fn ur3(self) -> Reg<regs::Ur3, RW> {
+            unsafe { Reg::from_ptr(self.0.add(780usize)) }
         }
-        #[doc = "Control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        #[doc = "SYSCFG user register 4"]
+        pub fn ur4(self) -> Reg<regs::Ur4, R> {
+            unsafe { Reg::from_ptr(self.0.add(784usize)) }
         }
-        #[doc = "Control register 3"]
-        pub fn cr3(self) -> Reg<regs::Cr3, RW> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        #[doc = "SYSCFG user register 5"]
+        pub fn ur5(self) -> Reg<regs::Ur5, R> {
+            unsafe { Reg::from_ptr(self.0.add(788usize)) }
         }
-    }
-    pub mod vals {
-        use crate::generic::*;
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Hdsel(pub u8);
-        impl Hdsel {
-            #[doc = "Half duplex mode is not selected"]
-            pub const FULLDUPLEX: Self = Self(0);
-            #[doc = "Half duplex mode is selected"]
-            pub const HALFDUPLEX: Self = Self(0x01);
+        #[doc = "SYSCFG user register 6"]
+        pub fn ur6(self) -> Reg<regs::Ur6, R> {
+            unsafe { Reg::from_ptr(self.0.add(792usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct M(pub u8);
-        impl M {
-            #[doc = "8 data bits"]
-            pub const M8: Self = Self(0);
-            #[doc = "9 data bits"]
-            pub const M9: Self = Self(0x01);
+        #[doc = "SYSCFG user register 7"]
+        pub fn ur7(self) -> Reg<regs::Ur7, R> {
+            unsafe { Reg::from_ptr(self.0.add(796usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cpol(pub u8);
-        impl Cpol {
-            #[doc = "Steady low value on CK pin outside transmission window"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Steady high value on CK pin outside transmission window"]
-            pub const HIGH: Self = Self(0x01);
+        #[doc = "SYSCFG user register 8"]
+        pub fn ur8(self) -> Reg<regs::Ur8, R> {
+            unsafe { Reg::from_ptr(self.0.add(800usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Rwu(pub u8);
-        impl Rwu {
-            #[doc = "Receiver in active mode"]
-            pub const ACTIVE: Self = Self(0);
-            #[doc = "Receiver in mute mode"]
-            pub const MUTE: Self = Self(0x01);
+        #[doc = "SYSCFG user register 9"]
+        pub fn ur9(self) -> Reg<regs::Ur9, R> {
+            unsafe { Reg::from_ptr(self.0.add(804usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ps(pub u8);
-        impl Ps {
-            #[doc = "Even parity"]
-            pub const EVEN: Self = Self(0);
-            #[doc = "Odd parity"]
-            pub const ODD: Self = Self(0x01);
+        #[doc = "SYSCFG user register 10"]
+        pub fn ur10(self) -> Reg<regs::Ur10, R> {
+            unsafe { Reg::from_ptr(self.0.add(808usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Irlp(pub u8);
-        impl Irlp {
-            #[doc = "Normal mode"]
-            pub const NORMAL: Self = Self(0);
-            #[doc = "Low-power mode"]
-            pub const LOWPOWER: Self = Self(0x01);
+        #[doc = "SYSCFG user register 11"]
+        pub fn ur11(self) -> Reg<regs::Ur11, R> {
+            unsafe { Reg::from_ptr(self.0.add(812usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Stop(pub u8);
-        impl Stop {
-            #[doc = "1 stop bit"]
-            pub const STOP1: Self = Self(0);
-            #[doc = "0.5 stop bits"]
-            pub const STOP0P5: Self = Self(0x01);
-            #[doc = "2 stop bits"]
-            pub const STOP2: Self = Self(0x02);
-            #[doc = "1.5 stop bits"]
-            pub const STOP1P5: Self = Self(0x03);
+        #[doc = "SYSCFG user register 12"]
+        pub fn ur12(self) -> Reg<regs::Ur12, R> {
+            unsafe { Reg::from_ptr(self.0.add(816usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cpha(pub u8);
-        impl Cpha {
-            #[doc = "The first clock transition is the first data capture edge"]
-            pub const FIRST: Self = Self(0);
-            #[doc = "The second clock transition is the first data capture edge"]
-            pub const SECOND: Self = Self(0x01);
+        #[doc = "SYSCFG user register 13"]
+        pub fn ur13(self) -> Reg<regs::Ur13, R> {
+            unsafe { Reg::from_ptr(self.0.add(820usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Wake(pub u8);
-        impl Wake {
-            #[doc = "USART wakeup on idle line"]
-            pub const IDLELINE: Self = Self(0);
-            #[doc = "USART wakeup on address mark"]
-            pub const ADDRESSMARK: Self = Self(0x01);
+        #[doc = "SYSCFG user register 14"]
+        pub fn ur14(self) -> Reg<regs::Ur14, RW> {
+            unsafe { Reg::from_ptr(self.0.add(824usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lbdl(pub u8);
-        impl Lbdl {
-            #[doc = "10-bit break detection"]
-            pub const LBDL10: Self = Self(0);
-            #[doc = "11-bit break detection"]
-            pub const LBDL11: Self = Self(0x01);
+        #[doc = "SYSCFG user register 15"]
+        pub fn ur15(self) -> Reg<regs::Ur15, R> {
+            unsafe { Reg::from_ptr(self.0.add(828usize)) }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Sbk(pub u8);
-        impl Sbk {
-            #[doc = "No break character is transmitted"]
-            pub const NOBREAK: Self = Self(0);
-            #[doc = "Break character transmitted"]
-            pub const BREAK: Self = Self(0x01);
+        #[doc = "SYSCFG user register 16"]
+        pub fn ur16(self) -> Reg<regs::Ur16, R> {
+            unsafe { Reg::from_ptr(self.0.add(832usize)) }
+        }
+        #[doc = "SYSCFG user register 17"]
+        pub fn ur17(self) -> Reg<regs::Ur17, R> {
+            unsafe { Reg::from_ptr(self.0.add(836usize)) }
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "Status register"]
+        #[doc = "SYSCFG user register 13"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Sr(pub u32);
-        impl Sr {
-            #[doc = "Parity error"]
-            pub const fn pe(&self) -> bool {
+        pub struct Ur13(pub u32);
+        impl Ur13 {
+            #[doc = "Secured DTCM RAM Size"]
+            pub const fn sdrs(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x03;
+                val as u8
+            }
+            #[doc = "Secured DTCM RAM Size"]
+            pub fn set_sdrs(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+            }
+            #[doc = "D1 Standby reset"]
+            pub const fn d1sbrst(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
+                val != 0
+            }
+            #[doc = "D1 Standby reset"]
+            pub fn set_d1sbrst(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            }
+        }
+        impl Default for Ur13 {
+            fn default() -> Ur13 {
+                Ur13(0)
+            }
+        }
+        #[doc = "peripheral mode configuration register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Pmcr(pub u32);
+        impl Pmcr {
+            #[doc = "I2C1 Fm+"]
+            pub const fn i2c1fmp(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Parity error"]
-            pub fn set_pe(&mut self, val: bool) {
+            #[doc = "I2C1 Fm+"]
+            pub fn set_i2c1fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Framing error"]
-            pub const fn fe(&self) -> bool {
+            #[doc = "I2C2 Fm+"]
+            pub const fn i2c2fmp(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Framing error"]
-            pub fn set_fe(&mut self, val: bool) {
+            #[doc = "I2C2 Fm+"]
+            pub fn set_i2c2fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Noise error flag"]
-            pub const fn ne(&self) -> bool {
+            #[doc = "I2C3 Fm+"]
+            pub const fn i2c3fmp(&self) -> bool {
                 let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Noise error flag"]
-            pub fn set_ne(&mut self, val: bool) {
+            #[doc = "I2C3 Fm+"]
+            pub fn set_i2c3fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Overrun error"]
-            pub const fn ore(&self) -> bool {
+            #[doc = "I2C4 Fm+"]
+            pub const fn i2c4fmp(&self) -> bool {
                 let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "Overrun error"]
-            pub fn set_ore(&mut self, val: bool) {
+            #[doc = "I2C4 Fm+"]
+            pub fn set_i2c4fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-            #[doc = "IDLE line detected"]
-            pub const fn idle(&self) -> bool {
+            #[doc = "PB(6) Fm+"]
+            pub const fn pb6fmp(&self) -> bool {
                 let val = (self.0 >> 4usize) & 0x01;
                 val != 0
             }
-            #[doc = "IDLE line detected"]
-            pub fn set_idle(&mut self, val: bool) {
+            #[doc = "PB(6) Fm+"]
+            pub fn set_pb6fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "Read data register not empty"]
-            pub const fn rxne(&self) -> bool {
+            #[doc = "PB(7) Fast Mode Plus"]
+            pub const fn pb7fmp(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Read data register not empty"]
-            pub fn set_rxne(&mut self, val: bool) {
+            #[doc = "PB(7) Fast Mode Plus"]
+            pub fn set_pb7fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Transmission complete"]
-            pub const fn tc(&self) -> bool {
+            #[doc = "PB(8) Fast Mode Plus"]
+            pub const fn pb8fmp(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transmission complete"]
-            pub fn set_tc(&mut self, val: bool) {
+            #[doc = "PB(8) Fast Mode Plus"]
+            pub fn set_pb8fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Transmit data register empty"]
-            pub const fn txe(&self) -> bool {
+            #[doc = "PB(9) Fm+"]
+            pub const fn pb9fmp(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transmit data register empty"]
-            pub fn set_txe(&mut self, val: bool) {
+            #[doc = "PB(9) Fm+"]
+            pub fn set_pb9fmp(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "LIN break detection flag"]
-            pub const fn lbd(&self) -> bool {
+            #[doc = "Booster Enable"]
+            pub const fn booste(&self) -> bool {
                 let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "LIN break detection flag"]
-            pub fn set_lbd(&mut self, val: bool) {
+            #[doc = "Booster Enable"]
+            pub fn set_booste(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
+            #[doc = "Analog switch supply voltage selection"]
+            pub const fn boostvddsel(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Analog switch supply voltage selection"]
+            pub fn set_boostvddsel(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            }
+            #[doc = "Ethernet PHY Interface Selection"]
+            pub const fn epis(&self) -> u8 {
+                let val = (self.0 >> 21usize) & 0x07;
+                val as u8
+            }
+            #[doc = "Ethernet PHY Interface Selection"]
+            pub fn set_epis(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize);
+            }
+            #[doc = "PA0 Switch Open"]
+            pub const fn pa0so(&self) -> bool {
+                let val = (self.0 >> 24usize) & 0x01;
+                val != 0
+            }
+            #[doc = "PA0 Switch Open"]
+            pub fn set_pa0so(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+            }
+            #[doc = "PA1 Switch Open"]
+            pub const fn pa1so(&self) -> bool {
+                let val = (self.0 >> 25usize) & 0x01;
+                val != 0
+            }
+            #[doc = "PA1 Switch Open"]
+            pub fn set_pa1so(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+            }
+            #[doc = "PC2 Switch Open"]
+            pub const fn pc2so(&self) -> bool {
+                let val = (self.0 >> 26usize) & 0x01;
+                val != 0
+            }
+            #[doc = "PC2 Switch Open"]
+            pub fn set_pc2so(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+            }
+            #[doc = "PC3 Switch Open"]
+            pub const fn pc3so(&self) -> bool {
+                let val = (self.0 >> 27usize) & 0x01;
+                val != 0
+            }
+            #[doc = "PC3 Switch Open"]
+            pub fn set_pc3so(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+            }
         }
-        impl Default for Sr {
-            fn default() -> Sr {
-                Sr(0)
+        impl Default for Pmcr {
+            fn default() -> Pmcr {
+                Pmcr(0)
             }
         }
-        #[doc = "Control register 2"]
+        #[doc = "SYSCFG user register 2"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2(pub u32);
-        impl Cr2 {
-            #[doc = "Address of the USART node"]
-            pub const fn add(&self) -> u8 {
+        pub struct Ur2(pub u32);
+        impl Ur2 {
+            #[doc = "BOR_LVL Brownout Reset Threshold Level"]
+            pub const fn borh(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x03;
+                val as u8
+            }
+            #[doc = "BOR_LVL Brownout Reset Threshold Level"]
+            pub fn set_borh(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+            }
+            #[doc = "Boot Address 0"]
+            pub const fn boot_add0(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Boot Address 0"]
+            pub fn set_boot_add0(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+            }
+        }
+        impl Default for Ur2 {
+            fn default() -> Ur2 {
+                Ur2(0)
+            }
+        }
+        #[doc = "SYSCFG user register 6"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur6(pub u32);
+        impl Ur6 {
+            #[doc = "Protected area start address for bank 1"]
+            pub const fn pa_beg_1(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x0fff;
+                val as u16
+            }
+            #[doc = "Protected area start address for bank 1"]
+            pub fn set_pa_beg_1(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+            }
+            #[doc = "Protected area end address for bank 1"]
+            pub const fn pa_end_1(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0x0fff;
+                val as u16
+            }
+            #[doc = "Protected area end address for bank 1"]
+            pub fn set_pa_end_1(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
+            }
+        }
+        impl Default for Ur6 {
+            fn default() -> Ur6 {
+                Ur6(0)
+            }
+        }
+        #[doc = "SYSCFG power control register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Pwrcr(pub u32);
+        impl Pwrcr {
+            #[doc = "Overdrive enable"]
+            pub const fn oden(&self) -> u8 {
                 let val = (self.0 >> 0usize) & 0x0f;
                 val as u8
             }
-            #[doc = "Address of the USART node"]
-            pub fn set_add(&mut self, val: u8) {
+            #[doc = "Overdrive enable"]
+            pub fn set_oden(&mut self, val: u8) {
                 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
             }
-            #[doc = "lin break detection length"]
-            pub const fn lbdl(&self) -> super::vals::Lbdl {
-                let val = (self.0 >> 5usize) & 0x01;
-                super::vals::Lbdl(val as u8)
+        }
+        impl Default for Pwrcr {
+            fn default() -> Pwrcr {
+                Pwrcr(0)
             }
-            #[doc = "lin break detection length"]
-            pub fn set_lbdl(&mut self, val: super::vals::Lbdl) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
+        }
+        #[doc = "SYSCFG user register 17"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur17(pub u32);
+        impl Ur17 {
+            #[doc = "I/O high speed / low voltage"]
+            pub const fn io_hslv(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "LIN break detection interrupt enable"]
-            pub const fn lbdie(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
+            #[doc = "I/O high speed / low voltage"]
+            pub fn set_io_hslv(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+        }
+        impl Default for Ur17 {
+            fn default() -> Ur17 {
+                Ur17(0)
+            }
+        }
+        #[doc = "SYSCFG user register 12"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur12(pub u32);
+        impl Ur12 {
+            #[doc = "Secure mode"]
+            pub const fn secure(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "LIN break detection interrupt enable"]
-            pub fn set_lbdie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            #[doc = "Secure mode"]
+            pub fn set_secure(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
-            #[doc = "STOP bits"]
-            pub const fn stop(&self) -> super::vals::Stop {
-                let val = (self.0 >> 12usize) & 0x03;
-                super::vals::Stop(val as u8)
+        }
+        impl Default for Ur12 {
+            fn default() -> Ur12 {
+                Ur12(0)
             }
-            #[doc = "STOP bits"]
-            pub fn set_stop(&mut self, val: super::vals::Stop) {
-                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+        }
+        #[doc = "SYSCFG user register 11"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur11(pub u32);
+        impl Ur11 {
+            #[doc = "Secured area end address for bank 2"]
+            pub const fn sa_end_2(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x0fff;
+                val as u16
             }
-            #[doc = "LIN mode enable"]
-            pub const fn linen(&self) -> bool {
-                let val = (self.0 >> 14usize) & 0x01;
+            #[doc = "Secured area end address for bank 2"]
+            pub fn set_sa_end_2(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+            }
+            #[doc = "Independent Watchdog 1 mode"]
+            pub const fn iwdg1m(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "LIN mode enable"]
-            pub fn set_linen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            #[doc = "Independent Watchdog 1 mode"]
+            pub fn set_iwdg1m(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
         }
-        impl Default for Cr2 {
-            fn default() -> Cr2 {
-                Cr2(0)
+        impl Default for Ur11 {
+            fn default() -> Ur11 {
+                Ur11(0)
             }
         }
-        #[doc = "Control register 1"]
+        #[doc = "compensation cell control/status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr1(pub u32);
-        impl Cr1 {
-            #[doc = "Send break"]
-            pub const fn sbk(&self) -> super::vals::Sbk {
+        pub struct Cccsr(pub u32);
+        impl Cccsr {
+            #[doc = "enable"]
+            pub const fn en(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
-                super::vals::Sbk(val as u8)
+                val != 0
             }
-            #[doc = "Send break"]
-            pub fn set_sbk(&mut self, val: super::vals::Sbk) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
+            #[doc = "enable"]
+            pub fn set_en(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Receiver wakeup"]
-            pub const fn rwu(&self) -> super::vals::Rwu {
+            #[doc = "Code selection"]
+            pub const fn cs(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
-                super::vals::Rwu(val as u8)
+                val != 0
             }
-            #[doc = "Receiver wakeup"]
-            pub fn set_rwu(&mut self, val: super::vals::Rwu) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
+            #[doc = "Code selection"]
+            pub fn set_cs(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Receiver enable"]
-            pub const fn re(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
+            #[doc = "Compensation cell ready flag"]
+            pub const fn ready(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "Receiver enable"]
-            pub fn set_re(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            #[doc = "Compensation cell ready flag"]
+            pub fn set_ready(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Transmitter enable"]
-            pub const fn te(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
+            #[doc = "High-speed at low-voltage"]
+            pub const fn hslv(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transmitter enable"]
-            pub fn set_te(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "High-speed at low-voltage"]
+            pub fn set_hslv(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
-            #[doc = "IDLE interrupt enable"]
-            pub const fn idleie(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
+        }
+        impl Default for Cccsr {
+            fn default() -> Cccsr {
+                Cccsr(0)
+            }
+        }
+        #[doc = "SYSCFG user register 8"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur8(pub u32);
+        impl Ur8 {
+            #[doc = "Mass erase protected area disabled for bank 2"]
+            pub const fn mepad_2(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "IDLE interrupt enable"]
-            pub fn set_idleie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            #[doc = "Mass erase protected area disabled for bank 2"]
+            pub fn set_mepad_2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "RXNE interrupt enable"]
-            pub const fn rxneie(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
+            #[doc = "Mass erase secured area disabled for bank 2"]
+            pub const fn mesad_2(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "RXNE interrupt enable"]
-            pub fn set_rxneie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            #[doc = "Mass erase secured area disabled for bank 2"]
+            pub fn set_mesad_2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
-            #[doc = "Transmission complete interrupt enable"]
-            pub const fn tcie(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
+        }
+        impl Default for Ur8 {
+            fn default() -> Ur8 {
+                Ur8(0)
+            }
+        }
+        #[doc = "SYSCFG user register 5"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur5(pub u32);
+        impl Ur5 {
+            #[doc = "Mass erase secured area disabled for bank 1"]
+            pub const fn mesad_1(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transmission complete interrupt enable"]
-            pub fn set_tcie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            #[doc = "Mass erase secured area disabled for bank 1"]
+            pub fn set_mesad_1(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "TXE interrupt enable"]
-            pub const fn txeie(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
+            #[doc = "Write protection for flash bank 1"]
+            pub const fn wrpn_1(&self) -> u8 {
+                let val = (self.0 >> 16usize) & 0xff;
+                val as u8
             }
-            #[doc = "TXE interrupt enable"]
-            pub fn set_txeie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            #[doc = "Write protection for flash bank 1"]
+            pub fn set_wrpn_1(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
             }
-            #[doc = "PE interrupt enable"]
-            pub const fn peie(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+        }
+        impl Default for Ur5 {
+            fn default() -> Ur5 {
+                Ur5(0)
+            }
+        }
+        #[doc = "SYSCFG user register 14"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur14(pub u32);
+        impl Ur14 {
+            #[doc = "D1 Stop Reset"]
+            pub const fn d1stprst(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "PE interrupt enable"]
-            pub fn set_peie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "D1 Stop Reset"]
+            pub fn set_d1stprst(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Parity selection"]
-            pub const fn ps(&self) -> super::vals::Ps {
-                let val = (self.0 >> 9usize) & 0x01;
-                super::vals::Ps(val as u8)
+        }
+        impl Default for Ur14 {
+            fn default() -> Ur14 {
+                Ur14(0)
             }
-            #[doc = "Parity selection"]
-            pub fn set_ps(&mut self, val: super::vals::Ps) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
+        }
+        #[doc = "SYSCFG user register 10"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur10(pub u32);
+        impl Ur10 {
+            #[doc = "Protected area end address for bank 2"]
+            pub const fn pa_end_2(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x0fff;
+                val as u16
             }
-            #[doc = "Parity control enable"]
-            pub const fn pce(&self) -> bool {
-                let val = (self.0 >> 10usize) & 0x01;
-                val != 0
+            #[doc = "Protected area end address for bank 2"]
+            pub fn set_pa_end_2(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
             }
-            #[doc = "Parity control enable"]
-            pub fn set_pce(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+            #[doc = "Secured area start address for bank 2"]
+            pub const fn sa_beg_2(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0x0fff;
+                val as u16
             }
-            #[doc = "Wakeup method"]
-            pub const fn wake(&self) -> super::vals::Wake {
-                let val = (self.0 >> 11usize) & 0x01;
-                super::vals::Wake(val as u8)
+            #[doc = "Secured area start address for bank 2"]
+            pub fn set_sa_beg_2(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
             }
-            #[doc = "Wakeup method"]
-            pub fn set_wake(&mut self, val: super::vals::Wake) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
+        }
+        impl Default for Ur10 {
+            fn default() -> Ur10 {
+                Ur10(0)
             }
-            #[doc = "Word length"]
-            pub const fn m(&self) -> super::vals::M {
-                let val = (self.0 >> 12usize) & 0x01;
-                super::vals::M(val as u8)
+        }
+        #[doc = "SYSCFG user register 16"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur16(pub u32);
+        impl Ur16 {
+            #[doc = "Freeze independent watchdog in Stop mode"]
+            pub const fn fziwdgstp(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Word length"]
-            pub fn set_m(&mut self, val: super::vals::M) {
-                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
+            #[doc = "Freeze independent watchdog in Stop mode"]
+            pub fn set_fziwdgstp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "USART enable"]
-            pub const fn ue(&self) -> bool {
-                let val = (self.0 >> 13usize) & 0x01;
+            #[doc = "Private key programmed"]
+            pub const fn pkp(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "USART enable"]
-            pub fn set_ue(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            #[doc = "Private key programmed"]
+            pub fn set_pkp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
         }
-        impl Default for Cr1 {
-            fn default() -> Cr1 {
-                Cr1(0)
+        impl Default for Ur16 {
+            fn default() -> Ur16 {
+                Ur16(0)
             }
         }
-        #[doc = "Guard time and prescaler register"]
+        #[doc = "SYSCFG user register 0"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Gtpr(pub u32);
-        impl Gtpr {
-            #[doc = "Prescaler value"]
-            pub const fn psc(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
+        pub struct Ur0(pub u32);
+        impl Ur0 {
+            #[doc = "Bank Swap"]
+            pub const fn bks(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Prescaler value"]
-            pub fn set_psc(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            #[doc = "Bank Swap"]
+            pub fn set_bks(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Guard time value"]
-            pub const fn gt(&self) -> u8 {
-                let val = (self.0 >> 8usize) & 0xff;
+            #[doc = "Readout protection"]
+            pub const fn rdp(&self) -> u8 {
+                let val = (self.0 >> 16usize) & 0xff;
                 val as u8
             }
-            #[doc = "Guard time value"]
-            pub fn set_gt(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+            #[doc = "Readout protection"]
+            pub fn set_rdp(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
             }
         }
-        impl Default for Gtpr {
-            fn default() -> Gtpr {
-                Gtpr(0)
+        impl Default for Ur0 {
+            fn default() -> Ur0 {
+                Ur0(0)
             }
         }
-        #[doc = "Baud rate register"]
+        #[doc = "SYSCFG user register 7"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Brr(pub u32);
-        impl Brr {
-            #[doc = "fraction of USARTDIV"]
-            pub const fn div_fraction(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x0f;
-                val as u8
+        pub struct Ur7(pub u32);
+        impl Ur7 {
+            #[doc = "Secured area start address for bank 1"]
+            pub const fn sa_beg_1(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x0fff;
+                val as u16
             }
-            #[doc = "fraction of USARTDIV"]
-            pub fn set_div_fraction(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+            #[doc = "Secured area start address for bank 1"]
+            pub fn set_sa_beg_1(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
             }
-            #[doc = "mantissa of USARTDIV"]
-            pub const fn div_mantissa(&self) -> u16 {
-                let val = (self.0 >> 4usize) & 0x0fff;
+            #[doc = "Secured area end address for bank 1"]
+            pub const fn sa_end_1(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0x0fff;
                 val as u16
             }
-            #[doc = "mantissa of USARTDIV"]
-            pub fn set_div_mantissa(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize);
+            #[doc = "Secured area end address for bank 1"]
+            pub fn set_sa_end_1(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
             }
         }
-        impl Default for Brr {
-            fn default() -> Brr {
-                Brr(0)
+        impl Default for Ur7 {
+            fn default() -> Ur7 {
+                Ur7(0)
             }
         }
-        #[doc = "Control register 2"]
+        #[doc = "SYSCFG compensation cell code register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2Usart(pub u32);
-        impl Cr2Usart {
-            #[doc = "Address of the USART node"]
-            pub const fn add(&self) -> u8 {
+        pub struct Cccr(pub u32);
+        impl Cccr {
+            #[doc = "NMOS compensation code"]
+            pub const fn ncc(&self) -> u8 {
                 let val = (self.0 >> 0usize) & 0x0f;
                 val as u8
             }
-            #[doc = "Address of the USART node"]
-            pub fn set_add(&mut self, val: u8) {
+            #[doc = "NMOS compensation code"]
+            pub fn set_ncc(&mut self, val: u8) {
                 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
             }
-            #[doc = "lin break detection length"]
-            pub const fn lbdl(&self) -> super::vals::Lbdl {
-                let val = (self.0 >> 5usize) & 0x01;
-                super::vals::Lbdl(val as u8)
+            #[doc = "PMOS compensation code"]
+            pub const fn pcc(&self) -> u8 {
+                let val = (self.0 >> 4usize) & 0x0f;
+                val as u8
             }
-            #[doc = "lin break detection length"]
-            pub fn set_lbdl(&mut self, val: super::vals::Lbdl) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
+            #[doc = "PMOS compensation code"]
+            pub fn set_pcc(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
             }
-            #[doc = "LIN break detection interrupt enable"]
-            pub const fn lbdie(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
+        }
+        impl Default for Cccr {
+            fn default() -> Cccr {
+                Cccr(0)
+            }
+        }
+        #[doc = "SYSCFG user register 4"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur4(pub u32);
+        impl Ur4 {
+            #[doc = "Mass Erase Protected Area Disabled for bank 1"]
+            pub const fn mepad_1(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "LIN break detection interrupt enable"]
-            pub fn set_lbdie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            #[doc = "Mass Erase Protected Area Disabled for bank 1"]
+            pub fn set_mepad_1(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
-            #[doc = "Last bit clock pulse"]
-            pub const fn lbcl(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+        }
+        impl Default for Ur4 {
+            fn default() -> Ur4 {
+                Ur4(0)
+            }
+        }
+        #[doc = "SYSCFG package register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Pkgr(pub u32);
+        impl Pkgr {
+            #[doc = "Package"]
+            pub const fn pkg(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "Package"]
+            pub fn set_pkg(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+            }
+        }
+        impl Default for Pkgr {
+            fn default() -> Pkgr {
+                Pkgr(0)
+            }
+        }
+        #[doc = "SYSCFG user register 15"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur15(pub u32);
+        impl Ur15 {
+            #[doc = "Freeze independent watchdog in Standby mode"]
+            pub const fn fziwdgstb(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
                 val != 0
             }
-            #[doc = "Last bit clock pulse"]
-            pub fn set_lbcl(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Freeze independent watchdog in Standby mode"]
+            pub fn set_fziwdgstb(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
-            #[doc = "Clock phase"]
-            pub const fn cpha(&self) -> super::vals::Cpha {
-                let val = (self.0 >> 9usize) & 0x01;
-                super::vals::Cpha(val as u8)
+        }
+        impl Default for Ur15 {
+            fn default() -> Ur15 {
+                Ur15(0)
             }
-            #[doc = "Clock phase"]
-            pub fn set_cpha(&mut self, val: super::vals::Cpha) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
+        }
+        #[doc = "SYSCFG user register 3"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur3(pub u32);
+        impl Ur3 {
+            #[doc = "Boot Address 1"]
+            pub const fn boot_add1(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0xffff;
+                val as u16
             }
-            #[doc = "Clock polarity"]
-            pub const fn cpol(&self) -> super::vals::Cpol {
-                let val = (self.0 >> 10usize) & 0x01;
-                super::vals::Cpol(val as u8)
+            #[doc = "Boot Address 1"]
+            pub fn set_boot_add1(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
             }
-            #[doc = "Clock polarity"]
-            pub fn set_cpol(&mut self, val: super::vals::Cpol) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
+        }
+        impl Default for Ur3 {
+            fn default() -> Ur3 {
+                Ur3(0)
             }
-            #[doc = "Clock enable"]
-            pub const fn clken(&self) -> bool {
-                let val = (self.0 >> 11usize) & 0x01;
-                val != 0
+        }
+        #[doc = "SYSCFG user register 9"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ur9(pub u32);
+        impl Ur9 {
+            #[doc = "Write protection for flash bank 2"]
+            pub const fn wrpn_2(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
             }
-            #[doc = "Clock enable"]
-            pub fn set_clken(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+            #[doc = "Write protection for flash bank 2"]
+            pub fn set_wrpn_2(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
             }
-            #[doc = "STOP bits"]
-            pub const fn stop(&self) -> super::vals::Stop {
-                let val = (self.0 >> 12usize) & 0x03;
-                super::vals::Stop(val as u8)
+            #[doc = "Protected area start address for bank 2"]
+            pub const fn pa_beg_2(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0x0fff;
+                val as u16
             }
-            #[doc = "STOP bits"]
-            pub fn set_stop(&mut self, val: super::vals::Stop) {
-                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+            #[doc = "Protected area start address for bank 2"]
+            pub fn set_pa_beg_2(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
             }
-            #[doc = "LIN mode enable"]
-            pub const fn linen(&self) -> bool {
-                let val = (self.0 >> 14usize) & 0x01;
-                val != 0
+        }
+        impl Default for Ur9 {
+            fn default() -> Ur9 {
+                Ur9(0)
             }
-            #[doc = "LIN mode enable"]
-            pub fn set_linen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+        }
+        #[doc = "external interrupt configuration register 2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Exticr(pub u32);
+        impl Exticr {
+            #[doc = "EXTI x configuration (x = 4 to 7)"]
+            pub fn exti(&self, n: usize) -> u8 {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x0f;
+                val as u8
+            }
+            #[doc = "EXTI x configuration (x = 4 to 7)"]
+            pub fn set_exti(&mut self, n: usize, val: u8) {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
             }
         }
-        impl Default for Cr2Usart {
-            fn default() -> Cr2Usart {
-                Cr2Usart(0)
+        impl Default for Exticr {
+            fn default() -> Exticr {
+                Exticr(0)
             }
         }
-        #[doc = "Data register"]
+        #[doc = "SYSCFG compensation cell value register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dr(pub u32);
-        impl Dr {
-            #[doc = "Data value"]
-            pub const fn dr(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x01ff;
-                val as u16
+        pub struct Ccvr(pub u32);
+        impl Ccvr {
+            #[doc = "NMOS compensation value"]
+            pub const fn ncv(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x0f;
+                val as u8
             }
-            #[doc = "Data value"]
-            pub fn set_dr(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+            #[doc = "NMOS compensation value"]
+            pub fn set_ncv(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+            }
+            #[doc = "PMOS compensation value"]
+            pub const fn pcv(&self) -> u8 {
+                let val = (self.0 >> 4usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "PMOS compensation value"]
+            pub fn set_pcv(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
             }
         }
-        impl Default for Dr {
-            fn default() -> Dr {
-                Dr(0)
+        impl Default for Ccvr {
+            fn default() -> Ccvr {
+                Ccvr(0)
             }
         }
-        #[doc = "Control register 3"]
+    }
+}
+pub mod gpio_v1 {
+    use crate::generic::*;
+    #[doc = "General purpose I/O"]
+    #[derive(Copy, Clone)]
+    pub struct Gpio(pub *mut u8);
+    unsafe impl Send for Gpio {}
+    unsafe impl Sync for Gpio {}
+    impl Gpio {
+        #[doc = "Port configuration register low (GPIOn_CRL)"]
+        pub fn cr(self, n: usize) -> Reg<regs::Cr, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
+        }
+        #[doc = "Port input data register (GPIOn_IDR)"]
+        pub fn idr(self) -> Reg<regs::Idr, R> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "Port output data register (GPIOn_ODR)"]
+        pub fn odr(self) -> Reg<regs::Odr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
+        pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "Port bit reset register (GPIOn_BRR)"]
+        pub fn brr(self) -> Reg<regs::Brr, W> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "Port configuration lock register"]
+        pub fn lckr(self) -> Reg<regs::Lckr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        }
+    }
+    pub mod vals {
+        use crate::generic::*;
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Odr(pub u8);
+        impl Odr {
+            #[doc = "Set output to logic low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Set output to logic high"]
+            pub const HIGH: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Cnf(pub u8);
+        impl Cnf {
+            #[doc = "Analog mode / Push-Pull mode"]
+            pub const PUSHPULL: Self = Self(0);
+            #[doc = "Floating input (reset state) / Open Drain-Mode"]
+            pub const OPENDRAIN: Self = Self(0x01);
+            #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"]
+            pub const ALTPUSHPULL: Self = Self(0x02);
+            #[doc = "Alternate Function Open-Drain Mode"]
+            pub const ALTOPENDRAIN: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Mode(pub u8);
+        impl Mode {
+            #[doc = "Input mode (reset state)"]
+            pub const INPUT: Self = Self(0);
+            #[doc = "Output mode 10 MHz"]
+            pub const OUTPUT: Self = Self(0x01);
+            #[doc = "Output mode 2 MHz"]
+            pub const OUTPUT2: Self = Self(0x02);
+            #[doc = "Output mode 50 MHz"]
+            pub const OUTPUT50: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Brw(pub u8);
+        impl Brw {
+            #[doc = "No action on the corresponding ODx bit"]
+            pub const NOACTION: Self = Self(0);
+            #[doc = "Reset the ODx bit"]
+            pub const RESET: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Lckk(pub u8);
+        impl Lckk {
+            #[doc = "Port configuration lock key not active"]
+            pub const NOTACTIVE: Self = Self(0);
+            #[doc = "Port configuration lock key active"]
+            pub const ACTIVE: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Lck(pub u8);
+        impl Lck {
+            #[doc = "Port configuration not locked"]
+            pub const UNLOCKED: Self = Self(0);
+            #[doc = "Port configuration locked"]
+            pub const LOCKED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Idr(pub u8);
+        impl Idr {
+            #[doc = "Input is logic low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Input is logic high"]
+            pub const HIGH: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Bsw(pub u8);
+        impl Bsw {
+            #[doc = "No action on the corresponding ODx bit"]
+            pub const NOACTION: Self = Self(0);
+            #[doc = "Sets the corresponding ODRx bit"]
+            pub const SET: Self = Self(0x01);
+        }
+    }
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr3(pub u32);
-        impl Cr3 {
-            #[doc = "Error interrupt enable"]
-            pub const fn eie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
+        pub struct Bsrr(pub u32);
+        impl Bsrr {
+            #[doc = "Set bit"]
+            pub fn bs(&self, n: usize) -> bool {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Error interrupt enable"]
-            pub fn set_eie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Set bit"]
+            pub fn set_bs(&mut self, n: usize, val: bool) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "IrDA mode enable"]
-            pub const fn iren(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
+            #[doc = "Reset bit"]
+            pub fn br(&self, n: usize) -> bool {
+                assert!(n < 16usize);
+                let offs = 16usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "IrDA mode enable"]
-            pub fn set_iren(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "Reset bit"]
+            pub fn set_br(&mut self, n: usize, val: bool) {
+                assert!(n < 16usize);
+                let offs = 16usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "IrDA low-power"]
-            pub const fn irlp(&self) -> super::vals::Irlp {
-                let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Irlp(val as u8)
+        }
+        impl Default for Bsrr {
+            fn default() -> Bsrr {
+                Bsrr(0)
             }
-            #[doc = "IrDA low-power"]
-            pub fn set_irlp(&mut self, val: super::vals::Irlp) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
+        }
+        #[doc = "Port output data register (GPIOn_ODR)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Odr(pub u32);
+        impl Odr {
+            #[doc = "Port output data"]
+            pub fn odr(&self, n: usize) -> super::vals::Odr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Odr(val as u8)
             }
-            #[doc = "Half-duplex selection"]
-            pub const fn hdsel(&self) -> super::vals::Hdsel {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Hdsel(val as u8)
+            #[doc = "Port output data"]
+            pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
-            #[doc = "Half-duplex selection"]
-            pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+        }
+        impl Default for Odr {
+            fn default() -> Odr {
+                Odr(0)
             }
-            #[doc = "DMA enable receiver"]
-            pub const fn dmar(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
+        }
+        #[doc = "Port configuration lock register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Lckr(pub u32);
+        impl Lckr {
+            #[doc = "Port A Lock bit"]
+            pub fn lck(&self, n: usize) -> super::vals::Lck {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Lck(val as u8)
             }
-            #[doc = "DMA enable receiver"]
-            pub fn set_dmar(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            #[doc = "Port A Lock bit"]
+            pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
-            #[doc = "DMA enable transmitter"]
-            pub const fn dmat(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
+            #[doc = "Lock key"]
+            pub const fn lckk(&self) -> super::vals::Lckk {
+                let val = (self.0 >> 16usize) & 0x01;
+                super::vals::Lckk(val as u8)
+            }
+            #[doc = "Lock key"]
+            pub fn set_lckk(&mut self, val: super::vals::Lckk) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
+            }
+        }
+        impl Default for Lckr {
+            fn default() -> Lckr {
+                Lckr(0)
+            }
+        }
+        #[doc = "Port input data register (GPIOn_IDR)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Idr(pub u32);
+        impl Idr {
+            #[doc = "Port input data"]
+            pub fn idr(&self, n: usize) -> super::vals::Idr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Idr(val as u8)
+            }
+            #[doc = "Port input data"]
+            pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for Idr {
+            fn default() -> Idr {
+                Idr(0)
+            }
+        }
+        #[doc = "Port configuration register (GPIOn_CRx)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr(pub u32);
+        impl Cr {
+            #[doc = "Port n mode bits"]
+            pub fn mode(&self, n: usize) -> super::vals::Mode {
+                assert!(n < 8usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Mode(val as u8)
+            }
+            #[doc = "Port n mode bits"]
+            pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
+                assert!(n < 8usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            }
+            #[doc = "Port n configuration bits"]
+            pub fn cnf(&self, n: usize) -> super::vals::Cnf {
+                assert!(n < 8usize);
+                let offs = 2usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Cnf(val as u8)
+            }
+            #[doc = "Port n configuration bits"]
+            pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) {
+                assert!(n < 8usize);
+                let offs = 2usize + n * 4usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            }
+        }
+        impl Default for Cr {
+            fn default() -> Cr {
+                Cr(0)
+            }
+        }
+        #[doc = "Port bit reset register (GPIOn_BRR)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Brr(pub u32);
+        impl Brr {
+            #[doc = "Reset bit"]
+            pub fn br(&self, n: usize) -> bool {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "DMA enable transmitter"]
-            pub fn set_dmat(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            #[doc = "Reset bit"]
+            pub fn set_br(&mut self, n: usize, val: bool) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Cr3 {
-            fn default() -> Cr3 {
-                Cr3(0)
+        impl Default for Brr {
+            fn default() -> Brr {
+                Brr(0)
             }
         }
-        #[doc = "Status register"]
+    }
+}
+pub mod dma_v2 {
+    use crate::generic::*;
+    #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
+    #[derive(Copy, Clone)]
+    pub struct St(pub *mut u8);
+    unsafe impl Send for St {}
+    unsafe impl Sync for St {}
+    impl St {
+        #[doc = "stream x configuration register"]
+        pub fn cr(self) -> Reg<regs::Cr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "stream x number of data register"]
+        pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "stream x peripheral address register"]
+        pub fn par(self) -> Reg<u32, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "stream x memory 0 address register"]
+        pub fn m0ar(self) -> Reg<u32, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "stream x memory 1 address register"]
+        pub fn m1ar(self) -> Reg<u32, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "stream x FIFO control register"]
+        pub fn fcr(self) -> Reg<regs::Fcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+    }
+    #[doc = "DMA controller"]
+    #[derive(Copy, Clone)]
+    pub struct Dma(pub *mut u8);
+    unsafe impl Send for Dma {}
+    unsafe impl Sync for Dma {}
+    impl Dma {
+        #[doc = "low interrupt status register"]
+        pub fn isr(self, n: usize) -> Reg<regs::Ixr, R> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
+        }
+        #[doc = "low interrupt flag clear register"]
+        pub fn ifcr(self, n: usize) -> Reg<regs::Ixr, W> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
+        }
+        #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
+        pub fn st(self, n: usize) -> St {
+            assert!(n < 8usize);
+            unsafe { St(self.0.add(16usize + n * 24usize)) }
+        }
+    }
+    pub mod vals {
+        use crate::generic::*;
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pincos(pub u8);
+        impl Pincos {
+            #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"]
+            pub const PSIZE: Self = Self(0);
+            #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"]
+            pub const FIXED4: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Inc(pub u8);
+        impl Inc {
+            #[doc = "Address pointer is fixed"]
+            pub const FIXED: Self = Self(0);
+            #[doc = "Address pointer is incremented after each data transfer"]
+            pub const INCREMENTED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ct(pub u8);
+        impl Ct {
+            #[doc = "The current target memory is Memory 0"]
+            pub const MEMORY0: Self = Self(0);
+            #[doc = "The current target memory is Memory 1"]
+            pub const MEMORY1: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Fs(pub u8);
+        impl Fs {
+            #[doc = "0 < fifo_level < 1/4"]
+            pub const QUARTER1: Self = Self(0);
+            #[doc = "1/4 <= fifo_level < 1/2"]
+            pub const QUARTER2: Self = Self(0x01);
+            #[doc = "1/2 <= fifo_level < 3/4"]
+            pub const QUARTER3: Self = Self(0x02);
+            #[doc = "3/4 <= fifo_level < full"]
+            pub const QUARTER4: Self = Self(0x03);
+            #[doc = "FIFO is empty"]
+            pub const EMPTY: Self = Self(0x04);
+            #[doc = "FIFO is full"]
+            pub const FULL: Self = Self(0x05);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Fth(pub u8);
+        impl Fth {
+            #[doc = "1/4 full FIFO"]
+            pub const QUARTER: Self = Self(0);
+            #[doc = "1/2 full FIFO"]
+            pub const HALF: Self = Self(0x01);
+            #[doc = "3/4 full FIFO"]
+            pub const THREEQUARTERS: Self = Self(0x02);
+            #[doc = "Full FIFO"]
+            pub const FULL: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Circ(pub u8);
+        impl Circ {
+            #[doc = "Circular mode disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Circular mode enabled"]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Size(pub u8);
+        impl Size {
+            #[doc = "Byte (8-bit)"]
+            pub const BITS8: Self = Self(0);
+            #[doc = "Half-word (16-bit)"]
+            pub const BITS16: Self = Self(0x01);
+            #[doc = "Word (32-bit)"]
+            pub const BITS32: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dmdis(pub u8);
+        impl Dmdis {
+            #[doc = "Direct mode is enabled"]
+            pub const ENABLED: Self = Self(0);
+            #[doc = "Direct mode is disabled"]
+            pub const DISABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dbm(pub u8);
+        impl Dbm {
+            #[doc = "No buffer switching at the end of transfer"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Memory target switched at the end of the DMA transfer"]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pl(pub u8);
+        impl Pl {
+            #[doc = "Low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Medium"]
+            pub const MEDIUM: Self = Self(0x01);
+            #[doc = "High"]
+            pub const HIGH: Self = Self(0x02);
+            #[doc = "Very high"]
+            pub const VERYHIGH: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Burst(pub u8);
+        impl Burst {
+            #[doc = "Single transfer"]
+            pub const SINGLE: Self = Self(0);
+            #[doc = "Incremental burst of 4 beats"]
+            pub const INCR4: Self = Self(0x01);
+            #[doc = "Incremental burst of 8 beats"]
+            pub const INCR8: Self = Self(0x02);
+            #[doc = "Incremental burst of 16 beats"]
+            pub const INCR16: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dir(pub u8);
+        impl Dir {
+            #[doc = "Peripheral-to-memory"]
+            pub const PERIPHERALTOMEMORY: Self = Self(0);
+            #[doc = "Memory-to-peripheral"]
+            pub const MEMORYTOPERIPHERAL: Self = Self(0x01);
+            #[doc = "Memory-to-memory"]
+            pub const MEMORYTOMEMORY: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pfctrl(pub u8);
+        impl Pfctrl {
+            #[doc = "The DMA is the flow controller"]
+            pub const DMA: Self = Self(0);
+            #[doc = "The peripheral is the flow controller"]
+            pub const PERIPHERAL: Self = Self(0x01);
+        }
+    }
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "stream x number of data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrUsart(pub u32);
-        impl SrUsart {
-            #[doc = "Parity error"]
-            pub const fn pe(&self) -> bool {
+        pub struct Ndtr(pub u32);
+        impl Ndtr {
+            #[doc = "Number of data items to transfer"]
+            pub const fn ndt(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Number of data items to transfer"]
+            pub fn set_ndt(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Ndtr {
+            fn default() -> Ndtr {
+                Ndtr(0)
+            }
+        }
+        #[doc = "stream x configuration register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr(pub u32);
+        impl Cr {
+            #[doc = "Stream enable / flag stream ready when read low"]
+            pub const fn en(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Parity error"]
-            pub fn set_pe(&mut self, val: bool) {
+            #[doc = "Stream enable / flag stream ready when read low"]
+            pub fn set_en(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Framing error"]
-            pub const fn fe(&self) -> bool {
+            #[doc = "Direct mode error interrupt enable"]
+            pub const fn dmeie(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Framing error"]
-            pub fn set_fe(&mut self, val: bool) {
+            #[doc = "Direct mode error interrupt enable"]
+            pub fn set_dmeie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Noise error flag"]
-            pub const fn ne(&self) -> bool {
+            #[doc = "Transfer error interrupt enable"]
+            pub const fn teie(&self) -> bool {
                 let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Noise error flag"]
-            pub fn set_ne(&mut self, val: bool) {
+            #[doc = "Transfer error interrupt enable"]
+            pub fn set_teie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Overrun error"]
-            pub const fn ore(&self) -> bool {
+            #[doc = "Half transfer interrupt enable"]
+            pub const fn htie(&self) -> bool {
                 let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "Overrun error"]
-            pub fn set_ore(&mut self, val: bool) {
+            #[doc = "Half transfer interrupt enable"]
+            pub fn set_htie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-            #[doc = "IDLE line detected"]
-            pub const fn idle(&self) -> bool {
+            #[doc = "Transfer complete interrupt enable"]
+            pub const fn tcie(&self) -> bool {
                 let val = (self.0 >> 4usize) & 0x01;
                 val != 0
             }
-            #[doc = "IDLE line detected"]
-            pub fn set_idle(&mut self, val: bool) {
+            #[doc = "Transfer complete interrupt enable"]
+            pub fn set_tcie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "Read data register not empty"]
-            pub const fn rxne(&self) -> bool {
+            #[doc = "Peripheral flow controller"]
+            pub const fn pfctrl(&self) -> super::vals::Pfctrl {
                 let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Read data register not empty"]
-            pub fn set_rxne(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Transmission complete"]
-            pub const fn tc(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
+                super::vals::Pfctrl(val as u8)
             }
-            #[doc = "Transmission complete"]
-            pub fn set_tc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            #[doc = "Peripheral flow controller"]
+            pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
             }
-            #[doc = "Transmit data register empty"]
-            pub const fn txe(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
+            #[doc = "Data transfer direction"]
+            pub const fn dir(&self) -> super::vals::Dir {
+                let val = (self.0 >> 6usize) & 0x03;
+                super::vals::Dir(val as u8)
             }
-            #[doc = "Transmit data register empty"]
-            pub fn set_txe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            #[doc = "Data transfer direction"]
+            pub fn set_dir(&mut self, val: super::vals::Dir) {
+                self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize);
             }
-            #[doc = "LIN break detection flag"]
-            pub const fn lbd(&self) -> bool {
+            #[doc = "Circular mode"]
+            pub const fn circ(&self) -> super::vals::Circ {
                 let val = (self.0 >> 8usize) & 0x01;
-                val != 0
+                super::vals::Circ(val as u8)
             }
-            #[doc = "LIN break detection flag"]
-            pub fn set_lbd(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Circular mode"]
+            pub fn set_circ(&mut self, val: super::vals::Circ) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
             }
-            #[doc = "CTS flag"]
-            pub const fn cts(&self) -> bool {
+            #[doc = "Peripheral increment mode"]
+            pub const fn pinc(&self) -> super::vals::Inc {
                 let val = (self.0 >> 9usize) & 0x01;
-                val != 0
+                super::vals::Inc(val as u8)
             }
-            #[doc = "CTS flag"]
-            pub fn set_cts(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            #[doc = "Peripheral increment mode"]
+            pub fn set_pinc(&mut self, val: super::vals::Inc) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
+            }
+            #[doc = "Memory increment mode"]
+            pub const fn minc(&self) -> super::vals::Inc {
+                let val = (self.0 >> 10usize) & 0x01;
+                super::vals::Inc(val as u8)
+            }
+            #[doc = "Memory increment mode"]
+            pub fn set_minc(&mut self, val: super::vals::Inc) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
+            }
+            #[doc = "Peripheral data size"]
+            pub const fn psize(&self) -> super::vals::Size {
+                let val = (self.0 >> 11usize) & 0x03;
+                super::vals::Size(val as u8)
+            }
+            #[doc = "Peripheral data size"]
+            pub fn set_psize(&mut self, val: super::vals::Size) {
+                self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
+            }
+            #[doc = "Memory data size"]
+            pub const fn msize(&self) -> super::vals::Size {
+                let val = (self.0 >> 13usize) & 0x03;
+                super::vals::Size(val as u8)
+            }
+            #[doc = "Memory data size"]
+            pub fn set_msize(&mut self, val: super::vals::Size) {
+                self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
+            }
+            #[doc = "Peripheral increment offset size"]
+            pub const fn pincos(&self) -> super::vals::Pincos {
+                let val = (self.0 >> 15usize) & 0x01;
+                super::vals::Pincos(val as u8)
+            }
+            #[doc = "Peripheral increment offset size"]
+            pub fn set_pincos(&mut self, val: super::vals::Pincos) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            }
+            #[doc = "Priority level"]
+            pub const fn pl(&self) -> super::vals::Pl {
+                let val = (self.0 >> 16usize) & 0x03;
+                super::vals::Pl(val as u8)
+            }
+            #[doc = "Priority level"]
+            pub fn set_pl(&mut self, val: super::vals::Pl) {
+                self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
+            }
+            #[doc = "Double buffer mode"]
+            pub const fn dbm(&self) -> super::vals::Dbm {
+                let val = (self.0 >> 18usize) & 0x01;
+                super::vals::Dbm(val as u8)
+            }
+            #[doc = "Double buffer mode"]
+            pub fn set_dbm(&mut self, val: super::vals::Dbm) {
+                self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
+            }
+            #[doc = "Current target (only in double buffer mode)"]
+            pub const fn ct(&self) -> super::vals::Ct {
+                let val = (self.0 >> 19usize) & 0x01;
+                super::vals::Ct(val as u8)
+            }
+            #[doc = "Current target (only in double buffer mode)"]
+            pub fn set_ct(&mut self, val: super::vals::Ct) {
+                self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
+            }
+            #[doc = "Peripheral burst transfer configuration"]
+            pub const fn pburst(&self) -> super::vals::Burst {
+                let val = (self.0 >> 21usize) & 0x03;
+                super::vals::Burst(val as u8)
+            }
+            #[doc = "Peripheral burst transfer configuration"]
+            pub fn set_pburst(&mut self, val: super::vals::Burst) {
+                self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
+            }
+            #[doc = "Memory burst transfer configuration"]
+            pub const fn mburst(&self) -> super::vals::Burst {
+                let val = (self.0 >> 23usize) & 0x03;
+                super::vals::Burst(val as u8)
+            }
+            #[doc = "Memory burst transfer configuration"]
+            pub fn set_mburst(&mut self, val: super::vals::Burst) {
+                self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize);
+            }
+            #[doc = "Channel selection"]
+            pub const fn chsel(&self) -> u8 {
+                let val = (self.0 >> 25usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "Channel selection"]
+            pub fn set_chsel(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
             }
         }
-        impl Default for SrUsart {
-            fn default() -> SrUsart {
-                SrUsart(0)
+        impl Default for Cr {
+            fn default() -> Cr {
+                Cr(0)
             }
         }
-        #[doc = "Control register 3"]
+        #[doc = "stream x FIFO control register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr3Usart(pub u32);
-        impl Cr3Usart {
-            #[doc = "Error interrupt enable"]
-            pub const fn eie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Error interrupt enable"]
-            pub fn set_eie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "IrDA mode enable"]
-            pub const fn iren(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
+        pub struct Fcr(pub u32);
+        impl Fcr {
+            #[doc = "FIFO threshold selection"]
+            pub const fn fth(&self) -> super::vals::Fth {
+                let val = (self.0 >> 0usize) & 0x03;
+                super::vals::Fth(val as u8)
             }
-            #[doc = "IrDA mode enable"]
-            pub fn set_iren(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "FIFO threshold selection"]
+            pub fn set_fth(&mut self, val: super::vals::Fth) {
+                self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
             }
-            #[doc = "IrDA low-power"]
-            pub const fn irlp(&self) -> super::vals::Irlp {
+            #[doc = "Direct mode disable"]
+            pub const fn dmdis(&self) -> super::vals::Dmdis {
                 let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Irlp(val as u8)
+                super::vals::Dmdis(val as u8)
             }
-            #[doc = "IrDA low-power"]
-            pub fn set_irlp(&mut self, val: super::vals::Irlp) {
+            #[doc = "Direct mode disable"]
+            pub fn set_dmdis(&mut self, val: super::vals::Dmdis) {
                 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
             }
-            #[doc = "Half-duplex selection"]
-            pub const fn hdsel(&self) -> super::vals::Hdsel {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Hdsel(val as u8)
+            #[doc = "FIFO status"]
+            pub const fn fs(&self) -> super::vals::Fs {
+                let val = (self.0 >> 3usize) & 0x07;
+                super::vals::Fs(val as u8)
             }
-            #[doc = "Half-duplex selection"]
-            pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+            #[doc = "FIFO status"]
+            pub fn set_fs(&mut self, val: super::vals::Fs) {
+                self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
             }
-            #[doc = "Smartcard NACK enable"]
-            pub const fn nack(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
+            #[doc = "FIFO error interrupt enable"]
+            pub const fn feie(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Smartcard NACK enable"]
-            pub fn set_nack(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
-            }
-            #[doc = "Smartcard mode enable"]
-            pub const fn scen(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
+            #[doc = "FIFO error interrupt enable"]
+            pub fn set_feie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Smartcard mode enable"]
-            pub fn set_scen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+        }
+        impl Default for Fcr {
+            fn default() -> Fcr {
+                Fcr(0)
             }
-            #[doc = "DMA enable receiver"]
-            pub const fn dmar(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
+        }
+        #[doc = "interrupt register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ixr(pub u32);
+        impl Ixr {
+            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
+            pub fn feif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "DMA enable receiver"]
-            pub fn set_dmar(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
+            pub fn set_feif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "DMA enable transmitter"]
-            pub const fn dmat(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
+            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
+            pub fn dmeif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "DMA enable transmitter"]
-            pub fn set_dmat(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
+            pub fn set_dmeif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "RTS enable"]
-            pub const fn rtse(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
+            pub fn teif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "RTS enable"]
-            pub fn set_rtse(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
+            pub fn set_teif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "CTS enable"]
-            pub const fn ctse(&self) -> bool {
-                let val = (self.0 >> 9usize) & 0x01;
+            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
+            pub fn htif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "CTS enable"]
-            pub fn set_ctse(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
+            pub fn set_htif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "CTS interrupt enable"]
-            pub const fn ctsie(&self) -> bool {
-                let val = (self.0 >> 10usize) & 0x01;
+            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
+            pub fn tcif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "CTS interrupt enable"]
-            pub fn set_ctsie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
+            pub fn set_tcif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Cr3Usart {
-            fn default() -> Cr3Usart {
-                Cr3Usart(0)
+        impl Default for Ixr {
+            fn default() -> Ixr {
+                Ixr(0)
             }
         }
     }
@@ -6892,30 +5208,21 @@ pub mod usart_v2 {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Datainv(pub u8);
-        impl Datainv {
-            #[doc = "Logical data from the data register are send/received in positive/direct logic"]
-            pub const POSITIVE: Self = Self(0);
-            #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
-            pub const NEGATIVE: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ovrdis(pub u8);
-        impl Ovrdis {
-            #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
-            pub const ENABLED: Self = Self(0);
-            #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
-            pub const DISABLED: Self = Self(0x01);
+        pub struct Ps(pub u8);
+        impl Ps {
+            #[doc = "Even parity"]
+            pub const EVEN: Self = Self(0);
+            #[doc = "Odd parity"]
+            pub const ODD: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ddre(pub u8);
-        impl Ddre {
-            #[doc = "DMA is not disabled in case of reception error"]
-            pub const NOTDISABLED: Self = Self(0);
-            #[doc = "DMA is disabled following a reception error"]
-            pub const DISABLED: Self = Self(0x01);
+        pub struct M1(pub u8);
+        impl M1 {
+            #[doc = "Use M0 to set the data bits"]
+            pub const M0: Self = Self(0);
+            #[doc = "1 start bit, 7 data bits, n stop bits"]
+            pub const BIT7: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -6928,12 +5235,25 @@ pub mod usart_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Onebit(pub u8);
-        impl Onebit {
-            #[doc = "Three sample bit method"]
-            pub const SAMPLE3: Self = Self(0);
-            #[doc = "One sample bit method"]
-            pub const SAMPLE1: Self = Self(0x01);
+        pub struct Dep(pub u8);
+        impl Dep {
+            #[doc = "DE signal is active high"]
+            pub const HIGH: Self = Self(0);
+            #[doc = "DE signal is active low"]
+            pub const LOW: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Abrmod(pub u8);
+        impl Abrmod {
+            #[doc = "Measurement of the start bit is used to detect the baud rate"]
+            pub const START: Self = Self(0);
+            #[doc = "Falling edge to falling edge measurement"]
+            pub const EDGE: Self = Self(0x01);
+            #[doc = "0x7F frame detection"]
+            pub const FRAME7F: Self = Self(0x02);
+            #[doc = "0x55 frame detection"]
+            pub const FRAME55: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -6946,12 +5266,12 @@ pub mod usart_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ps(pub u8);
-        impl Ps {
-            #[doc = "Even parity"]
-            pub const EVEN: Self = Self(0);
-            #[doc = "Odd parity"]
-            pub const ODD: Self = Self(0x01);
+        pub struct Msbfirst(pub u8);
+        impl Msbfirst {
+            #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
+            pub const LSB: Self = Self(0);
+            #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
+            pub const MSB: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -6962,57 +5282,30 @@ pub mod usart_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dep(pub u8);
-        impl Dep {
-            #[doc = "DE signal is active high"]
-            pub const HIGH: Self = Self(0);
-            #[doc = "DE signal is active low"]
-            pub const LOW: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Over(pub u8);
-        impl Over {
-            #[doc = "Oversampling by 16"]
-            pub const OVERSAMPLING16: Self = Self(0);
-            #[doc = "Oversampling by 8"]
-            pub const OVERSAMPLING8: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Rxfrq(pub u8);
-        impl Rxfrq {
-            #[doc = "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"]
-            pub const DISCARD: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Wus(pub u8);
-        impl Wus {
-            #[doc = "WUF active on address match"]
-            pub const ADDRESS: Self = Self(0);
-            #[doc = "WuF active on Start bit detection"]
-            pub const START: Self = Self(0x02);
-            #[doc = "WUF active on RXNE"]
-            pub const RXNE: Self = Self(0x03);
+        pub struct Ddre(pub u8);
+        impl Ddre {
+            #[doc = "DMA is not disabled in case of reception error"]
+            pub const NOTDISABLED: Self = Self(0);
+            #[doc = "DMA is disabled following a reception error"]
+            pub const DISABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cpol(pub u8);
-        impl Cpol {
-            #[doc = "Steady low value on CK pin outside transmission window"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Steady high value on CK pin outside transmission window"]
-            pub const HIGH: Self = Self(0x01);
+        pub struct Datainv(pub u8);
+        impl Datainv {
+            #[doc = "Logical data from the data register are send/received in positive/direct logic"]
+            pub const POSITIVE: Self = Self(0);
+            #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
+            pub const NEGATIVE: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cpha(pub u8);
-        impl Cpha {
-            #[doc = "The first clock transition is the first data capture edge"]
-            pub const FIRST: Self = Self(0);
-            #[doc = "The second clock transition is the first data capture edge"]
-            pub const SECOND: Self = Self(0x01);
+        pub struct Onebit(pub u8);
+        impl Onebit {
+            #[doc = "Three sample bit method"]
+            pub const SAMPLE3: Self = Self(0);
+            #[doc = "One sample bit method"]
+            pub const SAMPLE1: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -7025,12 +5318,25 @@ pub mod usart_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Irlp(pub u8);
-        impl Irlp {
-            #[doc = "Normal mode"]
-            pub const NORMAL: Self = Self(0);
-            #[doc = "Low-power mode"]
-            pub const LOWPOWER: Self = Self(0x01);
+        pub struct Lbdl(pub u8);
+        impl Lbdl {
+            #[doc = "10-bit break detection"]
+            pub const BIT10: Self = Self(0);
+            #[doc = "11-bit break detection"]
+            pub const BIT11: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Stop(pub u8);
+        impl Stop {
+            #[doc = "1 stop bit"]
+            pub const STOP1: Self = Self(0);
+            #[doc = "0.5 stop bit"]
+            pub const STOP0P5: Self = Self(0x01);
+            #[doc = "2 stop bit"]
+            pub const STOP2: Self = Self(0x02);
+            #[doc = "1.5 stop bit"]
+            pub const STOP1P5: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -7041,75 +5347,59 @@ pub mod usart_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lbcl(pub u8);
-        impl Lbcl {
-            #[doc = "The clock pulse of the last data bit is not output to the CK pin"]
-            pub const NOTOUTPUT: Self = Self(0);
-            #[doc = "The clock pulse of the last data bit is output to the CK pin"]
-            pub const OUTPUT: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mmrq(pub u8);
-        impl Mmrq {
-            #[doc = "Puts the USART in mute mode and sets the RWU flag"]
-            pub const MUTE: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Txfrq(pub u8);
-        impl Txfrq {
-            #[doc = "Set the TXE flags. This allows to discard the transmit data"]
-            pub const DISCARD: Self = Self(0x01);
+        pub struct Hdsel(pub u8);
+        impl Hdsel {
+            #[doc = "Half duplex mode is not selected"]
+            pub const NOTSELECTED: Self = Self(0);
+            #[doc = "Half duplex mode is selected"]
+            pub const SELECTED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Rxinv(pub u8);
-        impl Rxinv {
-            #[doc = "RX pin signal works using the standard logic levels"]
-            pub const STANDARD: Self = Self(0);
-            #[doc = "RX pin signal values are inverted"]
-            pub const INVERTED: Self = Self(0x01);
+        pub struct Cpha(pub u8);
+        impl Cpha {
+            #[doc = "The first clock transition is the first data capture edge"]
+            pub const FIRST: Self = Self(0);
+            #[doc = "The second clock transition is the first data capture edge"]
+            pub const SECOND: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct M1(pub u8);
-        impl M1 {
-            #[doc = "Use M0 to set the data bits"]
-            pub const M0: Self = Self(0);
-            #[doc = "1 start bit, 7 data bits, n stop bits"]
+        pub struct Addm(pub u8);
+        impl Addm {
+            #[doc = "4-bit address detection"]
+            pub const BIT4: Self = Self(0);
+            #[doc = "7-bit address detection"]
             pub const BIT7: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Stop(pub u8);
-        impl Stop {
-            #[doc = "1 stop bit"]
-            pub const STOP1: Self = Self(0);
-            #[doc = "0.5 stop bit"]
-            pub const STOP0P5: Self = Self(0x01);
-            #[doc = "2 stop bit"]
-            pub const STOP2: Self = Self(0x02);
-            #[doc = "1.5 stop bit"]
-            pub const STOP1P5: Self = Self(0x03);
+        pub struct Wus(pub u8);
+        impl Wus {
+            #[doc = "WUF active on address match"]
+            pub const ADDRESS: Self = Self(0);
+            #[doc = "WuF active on Start bit detection"]
+            pub const START: Self = Self(0x02);
+            #[doc = "WUF active on RXNE"]
+            pub const RXNE: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lbdl(pub u8);
-        impl Lbdl {
-            #[doc = "10-bit break detection"]
-            pub const BIT10: Self = Self(0);
-            #[doc = "11-bit break detection"]
-            pub const BIT11: Self = Self(0x01);
+        pub struct Over(pub u8);
+        impl Over {
+            #[doc = "Oversampling by 16"]
+            pub const OVERSAMPLING16: Self = Self(0);
+            #[doc = "Oversampling by 8"]
+            pub const OVERSAMPLING8: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Addm(pub u8);
-        impl Addm {
-            #[doc = "4-bit address detection"]
-            pub const BIT4: Self = Self(0);
-            #[doc = "7-bit address detection"]
-            pub const BIT7: Self = Self(0x01);
+        pub struct Cpol(pub u8);
+        impl Cpol {
+            #[doc = "Steady low value on CK pin outside transmission window"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Steady high value on CK pin outside transmission window"]
+            pub const HIGH: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -7122,97 +5412,64 @@ pub mod usart_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Hdsel(pub u8);
-        impl Hdsel {
-            #[doc = "Half duplex mode is not selected"]
-            pub const NOTSELECTED: Self = Self(0);
-            #[doc = "Half duplex mode is selected"]
-            pub const SELECTED: Self = Self(0x01);
+        pub struct Ovrdis(pub u8);
+        impl Ovrdis {
+            #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
+            pub const ENABLED: Self = Self(0);
+            #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
+            pub const DISABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Abrmod(pub u8);
-        impl Abrmod {
-            #[doc = "Measurement of the start bit is used to detect the baud rate"]
-            pub const START: Self = Self(0);
-            #[doc = "Falling edge to falling edge measurement"]
-            pub const EDGE: Self = Self(0x01);
-            #[doc = "0x7F frame detection"]
-            pub const FRAME7F: Self = Self(0x02);
-            #[doc = "0x55 frame detection"]
-            pub const FRAME55: Self = Self(0x03);
+        pub struct Rxinv(pub u8);
+        impl Rxinv {
+            #[doc = "RX pin signal works using the standard logic levels"]
+            pub const STANDARD: Self = Self(0);
+            #[doc = "RX pin signal values are inverted"]
+            pub const INVERTED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Msbfirst(pub u8);
-        impl Msbfirst {
-            #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
-            pub const LSB: Self = Self(0);
-            #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
-            pub const MSB: Self = Self(0x01);
+        pub struct Irlp(pub u8);
+        impl Irlp {
+            #[doc = "Normal mode"]
+            pub const NORMAL: Self = Self(0);
+            #[doc = "Low-power mode"]
+            pub const LOWPOWER: Self = Self(0x01);
         }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "Guard time and prescaler register"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Gtpr(pub u32);
-        impl Gtpr {
-            #[doc = "Prescaler value"]
-            pub const fn psc(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Prescaler value"]
-            pub fn set_psc(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
-            }
-            #[doc = "Guard time value"]
-            pub const fn gt(&self) -> u8 {
-                let val = (self.0 >> 8usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Guard time value"]
-            pub fn set_gt(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
-            }
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Lbcl(pub u8);
+        impl Lbcl {
+            #[doc = "The clock pulse of the last data bit is not output to the CK pin"]
+            pub const NOTOUTPUT: Self = Self(0);
+            #[doc = "The clock pulse of the last data bit is output to the CK pin"]
+            pub const OUTPUT: Self = Self(0x01);
         }
-        impl Default for Gtpr {
-            fn default() -> Gtpr {
-                Gtpr(0)
-            }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Txfrq(pub u8);
+        impl Txfrq {
+            #[doc = "Set the TXE flags. This allows to discard the transmit data"]
+            pub const DISCARD: Self = Self(0x01);
         }
-        #[doc = "Receiver timeout register"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Rtor(pub u32);
-        impl Rtor {
-            #[doc = "Receiver timeout value"]
-            pub const fn rto(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0x00ff_ffff;
-                val as u32
-            }
-            #[doc = "Receiver timeout value"]
-            pub fn set_rto(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
-            }
-            #[doc = "Block Length"]
-            pub const fn blen(&self) -> u8 {
-                let val = (self.0 >> 24usize) & 0xff;
-                val as u8
-            }
-            #[doc = "Block Length"]
-            pub fn set_blen(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize);
-            }
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Mmrq(pub u8);
+        impl Mmrq {
+            #[doc = "Puts the USART in mute mode and sets the RWU flag"]
+            pub const MUTE: Self = Self(0x01);
         }
-        impl Default for Rtor {
-            fn default() -> Rtor {
-                Rtor(0)
-            }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Rxfrq(pub u8);
+        impl Rxfrq {
+            #[doc = "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"]
+            pub const DISCARD: Self = Self(0x01);
         }
+    }
+    pub mod regs {
+        use crate::generic::*;
         #[doc = "Baud rate register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -7233,24 +5490,264 @@ pub mod usart_v2 {
                 Brr(0)
             }
         }
-        #[doc = "Data register"]
+        #[doc = "Control register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dr(pub u32);
-        impl Dr {
-            #[doc = "data value"]
-            pub const fn dr(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x01ff;
-                val as u16
+        pub struct Cr1(pub u32);
+        impl Cr1 {
+            #[doc = "USART enable"]
+            pub const fn ue(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "data value"]
-            pub fn set_dr(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+            #[doc = "USART enable"]
+            pub fn set_ue(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "USART enable in Stop mode"]
+            pub const fn uesm(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "USART enable in Stop mode"]
+            pub fn set_uesm(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Receiver enable"]
+            pub const fn re(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Receiver enable"]
+            pub fn set_re(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "Transmitter enable"]
+            pub const fn te(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transmitter enable"]
+            pub fn set_te(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "IDLE interrupt enable"]
+            pub const fn idleie(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
+                val != 0
+            }
+            #[doc = "IDLE interrupt enable"]
+            pub fn set_idleie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            }
+            #[doc = "RXNE interrupt enable"]
+            pub const fn rxneie(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "RXNE interrupt enable"]
+            pub fn set_rxneie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Transmission complete interrupt enable"]
+            pub const fn tcie(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transmission complete interrupt enable"]
+            pub fn set_tcie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "interrupt enable"]
+            pub const fn txeie(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "interrupt enable"]
+            pub fn set_txeie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "PE interrupt enable"]
+            pub const fn peie(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "PE interrupt enable"]
+            pub fn set_peie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Parity selection"]
+            pub const fn ps(&self) -> super::vals::Ps {
+                let val = (self.0 >> 9usize) & 0x01;
+                super::vals::Ps(val as u8)
+            }
+            #[doc = "Parity selection"]
+            pub fn set_ps(&mut self, val: super::vals::Ps) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
+            }
+            #[doc = "Parity control enable"]
+            pub const fn pce(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Parity control enable"]
+            pub fn set_pce(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+            }
+            #[doc = "Receiver wakeup method"]
+            pub const fn wake(&self) -> bool {
+                let val = (self.0 >> 11usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Receiver wakeup method"]
+            pub fn set_wake(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+            }
+            #[doc = "Word length"]
+            pub const fn m0(&self) -> super::vals::M0 {
+                let val = (self.0 >> 12usize) & 0x01;
+                super::vals::M0(val as u8)
+            }
+            #[doc = "Word length"]
+            pub fn set_m0(&mut self, val: super::vals::M0) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
+            }
+            #[doc = "Word length"]
+            pub const fn m1(&self) -> super::vals::M1 {
+                let val = (self.0 >> 12usize) & 0x01;
+                super::vals::M1(val as u8)
+            }
+            #[doc = "Word length"]
+            pub fn set_m1(&mut self, val: super::vals::M1) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
+            }
+            #[doc = "Mute mode enable"]
+            pub const fn mme(&self) -> bool {
+                let val = (self.0 >> 13usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Mute mode enable"]
+            pub fn set_mme(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            }
+            #[doc = "Character match interrupt enable"]
+            pub const fn cmie(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Character match interrupt enable"]
+            pub fn set_cmie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            }
+            #[doc = "Oversampling mode"]
+            pub fn over(&self, n: usize) -> super::vals::Over {
+                assert!(n < 1usize);
+                let offs = 15usize + n * 0usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Over(val as u8)
+            }
+            #[doc = "Oversampling mode"]
+            pub fn set_over(&mut self, n: usize, val: super::vals::Over) {
+                assert!(n < 1usize);
+                let offs = 15usize + n * 0usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
+            #[doc = "Driver Enable deassertion time"]
+            pub const fn dedt(&self) -> u8 {
+                let val = (self.0 >> 16usize) & 0x1f;
+                val as u8
+            }
+            #[doc = "Driver Enable deassertion time"]
+            pub fn set_dedt(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
+            }
+            #[doc = "Driver Enable assertion time"]
+            pub const fn deat(&self) -> u8 {
+                let val = (self.0 >> 21usize) & 0x1f;
+                val as u8
+            }
+            #[doc = "Driver Enable assertion time"]
+            pub fn set_deat(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 21usize)) | (((val as u32) & 0x1f) << 21usize);
+            }
+            #[doc = "Receiver timeout interrupt enable"]
+            pub const fn rtoie(&self) -> bool {
+                let val = (self.0 >> 26usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Receiver timeout interrupt enable"]
+            pub fn set_rtoie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+            }
+            #[doc = "End of Block interrupt enable"]
+            pub const fn eobie(&self) -> bool {
+                let val = (self.0 >> 27usize) & 0x01;
+                val != 0
+            }
+            #[doc = "End of Block interrupt enable"]
+            pub fn set_eobie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
             }
         }
-        impl Default for Dr {
-            fn default() -> Dr {
-                Dr(0)
+        impl Default for Cr1 {
+            fn default() -> Cr1 {
+                Cr1(0)
+            }
+        }
+        #[doc = "Request register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Rqr(pub u32);
+        impl Rqr {
+            #[doc = "Auto baud rate request"]
+            pub const fn abrrq(&self) -> super::vals::Abrrq {
+                let val = (self.0 >> 0usize) & 0x01;
+                super::vals::Abrrq(val as u8)
+            }
+            #[doc = "Auto baud rate request"]
+            pub fn set_abrrq(&mut self, val: super::vals::Abrrq) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Send break request"]
+            pub const fn sbkrq(&self) -> super::vals::Sbkrq {
+                let val = (self.0 >> 1usize) & 0x01;
+                super::vals::Sbkrq(val as u8)
+            }
+            #[doc = "Send break request"]
+            pub fn set_sbkrq(&mut self, val: super::vals::Sbkrq) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Mute mode request"]
+            pub const fn mmrq(&self) -> super::vals::Mmrq {
+                let val = (self.0 >> 2usize) & 0x01;
+                super::vals::Mmrq(val as u8)
+            }
+            #[doc = "Mute mode request"]
+            pub fn set_mmrq(&mut self, val: super::vals::Mmrq) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
+            }
+            #[doc = "Receive data flush request"]
+            pub const fn rxfrq(&self) -> super::vals::Rxfrq {
+                let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Rxfrq(val as u8)
+            }
+            #[doc = "Receive data flush request"]
+            pub fn set_rxfrq(&mut self, val: super::vals::Rxfrq) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Transmit data flush request"]
+            pub const fn txfrq(&self) -> super::vals::Txfrq {
+                let val = (self.0 >> 4usize) & 0x01;
+                super::vals::Txfrq(val as u8)
+            }
+            #[doc = "Transmit data flush request"]
+            pub fn set_txfrq(&mut self, val: super::vals::Txfrq) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
+            }
+        }
+        impl Default for Rqr {
+            fn default() -> Rqr {
+                Rqr(0)
             }
         }
         #[doc = "Control register 2"]
@@ -7430,208 +5927,186 @@ pub mod usart_v2 {
                 Cr2(0)
             }
         }
-        #[doc = "Control register 1"]
+        #[doc = "Control register 3"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr1(pub u32);
-        impl Cr1 {
-            #[doc = "USART enable"]
-            pub const fn ue(&self) -> bool {
+        pub struct Cr3(pub u32);
+        impl Cr3 {
+            #[doc = "Error interrupt enable"]
+            pub const fn eie(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "USART enable"]
-            pub fn set_ue(&mut self, val: bool) {
+            #[doc = "Error interrupt enable"]
+            pub fn set_eie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "USART enable in Stop mode"]
-            pub const fn uesm(&self) -> bool {
+            #[doc = "IrDA mode enable"]
+            pub const fn iren(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "USART enable in Stop mode"]
-            pub fn set_uesm(&mut self, val: bool) {
+            #[doc = "IrDA mode enable"]
+            pub fn set_iren(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Receiver enable"]
-            pub const fn re(&self) -> bool {
+            #[doc = "IrDA low-power"]
+            pub const fn irlp(&self) -> super::vals::Irlp {
                 let val = (self.0 >> 2usize) & 0x01;
-                val != 0
+                super::vals::Irlp(val as u8)
             }
-            #[doc = "Receiver enable"]
-            pub fn set_re(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            #[doc = "IrDA low-power"]
+            pub fn set_irlp(&mut self, val: super::vals::Irlp) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
             }
-            #[doc = "Transmitter enable"]
-            pub const fn te(&self) -> bool {
+            #[doc = "Half-duplex selection"]
+            pub const fn hdsel(&self) -> super::vals::Hdsel {
                 let val = (self.0 >> 3usize) & 0x01;
-                val != 0
+                super::vals::Hdsel(val as u8)
             }
-            #[doc = "Transmitter enable"]
-            pub fn set_te(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "Half-duplex selection"]
+            pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
             }
-            #[doc = "IDLE interrupt enable"]
-            pub const fn idleie(&self) -> bool {
+            #[doc = "Smartcard NACK enable"]
+            pub const fn nack(&self) -> bool {
                 let val = (self.0 >> 4usize) & 0x01;
                 val != 0
             }
-            #[doc = "IDLE interrupt enable"]
-            pub fn set_idleie(&mut self, val: bool) {
+            #[doc = "Smartcard NACK enable"]
+            pub fn set_nack(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "RXNE interrupt enable"]
-            pub const fn rxneie(&self) -> bool {
+            #[doc = "Smartcard mode enable"]
+            pub const fn scen(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "RXNE interrupt enable"]
-            pub fn set_rxneie(&mut self, val: bool) {
+            #[doc = "Smartcard mode enable"]
+            pub fn set_scen(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Transmission complete interrupt enable"]
-            pub const fn tcie(&self) -> bool {
+            #[doc = "DMA enable receiver"]
+            pub const fn dmar(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transmission complete interrupt enable"]
-            pub fn set_tcie(&mut self, val: bool) {
+            #[doc = "DMA enable receiver"]
+            pub fn set_dmar(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "interrupt enable"]
-            pub const fn txeie(&self) -> bool {
+            #[doc = "DMA enable transmitter"]
+            pub const fn dmat(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "interrupt enable"]
-            pub fn set_txeie(&mut self, val: bool) {
+            #[doc = "DMA enable transmitter"]
+            pub fn set_dmat(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "PE interrupt enable"]
-            pub const fn peie(&self) -> bool {
+            #[doc = "RTS enable"]
+            pub const fn rtse(&self) -> bool {
                 let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "PE interrupt enable"]
-            pub fn set_peie(&mut self, val: bool) {
+            #[doc = "RTS enable"]
+            pub fn set_rtse(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Parity selection"]
-            pub const fn ps(&self) -> super::vals::Ps {
+            #[doc = "CTS enable"]
+            pub const fn ctse(&self) -> bool {
                 let val = (self.0 >> 9usize) & 0x01;
-                super::vals::Ps(val as u8)
+                val != 0
             }
-            #[doc = "Parity selection"]
-            pub fn set_ps(&mut self, val: super::vals::Ps) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
+            #[doc = "CTS enable"]
+            pub fn set_ctse(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
             }
-            #[doc = "Parity control enable"]
-            pub const fn pce(&self) -> bool {
+            #[doc = "CTS interrupt enable"]
+            pub const fn ctsie(&self) -> bool {
                 let val = (self.0 >> 10usize) & 0x01;
                 val != 0
             }
-            #[doc = "Parity control enable"]
-            pub fn set_pce(&mut self, val: bool) {
+            #[doc = "CTS interrupt enable"]
+            pub fn set_ctsie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
             }
-            #[doc = "Receiver wakeup method"]
-            pub const fn wake(&self) -> bool {
+            #[doc = "One sample bit method enable"]
+            pub const fn onebit(&self) -> super::vals::Onebit {
                 let val = (self.0 >> 11usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Receiver wakeup method"]
-            pub fn set_wake(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
-            }
-            #[doc = "Word length"]
-            pub const fn m0(&self) -> super::vals::M0 {
-                let val = (self.0 >> 12usize) & 0x01;
-                super::vals::M0(val as u8)
+                super::vals::Onebit(val as u8)
             }
-            #[doc = "Word length"]
-            pub fn set_m0(&mut self, val: super::vals::M0) {
-                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
+            #[doc = "One sample bit method enable"]
+            pub fn set_onebit(&mut self, val: super::vals::Onebit) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
             }
-            #[doc = "Word length"]
-            pub const fn m1(&self) -> super::vals::M1 {
+            #[doc = "Overrun Disable"]
+            pub const fn ovrdis(&self) -> super::vals::Ovrdis {
                 let val = (self.0 >> 12usize) & 0x01;
-                super::vals::M1(val as u8)
+                super::vals::Ovrdis(val as u8)
             }
-            #[doc = "Word length"]
-            pub fn set_m1(&mut self, val: super::vals::M1) {
+            #[doc = "Overrun Disable"]
+            pub fn set_ovrdis(&mut self, val: super::vals::Ovrdis) {
                 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
             }
-            #[doc = "Mute mode enable"]
-            pub const fn mme(&self) -> bool {
+            #[doc = "DMA Disable on Reception Error"]
+            pub const fn ddre(&self) -> bool {
                 let val = (self.0 >> 13usize) & 0x01;
                 val != 0
             }
-            #[doc = "Mute mode enable"]
-            pub fn set_mme(&mut self, val: bool) {
+            #[doc = "DMA Disable on Reception Error"]
+            pub fn set_ddre(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
             }
-            #[doc = "Character match interrupt enable"]
-            pub const fn cmie(&self) -> bool {
+            #[doc = "Driver enable mode"]
+            pub const fn dem(&self) -> bool {
                 let val = (self.0 >> 14usize) & 0x01;
                 val != 0
             }
-            #[doc = "Character match interrupt enable"]
-            pub fn set_cmie(&mut self, val: bool) {
+            #[doc = "Driver enable mode"]
+            pub fn set_dem(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
             }
-            #[doc = "Oversampling mode"]
-            pub fn over(&self, n: usize) -> super::vals::Over {
-                assert!(n < 1usize);
-                let offs = 15usize + n * 0usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Over(val as u8)
-            }
-            #[doc = "Oversampling mode"]
-            pub fn set_over(&mut self, n: usize, val: super::vals::Over) {
-                assert!(n < 1usize);
-                let offs = 15usize + n * 0usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-            #[doc = "Driver Enable deassertion time"]
-            pub const fn dedt(&self) -> u8 {
-                let val = (self.0 >> 16usize) & 0x1f;
-                val as u8
+            #[doc = "Driver enable polarity selection"]
+            pub const fn dep(&self) -> super::vals::Dep {
+                let val = (self.0 >> 15usize) & 0x01;
+                super::vals::Dep(val as u8)
             }
-            #[doc = "Driver Enable deassertion time"]
-            pub fn set_dedt(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
+            #[doc = "Driver enable polarity selection"]
+            pub fn set_dep(&mut self, val: super::vals::Dep) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
             }
-            #[doc = "Driver Enable assertion time"]
-            pub const fn deat(&self) -> u8 {
-                let val = (self.0 >> 21usize) & 0x1f;
+            #[doc = "Smartcard auto-retry count"]
+            pub const fn scarcnt(&self) -> u8 {
+                let val = (self.0 >> 17usize) & 0x07;
                 val as u8
             }
-            #[doc = "Driver Enable assertion time"]
-            pub fn set_deat(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x1f << 21usize)) | (((val as u32) & 0x1f) << 21usize);
+            #[doc = "Smartcard auto-retry count"]
+            pub fn set_scarcnt(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x07 << 17usize)) | (((val as u32) & 0x07) << 17usize);
             }
-            #[doc = "Receiver timeout interrupt enable"]
-            pub const fn rtoie(&self) -> bool {
-                let val = (self.0 >> 26usize) & 0x01;
-                val != 0
+            #[doc = "Wakeup from Stop mode interrupt flag selection"]
+            pub const fn wus(&self) -> super::vals::Wus {
+                let val = (self.0 >> 20usize) & 0x03;
+                super::vals::Wus(val as u8)
             }
-            #[doc = "Receiver timeout interrupt enable"]
-            pub fn set_rtoie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+            #[doc = "Wakeup from Stop mode interrupt flag selection"]
+            pub fn set_wus(&mut self, val: super::vals::Wus) {
+                self.0 = (self.0 & !(0x03 << 20usize)) | (((val.0 as u32) & 0x03) << 20usize);
             }
-            #[doc = "End of Block interrupt enable"]
-            pub const fn eobie(&self) -> bool {
-                let val = (self.0 >> 27usize) & 0x01;
+            #[doc = "Wakeup from Stop mode interrupt enable"]
+            pub const fn wufie(&self) -> bool {
+                let val = (self.0 >> 22usize) & 0x01;
                 val != 0
             }
-            #[doc = "End of Block interrupt enable"]
-            pub fn set_eobie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+            #[doc = "Wakeup from Stop mode interrupt enable"]
+            pub fn set_wufie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
             }
         }
-        impl Default for Cr1 {
-            fn default() -> Cr1 {
-                Cr1(0)
+        impl Default for Cr3 {
+            fn default() -> Cr3 {
+                Cr3(0)
             }
         }
         #[doc = "Interrupt & status register"]
@@ -7843,11 +6318,333 @@ pub mod usart_v2 {
                 Ixr(0)
             }
         }
+        #[doc = "Receiver timeout register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Rtor(pub u32);
+        impl Rtor {
+            #[doc = "Receiver timeout value"]
+            pub const fn rto(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0x00ff_ffff;
+                val as u32
+            }
+            #[doc = "Receiver timeout value"]
+            pub fn set_rto(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+            }
+            #[doc = "Block Length"]
+            pub const fn blen(&self) -> u8 {
+                let val = (self.0 >> 24usize) & 0xff;
+                val as u8
+            }
+            #[doc = "Block Length"]
+            pub fn set_blen(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize);
+            }
+        }
+        impl Default for Rtor {
+            fn default() -> Rtor {
+                Rtor(0)
+            }
+        }
+        #[doc = "Guard time and prescaler register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Gtpr(pub u32);
+        impl Gtpr {
+            #[doc = "Prescaler value"]
+            pub const fn psc(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
+            }
+            #[doc = "Prescaler value"]
+            pub fn set_psc(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            }
+            #[doc = "Guard time value"]
+            pub const fn gt(&self) -> u8 {
+                let val = (self.0 >> 8usize) & 0xff;
+                val as u8
+            }
+            #[doc = "Guard time value"]
+            pub fn set_gt(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+            }
+        }
+        impl Default for Gtpr {
+            fn default() -> Gtpr {
+                Gtpr(0)
+            }
+        }
+        #[doc = "Data register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Dr(pub u32);
+        impl Dr {
+            #[doc = "data value"]
+            pub const fn dr(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x01ff;
+                val as u16
+            }
+            #[doc = "data value"]
+            pub fn set_dr(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+            }
+        }
+        impl Default for Dr {
+            fn default() -> Dr {
+                Dr(0)
+            }
+        }
+    }
+}
+pub mod generic {
+    use core::marker::PhantomData;
+    #[derive(Copy, Clone)]
+    pub struct RW;
+    #[derive(Copy, Clone)]
+    pub struct R;
+    #[derive(Copy, Clone)]
+    pub struct W;
+    mod sealed {
+        use super::*;
+        pub trait Access {}
+        impl Access for R {}
+        impl Access for W {}
+        impl Access for RW {}
+    }
+    pub trait Access: sealed::Access + Copy {}
+    impl Access for R {}
+    impl Access for W {}
+    impl Access for RW {}
+    pub trait Read: Access {}
+    impl Read for RW {}
+    impl Read for R {}
+    pub trait Write: Access {}
+    impl Write for RW {}
+    impl Write for W {}
+    #[derive(Copy, Clone)]
+    pub struct Reg<T: Copy, A: Access> {
+        ptr: *mut u8,
+        phantom: PhantomData<*mut (T, A)>,
+    }
+    unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
+    unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
+    impl<T: Copy, A: Access> Reg<T, A> {
+        pub fn from_ptr(ptr: *mut u8) -> Self {
+            Self {
+                ptr,
+                phantom: PhantomData,
+            }
+        }
+        pub fn ptr(&self) -> *mut T {
+            self.ptr as _
+        }
+    }
+    impl<T: Copy, A: Read> Reg<T, A> {
+        pub unsafe fn read(&self) -> T {
+            (self.ptr as *mut T).read_volatile()
+        }
+    }
+    impl<T: Copy, A: Write> Reg<T, A> {
+        pub unsafe fn write_value(&self, val: T) {
+            (self.ptr as *mut T).write_volatile(val)
+        }
+    }
+    impl<T: Default + Copy, A: Write> Reg<T, A> {
+        pub unsafe fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+            let mut val = Default::default();
+            let res = f(&mut val);
+            self.write_value(val);
+            res
+        }
+    }
+    impl<T: Copy, A: Read + Write> Reg<T, A> {
+        pub unsafe fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+            let mut val = self.read();
+            let res = f(&mut val);
+            self.write_value(val);
+            res
+        }
+    }
+}
+pub mod usart_v1 {
+    use crate::generic::*;
+    #[doc = "Universal asynchronous receiver transmitter"]
+    #[derive(Copy, Clone)]
+    pub struct Uart(pub *mut u8);
+    unsafe impl Send for Uart {}
+    unsafe impl Sync for Uart {}
+    impl Uart {
+        #[doc = "Status register"]
+        pub fn sr(self) -> Reg<regs::Sr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "Data register"]
+        pub fn dr(self) -> Reg<regs::Dr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "Baud rate register"]
+        pub fn brr(self) -> Reg<regs::Brr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "Control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "Control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "Control register 3"]
+        pub fn cr3(self) -> Reg<regs::Cr3, RW> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+    }
+    #[doc = "Universal synchronous asynchronous receiver transmitter"]
+    #[derive(Copy, Clone)]
+    pub struct Usart(pub *mut u8);
+    unsafe impl Send for Usart {}
+    unsafe impl Sync for Usart {}
+    impl Usart {
+        #[doc = "Status register"]
+        pub fn sr(self) -> Reg<regs::Sr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "Data register"]
+        pub fn dr(self) -> Reg<regs::Dr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "Baud rate register"]
+        pub fn brr(self) -> Reg<regs::Brr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "Control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "Control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2Usart, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "Control register 3"]
+        pub fn cr3(self) -> Reg<regs::Cr3Usart, RW> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "Guard time and prescaler register"]
+        pub fn gtpr(self) -> Reg<regs::Gtpr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        }
+    }
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "Status register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct SrUsart(pub u32);
+        impl SrUsart {
+            #[doc = "Parity error"]
+            pub const fn pe(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Parity error"]
+            pub fn set_pe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Framing error"]
+            pub const fn fe(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Framing error"]
+            pub fn set_fe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Noise error flag"]
+            pub const fn ne(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Noise error flag"]
+            pub fn set_ne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "Overrun error"]
+            pub const fn ore(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Overrun error"]
+            pub fn set_ore(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "IDLE line detected"]
+            pub const fn idle(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
+                val != 0
+            }
+            #[doc = "IDLE line detected"]
+            pub fn set_idle(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            }
+            #[doc = "Read data register not empty"]
+            pub const fn rxne(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Read data register not empty"]
+            pub fn set_rxne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Transmission complete"]
+            pub const fn tc(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transmission complete"]
+            pub fn set_tc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Transmit data register empty"]
+            pub const fn txe(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transmit data register empty"]
+            pub fn set_txe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "LIN break detection flag"]
+            pub const fn lbd(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "LIN break detection flag"]
+            pub fn set_lbd(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "CTS flag"]
+            pub const fn cts(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
+                val != 0
+            }
+            #[doc = "CTS flag"]
+            pub fn set_cts(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            }
+        }
+        impl Default for SrUsart {
+            fn default() -> SrUsart {
+                SrUsart(0)
+            }
+        }
         #[doc = "Control register 3"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr3(pub u32);
-        impl Cr3 {
+        pub struct Cr3Usart(pub u32);
+        impl Cr3Usart {
             #[doc = "Error interrupt enable"]
             pub const fn eie(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
@@ -7947,544 +6744,530 @@ pub mod usart_v2 {
             pub fn set_ctsie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
             }
-            #[doc = "One sample bit method enable"]
-            pub const fn onebit(&self) -> super::vals::Onebit {
-                let val = (self.0 >> 11usize) & 0x01;
-                super::vals::Onebit(val as u8)
+        }
+        impl Default for Cr3Usart {
+            fn default() -> Cr3Usart {
+                Cr3Usart(0)
             }
-            #[doc = "One sample bit method enable"]
-            pub fn set_onebit(&mut self, val: super::vals::Onebit) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
+        }
+        #[doc = "Control register 2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr2Usart(pub u32);
+        impl Cr2Usart {
+            #[doc = "Address of the USART node"]
+            pub const fn add(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x0f;
+                val as u8
             }
-            #[doc = "Overrun Disable"]
-            pub const fn ovrdis(&self) -> super::vals::Ovrdis {
-                let val = (self.0 >> 12usize) & 0x01;
-                super::vals::Ovrdis(val as u8)
+            #[doc = "Address of the USART node"]
+            pub fn set_add(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
             }
-            #[doc = "Overrun Disable"]
-            pub fn set_ovrdis(&mut self, val: super::vals::Ovrdis) {
-                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
+            #[doc = "lin break detection length"]
+            pub const fn lbdl(&self) -> super::vals::Lbdl {
+                let val = (self.0 >> 5usize) & 0x01;
+                super::vals::Lbdl(val as u8)
             }
-            #[doc = "DMA Disable on Reception Error"]
-            pub const fn ddre(&self) -> bool {
-                let val = (self.0 >> 13usize) & 0x01;
+            #[doc = "lin break detection length"]
+            pub fn set_lbdl(&mut self, val: super::vals::Lbdl) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
+            }
+            #[doc = "LIN break detection interrupt enable"]
+            pub const fn lbdie(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "DMA Disable on Reception Error"]
-            pub fn set_ddre(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            #[doc = "LIN break detection interrupt enable"]
+            pub fn set_lbdie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Driver enable mode"]
-            pub const fn dem(&self) -> bool {
-                let val = (self.0 >> 14usize) & 0x01;
+            #[doc = "Last bit clock pulse"]
+            pub const fn lbcl(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "Driver enable mode"]
-            pub fn set_dem(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            #[doc = "Last bit clock pulse"]
+            pub fn set_lbcl(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Driver enable polarity selection"]
-            pub const fn dep(&self) -> super::vals::Dep {
-                let val = (self.0 >> 15usize) & 0x01;
-                super::vals::Dep(val as u8)
+            #[doc = "Clock phase"]
+            pub const fn cpha(&self) -> super::vals::Cpha {
+                let val = (self.0 >> 9usize) & 0x01;
+                super::vals::Cpha(val as u8)
             }
-            #[doc = "Driver enable polarity selection"]
-            pub fn set_dep(&mut self, val: super::vals::Dep) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            #[doc = "Clock phase"]
+            pub fn set_cpha(&mut self, val: super::vals::Cpha) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
             }
-            #[doc = "Smartcard auto-retry count"]
-            pub const fn scarcnt(&self) -> u8 {
-                let val = (self.0 >> 17usize) & 0x07;
-                val as u8
+            #[doc = "Clock polarity"]
+            pub const fn cpol(&self) -> super::vals::Cpol {
+                let val = (self.0 >> 10usize) & 0x01;
+                super::vals::Cpol(val as u8)
             }
-            #[doc = "Smartcard auto-retry count"]
-            pub fn set_scarcnt(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x07 << 17usize)) | (((val as u32) & 0x07) << 17usize);
+            #[doc = "Clock polarity"]
+            pub fn set_cpol(&mut self, val: super::vals::Cpol) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
             }
-            #[doc = "Wakeup from Stop mode interrupt flag selection"]
-            pub const fn wus(&self) -> super::vals::Wus {
-                let val = (self.0 >> 20usize) & 0x03;
-                super::vals::Wus(val as u8)
+            #[doc = "Clock enable"]
+            pub const fn clken(&self) -> bool {
+                let val = (self.0 >> 11usize) & 0x01;
+                val != 0
             }
-            #[doc = "Wakeup from Stop mode interrupt flag selection"]
-            pub fn set_wus(&mut self, val: super::vals::Wus) {
-                self.0 = (self.0 & !(0x03 << 20usize)) | (((val.0 as u32) & 0x03) << 20usize);
+            #[doc = "Clock enable"]
+            pub fn set_clken(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
             }
-            #[doc = "Wakeup from Stop mode interrupt enable"]
-            pub const fn wufie(&self) -> bool {
-                let val = (self.0 >> 22usize) & 0x01;
+            #[doc = "STOP bits"]
+            pub const fn stop(&self) -> super::vals::Stop {
+                let val = (self.0 >> 12usize) & 0x03;
+                super::vals::Stop(val as u8)
+            }
+            #[doc = "STOP bits"]
+            pub fn set_stop(&mut self, val: super::vals::Stop) {
+                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+            }
+            #[doc = "LIN mode enable"]
+            pub const fn linen(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
                 val != 0
             }
-            #[doc = "Wakeup from Stop mode interrupt enable"]
-            pub fn set_wufie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+            #[doc = "LIN mode enable"]
+            pub fn set_linen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
             }
         }
-        impl Default for Cr3 {
-            fn default() -> Cr3 {
-                Cr3(0)
+        impl Default for Cr2Usart {
+            fn default() -> Cr2Usart {
+                Cr2Usart(0)
             }
         }
-        #[doc = "Request register"]
+        #[doc = "Control register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Rqr(pub u32);
-        impl Rqr {
-            #[doc = "Auto baud rate request"]
-            pub const fn abrrq(&self) -> super::vals::Abrrq {
+        pub struct Cr1(pub u32);
+        impl Cr1 {
+            #[doc = "Send break"]
+            pub const fn sbk(&self) -> super::vals::Sbk {
                 let val = (self.0 >> 0usize) & 0x01;
-                super::vals::Abrrq(val as u8)
+                super::vals::Sbk(val as u8)
             }
-            #[doc = "Auto baud rate request"]
-            pub fn set_abrrq(&mut self, val: super::vals::Abrrq) {
+            #[doc = "Send break"]
+            pub fn set_sbk(&mut self, val: super::vals::Sbk) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
             }
-            #[doc = "Send break request"]
-            pub const fn sbkrq(&self) -> super::vals::Sbkrq {
+            #[doc = "Receiver wakeup"]
+            pub const fn rwu(&self) -> super::vals::Rwu {
                 let val = (self.0 >> 1usize) & 0x01;
-                super::vals::Sbkrq(val as u8)
+                super::vals::Rwu(val as u8)
             }
-            #[doc = "Send break request"]
-            pub fn set_sbkrq(&mut self, val: super::vals::Sbkrq) {
+            #[doc = "Receiver wakeup"]
+            pub fn set_rwu(&mut self, val: super::vals::Rwu) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
             }
-            #[doc = "Mute mode request"]
-            pub const fn mmrq(&self) -> super::vals::Mmrq {
+            #[doc = "Receiver enable"]
+            pub const fn re(&self) -> bool {
                 let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Mmrq(val as u8)
-            }
-            #[doc = "Mute mode request"]
-            pub fn set_mmrq(&mut self, val: super::vals::Mmrq) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Receive data flush request"]
-            pub const fn rxfrq(&self) -> super::vals::Rxfrq {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Rxfrq(val as u8)
-            }
-            #[doc = "Receive data flush request"]
-            pub fn set_rxfrq(&mut self, val: super::vals::Rxfrq) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Transmit data flush request"]
-            pub const fn txfrq(&self) -> super::vals::Txfrq {
-                let val = (self.0 >> 4usize) & 0x01;
-                super::vals::Txfrq(val as u8)
-            }
-            #[doc = "Transmit data flush request"]
-            pub fn set_txfrq(&mut self, val: super::vals::Txfrq) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
-            }
-        }
-        impl Default for Rqr {
-            fn default() -> Rqr {
-                Rqr(0)
-            }
-        }
-    }
-}
-pub mod spi_v1 {
-    use crate::generic::*;
-    #[doc = "Serial peripheral interface"]
-    #[derive(Copy, Clone)]
-    pub struct Spi(pub *mut u8);
-    unsafe impl Send for Spi {}
-    unsafe impl Sync for Spi {}
-    impl Spi {
-        #[doc = "control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::Sr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "data register"]
-        pub fn dr(self) -> Reg<regs::Dr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "CRC polynomial register"]
-        pub fn crcpr(self) -> Reg<regs::Crcpr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "RX CRC register"]
-        pub fn rxcrcr(self) -> Reg<regs::Rxcrcr, R> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-        #[doc = "TX CRC register"]
-        pub fn txcrcr(self) -> Reg<regs::Txcrcr, R> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "TX CRC register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Txcrcr(pub u32);
-        impl Txcrcr {
-            #[doc = "Tx CRC register"]
-            pub const fn tx_crc(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "Tx CRC register"]
-            pub fn set_tx_crc(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
-        }
-        impl Default for Txcrcr {
-            fn default() -> Txcrcr {
-                Txcrcr(0)
-            }
-        }
-        #[doc = "status register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Sr(pub u32);
-        impl Sr {
-            #[doc = "Receive buffer not empty"]
-            pub const fn rxne(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Receive buffer not empty"]
-            pub fn set_rxne(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Receiver enable"]
+            pub fn set_re(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Transmit buffer empty"]
-            pub const fn txe(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
+            #[doc = "Transmitter enable"]
+            pub const fn te(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transmit buffer empty"]
-            pub fn set_txe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "Transmitter enable"]
+            pub fn set_te(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-            #[doc = "CRC error flag"]
-            pub const fn crcerr(&self) -> bool {
+            #[doc = "IDLE interrupt enable"]
+            pub const fn idleie(&self) -> bool {
                 let val = (self.0 >> 4usize) & 0x01;
                 val != 0
             }
-            #[doc = "CRC error flag"]
-            pub fn set_crcerr(&mut self, val: bool) {
+            #[doc = "IDLE interrupt enable"]
+            pub fn set_idleie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "Mode fault"]
-            pub const fn modf(&self) -> bool {
+            #[doc = "RXNE interrupt enable"]
+            pub const fn rxneie(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Mode fault"]
-            pub fn set_modf(&mut self, val: bool) {
+            #[doc = "RXNE interrupt enable"]
+            pub fn set_rxneie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Overrun flag"]
-            pub const fn ovr(&self) -> bool {
+            #[doc = "Transmission complete interrupt enable"]
+            pub const fn tcie(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Overrun flag"]
-            pub fn set_ovr(&mut self, val: bool) {
+            #[doc = "Transmission complete interrupt enable"]
+            pub fn set_tcie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Busy flag"]
-            pub const fn bsy(&self) -> bool {
+            #[doc = "TXE interrupt enable"]
+            pub const fn txeie(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Busy flag"]
-            pub fn set_bsy(&mut self, val: bool) {
+            #[doc = "TXE interrupt enable"]
+            pub fn set_txeie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "TI frame format error"]
-            pub const fn fre(&self) -> bool {
+            #[doc = "PE interrupt enable"]
+            pub const fn peie(&self) -> bool {
                 let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "TI frame format error"]
-            pub fn set_fre(&mut self, val: bool) {
+            #[doc = "PE interrupt enable"]
+            pub fn set_peie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-        }
-        impl Default for Sr {
-            fn default() -> Sr {
-                Sr(0)
+            #[doc = "Parity selection"]
+            pub const fn ps(&self) -> super::vals::Ps {
+                let val = (self.0 >> 9usize) & 0x01;
+                super::vals::Ps(val as u8)
             }
-        }
-        #[doc = "CRC polynomial register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Crcpr(pub u32);
-        impl Crcpr {
-            #[doc = "CRC polynomial register"]
-            pub const fn crcpoly(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
+            #[doc = "Parity selection"]
+            pub fn set_ps(&mut self, val: super::vals::Ps) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
             }
-            #[doc = "CRC polynomial register"]
-            pub fn set_crcpoly(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "Parity control enable"]
+            pub const fn pce(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Parity control enable"]
+            pub fn set_pce(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+            }
+            #[doc = "Wakeup method"]
+            pub const fn wake(&self) -> super::vals::Wake {
+                let val = (self.0 >> 11usize) & 0x01;
+                super::vals::Wake(val as u8)
+            }
+            #[doc = "Wakeup method"]
+            pub fn set_wake(&mut self, val: super::vals::Wake) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
+            }
+            #[doc = "Word length"]
+            pub const fn m(&self) -> super::vals::M {
+                let val = (self.0 >> 12usize) & 0x01;
+                super::vals::M(val as u8)
+            }
+            #[doc = "Word length"]
+            pub fn set_m(&mut self, val: super::vals::M) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
+            }
+            #[doc = "USART enable"]
+            pub const fn ue(&self) -> bool {
+                let val = (self.0 >> 13usize) & 0x01;
+                val != 0
+            }
+            #[doc = "USART enable"]
+            pub fn set_ue(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
             }
         }
-        impl Default for Crcpr {
-            fn default() -> Crcpr {
-                Crcpr(0)
+        impl Default for Cr1 {
+            fn default() -> Cr1 {
+                Cr1(0)
             }
         }
-        #[doc = "data register"]
+        #[doc = "Baud rate register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dr(pub u32);
-        impl Dr {
-            #[doc = "Data register"]
-            pub const fn dr(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
+        pub struct Brr(pub u32);
+        impl Brr {
+            #[doc = "fraction of USARTDIV"]
+            pub const fn div_fraction(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "fraction of USARTDIV"]
+            pub fn set_div_fraction(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+            }
+            #[doc = "mantissa of USARTDIV"]
+            pub const fn div_mantissa(&self) -> u16 {
+                let val = (self.0 >> 4usize) & 0x0fff;
                 val as u16
             }
-            #[doc = "Data register"]
-            pub fn set_dr(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "mantissa of USARTDIV"]
+            pub fn set_div_mantissa(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize);
             }
         }
-        impl Default for Dr {
-            fn default() -> Dr {
-                Dr(0)
+        impl Default for Brr {
+            fn default() -> Brr {
+                Brr(0)
             }
         }
-        #[doc = "control register 2"]
+        #[doc = "Control register 3"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2(pub u32);
-        impl Cr2 {
-            #[doc = "Rx buffer DMA enable"]
-            pub const fn rxdmaen(&self) -> bool {
+        pub struct Cr3(pub u32);
+        impl Cr3 {
+            #[doc = "Error interrupt enable"]
+            pub const fn eie(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Rx buffer DMA enable"]
-            pub fn set_rxdmaen(&mut self, val: bool) {
+            #[doc = "Error interrupt enable"]
+            pub fn set_eie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Tx buffer DMA enable"]
-            pub const fn txdmaen(&self) -> bool {
+            #[doc = "IrDA mode enable"]
+            pub const fn iren(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Tx buffer DMA enable"]
-            pub fn set_txdmaen(&mut self, val: bool) {
+            #[doc = "IrDA mode enable"]
+            pub fn set_iren(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "SS output enable"]
-            pub const fn ssoe(&self) -> bool {
+            #[doc = "IrDA low-power"]
+            pub const fn irlp(&self) -> super::vals::Irlp {
                 let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "SS output enable"]
-            pub fn set_ssoe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Frame format"]
-            pub const fn frf(&self) -> super::vals::Frf {
-                let val = (self.0 >> 4usize) & 0x01;
-                super::vals::Frf(val as u8)
+                super::vals::Irlp(val as u8)
             }
-            #[doc = "Frame format"]
-            pub fn set_frf(&mut self, val: super::vals::Frf) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
+            #[doc = "IrDA low-power"]
+            pub fn set_irlp(&mut self, val: super::vals::Irlp) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
             }
-            #[doc = "Error interrupt enable"]
-            pub const fn errie(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
+            #[doc = "Half-duplex selection"]
+            pub const fn hdsel(&self) -> super::vals::Hdsel {
+                let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Hdsel(val as u8)
             }
-            #[doc = "Error interrupt enable"]
-            pub fn set_errie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            #[doc = "Half-duplex selection"]
+            pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
             }
-            #[doc = "RX buffer not empty interrupt enable"]
-            pub const fn rxneie(&self) -> bool {
+            #[doc = "DMA enable receiver"]
+            pub const fn dmar(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "RX buffer not empty interrupt enable"]
-            pub fn set_rxneie(&mut self, val: bool) {
+            #[doc = "DMA enable receiver"]
+            pub fn set_dmar(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Tx buffer empty interrupt enable"]
-            pub const fn txeie(&self) -> bool {
+            #[doc = "DMA enable transmitter"]
+            pub const fn dmat(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Tx buffer empty interrupt enable"]
-            pub fn set_txeie(&mut self, val: bool) {
+            #[doc = "DMA enable transmitter"]
+            pub fn set_dmat(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
         }
-        impl Default for Cr2 {
-            fn default() -> Cr2 {
-                Cr2(0)
+        impl Default for Cr3 {
+            fn default() -> Cr3 {
+                Cr3(0)
             }
         }
-        #[doc = "control register 1"]
+        #[doc = "Control register 2"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr1(pub u32);
-        impl Cr1 {
-            #[doc = "Clock phase"]
-            pub const fn cpha(&self) -> super::vals::Cpha {
-                let val = (self.0 >> 0usize) & 0x01;
-                super::vals::Cpha(val as u8)
+        pub struct Cr2(pub u32);
+        impl Cr2 {
+            #[doc = "Address of the USART node"]
+            pub const fn add(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x0f;
+                val as u8
             }
-            #[doc = "Clock phase"]
-            pub fn set_cpha(&mut self, val: super::vals::Cpha) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
+            #[doc = "Address of the USART node"]
+            pub fn set_add(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
             }
-            #[doc = "Clock polarity"]
-            pub const fn cpol(&self) -> super::vals::Cpol {
-                let val = (self.0 >> 1usize) & 0x01;
-                super::vals::Cpol(val as u8)
+            #[doc = "lin break detection length"]
+            pub const fn lbdl(&self) -> super::vals::Lbdl {
+                let val = (self.0 >> 5usize) & 0x01;
+                super::vals::Lbdl(val as u8)
             }
-            #[doc = "Clock polarity"]
-            pub fn set_cpol(&mut self, val: super::vals::Cpol) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
+            #[doc = "lin break detection length"]
+            pub fn set_lbdl(&mut self, val: super::vals::Lbdl) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
             }
-            #[doc = "Master selection"]
-            pub const fn mstr(&self) -> super::vals::Mstr {
-                let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Mstr(val as u8)
+            #[doc = "LIN break detection interrupt enable"]
+            pub const fn lbdie(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
             }
-            #[doc = "Master selection"]
-            pub fn set_mstr(&mut self, val: super::vals::Mstr) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
+            #[doc = "LIN break detection interrupt enable"]
+            pub fn set_lbdie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Baud rate control"]
-            pub const fn br(&self) -> super::vals::Br {
-                let val = (self.0 >> 3usize) & 0x07;
-                super::vals::Br(val as u8)
+            #[doc = "STOP bits"]
+            pub const fn stop(&self) -> super::vals::Stop {
+                let val = (self.0 >> 12usize) & 0x03;
+                super::vals::Stop(val as u8)
             }
-            #[doc = "Baud rate control"]
-            pub fn set_br(&mut self, val: super::vals::Br) {
-                self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
+            #[doc = "STOP bits"]
+            pub fn set_stop(&mut self, val: super::vals::Stop) {
+                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
             }
-            #[doc = "SPI enable"]
-            pub const fn spe(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
+            #[doc = "LIN mode enable"]
+            pub const fn linen(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
                 val != 0
             }
-            #[doc = "SPI enable"]
-            pub fn set_spe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            #[doc = "LIN mode enable"]
+            pub fn set_linen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
             }
-            #[doc = "Frame format"]
-            pub const fn lsbfirst(&self) -> super::vals::Lsbfirst {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Lsbfirst(val as u8)
+        }
+        impl Default for Cr2 {
+            fn default() -> Cr2 {
+                Cr2(0)
             }
-            #[doc = "Frame format"]
-            pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+        }
+        #[doc = "Guard time and prescaler register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Gtpr(pub u32);
+        impl Gtpr {
+            #[doc = "Prescaler value"]
+            pub const fn psc(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
             }
-            #[doc = "Internal slave select"]
-            pub const fn ssi(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+            #[doc = "Prescaler value"]
+            pub fn set_psc(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            }
+            #[doc = "Guard time value"]
+            pub const fn gt(&self) -> u8 {
+                let val = (self.0 >> 8usize) & 0xff;
+                val as u8
+            }
+            #[doc = "Guard time value"]
+            pub fn set_gt(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+            }
+        }
+        impl Default for Gtpr {
+            fn default() -> Gtpr {
+                Gtpr(0)
+            }
+        }
+        #[doc = "Status register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Sr(pub u32);
+        impl Sr {
+            #[doc = "Parity error"]
+            pub const fn pe(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Internal slave select"]
-            pub fn set_ssi(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Parity error"]
+            pub fn set_pe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Software slave management"]
-            pub const fn ssm(&self) -> bool {
-                let val = (self.0 >> 9usize) & 0x01;
+            #[doc = "Framing error"]
+            pub const fn fe(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Software slave management"]
-            pub fn set_ssm(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            #[doc = "Framing error"]
+            pub fn set_fe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Receive only"]
-            pub const fn rxonly(&self) -> super::vals::Rxonly {
-                let val = (self.0 >> 10usize) & 0x01;
-                super::vals::Rxonly(val as u8)
+            #[doc = "Noise error flag"]
+            pub const fn ne(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
             }
-            #[doc = "Receive only"]
-            pub fn set_rxonly(&mut self, val: super::vals::Rxonly) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
+            #[doc = "Noise error flag"]
+            pub fn set_ne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Data frame format"]
-            pub const fn dff(&self) -> super::vals::Dff {
-                let val = (self.0 >> 11usize) & 0x01;
-                super::vals::Dff(val as u8)
+            #[doc = "Overrun error"]
+            pub const fn ore(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
             }
-            #[doc = "Data frame format"]
-            pub fn set_dff(&mut self, val: super::vals::Dff) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
+            #[doc = "Overrun error"]
+            pub fn set_ore(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-            #[doc = "CRC transfer next"]
-            pub const fn crcnext(&self) -> super::vals::Crcnext {
-                let val = (self.0 >> 12usize) & 0x01;
-                super::vals::Crcnext(val as u8)
+            #[doc = "IDLE line detected"]
+            pub const fn idle(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
+                val != 0
             }
-            #[doc = "CRC transfer next"]
-            pub fn set_crcnext(&mut self, val: super::vals::Crcnext) {
-                self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
+            #[doc = "IDLE line detected"]
+            pub fn set_idle(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "Hardware CRC calculation enable"]
-            pub const fn crcen(&self) -> bool {
-                let val = (self.0 >> 13usize) & 0x01;
+            #[doc = "Read data register not empty"]
+            pub const fn rxne(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Hardware CRC calculation enable"]
-            pub fn set_crcen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            #[doc = "Read data register not empty"]
+            pub fn set_rxne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Output enable in bidirectional mode"]
-            pub const fn bidioe(&self) -> super::vals::Bidioe {
-                let val = (self.0 >> 14usize) & 0x01;
-                super::vals::Bidioe(val as u8)
+            #[doc = "Transmission complete"]
+            pub const fn tc(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
             }
-            #[doc = "Output enable in bidirectional mode"]
-            pub fn set_bidioe(&mut self, val: super::vals::Bidioe) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
+            #[doc = "Transmission complete"]
+            pub fn set_tc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Bidirectional data mode enable"]
-            pub const fn bidimode(&self) -> super::vals::Bidimode {
-                let val = (self.0 >> 15usize) & 0x01;
-                super::vals::Bidimode(val as u8)
+            #[doc = "Transmit data register empty"]
+            pub const fn txe(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
             }
-            #[doc = "Bidirectional data mode enable"]
-            pub fn set_bidimode(&mut self, val: super::vals::Bidimode) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            #[doc = "Transmit data register empty"]
+            pub fn set_txe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "LIN break detection flag"]
+            pub const fn lbd(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "LIN break detection flag"]
+            pub fn set_lbd(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
         }
-        impl Default for Cr1 {
-            fn default() -> Cr1 {
-                Cr1(0)
+        impl Default for Sr {
+            fn default() -> Sr {
+                Sr(0)
             }
         }
-        #[doc = "RX CRC register"]
+        #[doc = "Data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Rxcrcr(pub u32);
-        impl Rxcrcr {
-            #[doc = "Rx CRC register"]
-            pub const fn rx_crc(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
+        pub struct Dr(pub u32);
+        impl Dr {
+            #[doc = "Data value"]
+            pub const fn dr(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x01ff;
                 val as u16
             }
-            #[doc = "Rx CRC register"]
-            pub fn set_rx_crc(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "Data value"]
+            pub fn set_dr(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
             }
         }
-        impl Default for Rxcrcr {
-            fn default() -> Rxcrcr {
-                Rxcrcr(0)
+        impl Default for Dr {
+            fn default() -> Dr {
+                Dr(0)
             }
         }
     }
@@ -8492,74 +7275,176 @@ pub mod spi_v1 {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Br(pub u8);
-        impl Br {
-            #[doc = "f_PCLK / 2"]
-            pub const DIV2: Self = Self(0);
-            #[doc = "f_PCLK / 4"]
-            pub const DIV4: Self = Self(0x01);
-            #[doc = "f_PCLK / 8"]
-            pub const DIV8: Self = Self(0x02);
-            #[doc = "f_PCLK / 16"]
-            pub const DIV16: Self = Self(0x03);
-            #[doc = "f_PCLK / 32"]
-            pub const DIV32: Self = Self(0x04);
-            #[doc = "f_PCLK / 64"]
-            pub const DIV64: Self = Self(0x05);
-            #[doc = "f_PCLK / 128"]
-            pub const DIV128: Self = Self(0x06);
-            #[doc = "f_PCLK / 256"]
-            pub const DIV256: Self = Self(0x07);
+        pub struct Ps(pub u8);
+        impl Ps {
+            #[doc = "Even parity"]
+            pub const EVEN: Self = Self(0);
+            #[doc = "Odd parity"]
+            pub const ODD: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lsbfirst(pub u8);
-        impl Lsbfirst {
-            #[doc = "Data is transmitted/received with the MSB first"]
-            pub const MSBFIRST: Self = Self(0);
-            #[doc = "Data is transmitted/received with the LSB first"]
-            pub const LSBFIRST: Self = Self(0x01);
+        pub struct Rwu(pub u8);
+        impl Rwu {
+            #[doc = "Receiver in active mode"]
+            pub const ACTIVE: Self = Self(0);
+            #[doc = "Receiver in mute mode"]
+            pub const MUTE: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dff(pub u8);
-        impl Dff {
-            #[doc = "8-bit data frame format is selected for transmission/reception"]
-            pub const EIGHTBIT: Self = Self(0);
-            #[doc = "16-bit data frame format is selected for transmission/reception"]
-            pub const SIXTEENBIT: Self = Self(0x01);
+        pub struct Lbdl(pub u8);
+        impl Lbdl {
+            #[doc = "10-bit break detection"]
+            pub const LBDL10: Self = Self(0);
+            #[doc = "11-bit break detection"]
+            pub const LBDL11: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Crcnext(pub u8);
-        impl Crcnext {
-            #[doc = "Next transmit value is from Tx buffer"]
-            pub const TXBUFFER: Self = Self(0);
-            #[doc = "Next transmit value is from Tx CRC register"]
-            pub const CRC: Self = Self(0x01);
+        pub struct Cpha(pub u8);
+        impl Cpha {
+            #[doc = "The first clock transition is the first data capture edge"]
+            pub const FIRST: Self = Self(0);
+            #[doc = "The second clock transition is the first data capture edge"]
+            pub const SECOND: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Bidimode(pub u8);
-        impl Bidimode {
-            #[doc = "2-line unidirectional data mode selected"]
-            pub const UNIDIRECTIONAL: Self = Self(0);
-            #[doc = "1-line bidirectional data mode selected"]
-            pub const BIDIRECTIONAL: Self = Self(0x01);
+        pub struct Cpol(pub u8);
+        impl Cpol {
+            #[doc = "Steady low value on CK pin outside transmission window"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Steady high value on CK pin outside transmission window"]
+            pub const HIGH: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Frer(pub u8);
-        impl Frer {
-            #[doc = "No frame format error"]
-            pub const NOERROR: Self = Self(0);
-            #[doc = "A frame format error occurred"]
-            pub const ERROR: Self = Self(0x01);
+        pub struct Wake(pub u8);
+        impl Wake {
+            #[doc = "USART wakeup on idle line"]
+            pub const IDLELINE: Self = Self(0);
+            #[doc = "USART wakeup on address mark"]
+            pub const ADDRESSMARK: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mstr(pub u8);
-        impl Mstr {
+        pub struct Hdsel(pub u8);
+        impl Hdsel {
+            #[doc = "Half duplex mode is not selected"]
+            pub const FULLDUPLEX: Self = Self(0);
+            #[doc = "Half duplex mode is selected"]
+            pub const HALFDUPLEX: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Irlp(pub u8);
+        impl Irlp {
+            #[doc = "Normal mode"]
+            pub const NORMAL: Self = Self(0);
+            #[doc = "Low-power mode"]
+            pub const LOWPOWER: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct M(pub u8);
+        impl M {
+            #[doc = "8 data bits"]
+            pub const M8: Self = Self(0);
+            #[doc = "9 data bits"]
+            pub const M9: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Stop(pub u8);
+        impl Stop {
+            #[doc = "1 stop bit"]
+            pub const STOP1: Self = Self(0);
+            #[doc = "0.5 stop bits"]
+            pub const STOP0P5: Self = Self(0x01);
+            #[doc = "2 stop bits"]
+            pub const STOP2: Self = Self(0x02);
+            #[doc = "1.5 stop bits"]
+            pub const STOP1P5: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Sbk(pub u8);
+        impl Sbk {
+            #[doc = "No break character is transmitted"]
+            pub const NOBREAK: Self = Self(0);
+            #[doc = "Break character transmitted"]
+            pub const BREAK: Self = Self(0x01);
+        }
+    }
+}
+pub mod spi_v3 {
+    use crate::generic::*;
+    #[doc = "Serial peripheral interface"]
+    #[derive(Copy, Clone)]
+    pub struct Spi(pub *mut u8);
+    unsafe impl Send for Spi {}
+    unsafe impl Sync for Spi {}
+    impl Spi {
+        #[doc = "control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "configuration register 1"]
+        pub fn cfg1(self) -> Reg<regs::Cfg1, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "configuration register 2"]
+        pub fn cfg2(self) -> Reg<regs::Cfg2, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "Interrupt Enable Register"]
+        pub fn ier(self) -> Reg<regs::Ier, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "Status Register"]
+        pub fn sr(self) -> Reg<regs::Sr, R> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "Interrupt/Status Flags Clear Register"]
+        pub fn ifcr(self) -> Reg<regs::Ifcr, W> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        }
+        #[doc = "Transmit Data Register"]
+        pub fn txdr(self) -> Reg<regs::Txdr, W> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        }
+        #[doc = "Receive Data Register"]
+        pub fn rxdr(self) -> Reg<regs::Rxdr, R> {
+            unsafe { Reg::from_ptr(self.0.add(48usize)) }
+        }
+        #[doc = "Polynomial Register"]
+        pub fn crcpoly(self) -> Reg<regs::Crcpoly, RW> {
+            unsafe { Reg::from_ptr(self.0.add(64usize)) }
+        }
+        #[doc = "Transmitter CRC Register"]
+        pub fn txcrc(self) -> Reg<regs::Txcrc, RW> {
+            unsafe { Reg::from_ptr(self.0.add(68usize)) }
+        }
+        #[doc = "Receiver CRC Register"]
+        pub fn rxcrc(self) -> Reg<regs::Rxcrc, RW> {
+            unsafe { Reg::from_ptr(self.0.add(72usize)) }
+        }
+        #[doc = "Underrun Data Register"]
+        pub fn udrdr(self) -> Reg<regs::Udrdr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(76usize)) }
+        }
+    }
+    pub mod vals {
+        use crate::generic::*;
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Master(pub u8);
+        impl Master {
             #[doc = "Slave configuration"]
             pub const SLAVE: Self = Self(0);
             #[doc = "Master configuration"]
@@ -8567,15 +7452,6 @@ pub mod spi_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Rxonly(pub u8);
-        impl Rxonly {
-            #[doc = "Full duplex (Transmit and receive)"]
-            pub const FULLDUPLEX: Self = Self(0);
-            #[doc = "Output disabled (Receive-only mode)"]
-            pub const OUTPUTDISABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Cpha(pub u8);
         impl Cpha {
             #[doc = "The first clock transition is the first data capture edge"]
@@ -8585,16 +7461,75 @@ pub mod spi_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Iscfg(pub u8);
-        impl Iscfg {
-            #[doc = "Slave - transmit"]
-            pub const SLAVETX: Self = Self(0);
-            #[doc = "Slave - receive"]
-            pub const SLAVERX: Self = Self(0x01);
-            #[doc = "Master - transmit"]
-            pub const MASTERTX: Self = Self(0x02);
-            #[doc = "Master - receive"]
-            pub const MASTERRX: Self = Self(0x03);
+        pub struct Datlen(pub u8);
+        impl Datlen {
+            #[doc = "16 bit data length"]
+            pub const BITS16: Self = Self(0);
+            #[doc = "24 bit data length"]
+            pub const BITS24: Self = Self(0x01);
+            #[doc = "32 bit data length"]
+            pub const BITS32: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Comm(pub u8);
+        impl Comm {
+            #[doc = "Full duplex"]
+            pub const FULLDUPLEX: Self = Self(0);
+            #[doc = "Simplex transmitter only"]
+            pub const TRANSMITTER: Self = Self(0x01);
+            #[doc = "Simplex receiver only"]
+            pub const RECEIVER: Self = Self(0x02);
+            #[doc = "Half duplex"]
+            pub const HALFDUPLEX: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ssiop(pub u8);
+        impl Ssiop {
+            #[doc = "Low level is active for SS signal"]
+            pub const ACTIVELOW: Self = Self(0);
+            #[doc = "High level is active for SS signal"]
+            pub const ACTIVEHIGH: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Datfmt(pub u8);
+        impl Datfmt {
+            #[doc = "The data inside RXDR and TXDR are right aligned"]
+            pub const RIGHTALIGNED: Self = Self(0);
+            #[doc = "The data inside RXDR and TXDR are left aligned"]
+            pub const LEFTALIGNED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Tcrcini(pub u8);
+        impl Tcrcini {
+            #[doc = "All zeros TX CRC initialization pattern"]
+            pub const ALLZEROS: Self = Self(0);
+            #[doc = "All ones TX CRC initialization pattern"]
+            pub const ALLONES: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Mbr(pub u8);
+        impl Mbr {
+            #[doc = "f_spi_ker_ck / 2"]
+            pub const DIV2: Self = Self(0);
+            #[doc = "f_spi_ker_ck / 4"]
+            pub const DIV4: Self = Self(0x01);
+            #[doc = "f_spi_ker_ck / 8"]
+            pub const DIV8: Self = Self(0x02);
+            #[doc = "f_spi_ker_ck / 16"]
+            pub const DIV16: Self = Self(0x03);
+            #[doc = "f_spi_ker_ck / 32"]
+            pub const DIV32: Self = Self(0x04);
+            #[doc = "f_spi_ker_ck / 64"]
+            pub const DIV64: Self = Self(0x05);
+            #[doc = "f_spi_ker_ck / 128"]
+            pub const DIV128: Self = Self(0x06);
+            #[doc = "f_spi_ker_ck / 256"]
+            pub const DIV256: Self = Self(0x07);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -8607,754 +7542,1259 @@ pub mod spi_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Frf(pub u8);
-        impl Frf {
-            #[doc = "SPI Motorola mode"]
-            pub const MOTOROLA: Self = Self(0);
-            #[doc = "SPI TI mode"]
-            pub const TI: Self = Self(0x01);
+        pub struct Udrdet(pub u8);
+        impl Udrdet {
+            #[doc = "Underrun is detected at begin of data frame"]
+            pub const STARTOFFRAME: Self = Self(0);
+            #[doc = "Underrun is detected at end of last data frame"]
+            pub const ENDOFFRAME: Self = Self(0x01);
+            #[doc = "Underrun is detected at begin of active SS signal"]
+            pub const STARTOFSLAVESELECT: Self = Self(0x02);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Bidioe(pub u8);
-        impl Bidioe {
-            #[doc = "Output disabled (receive-only mode)"]
-            pub const OUTPUTDISABLED: Self = Self(0);
-            #[doc = "Output enabled (transmit-only mode)"]
-            pub const OUTPUTENABLED: Self = Self(0x01);
-        }
-    }
-}
-pub mod syscfg_l4 {
-    use crate::generic::*;
-    #[doc = "System configuration controller"]
-    #[derive(Copy, Clone)]
-    pub struct Syscfg(pub *mut u8);
-    unsafe impl Send for Syscfg {}
-    unsafe impl Sync for Syscfg {}
-    impl Syscfg {
-        #[doc = "memory remap register"]
-        pub fn memrmp(self) -> Reg<regs::Memrmp, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        pub struct Rxwne(pub u8);
+        impl Rxwne {
+            #[doc = "Less than 32-bit data frame received"]
+            pub const LESSTHAN32: Self = Self(0);
+            #[doc = "At least 32-bit data frame received"]
+            pub const ATLEAST32: Self = Self(0x01);
         }
-        #[doc = "configuration register 1"]
-        pub fn cfgr1(self) -> Reg<regs::Cfgr1, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "external interrupt configuration register 1"]
-        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
-        }
-        #[doc = "SCSR"]
-        pub fn scsr(self) -> Reg<regs::Scsr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Crc(pub u8);
+        impl Crc {
+            #[doc = "Full size (33/17 bit) CRC polynomial is not used"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Full size (33/17 bit) CRC polynomial is used"]
+            pub const ENABLED: Self = Self(0x01);
         }
-        #[doc = "CFGR2"]
-        pub fn cfgr2(self) -> Reg<regs::Cfgr2, RW> {
-            unsafe { Reg::from_ptr(self.0.add(28usize)) }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Hddir(pub u8);
+        impl Hddir {
+            #[doc = "Receiver in half duplex mode"]
+            pub const RECEIVER: Self = Self(0);
+            #[doc = "Transmitter in half duplex mode"]
+            pub const TRANSMITTER: Self = Self(0x01);
         }
-        #[doc = "SWPR"]
-        pub fn swpr(self) -> Reg<regs::Swpr, W> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Sp(pub u8);
+        impl Sp {
+            #[doc = "Motorola SPI protocol"]
+            pub const MOTOROLA: Self = Self(0);
+            #[doc = "TI SPI protocol"]
+            pub const TI: Self = Self(0x01);
         }
-        #[doc = "SKR"]
-        pub fn skr(self) -> Reg<regs::Skr, W> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Rxplvl(pub u8);
+        impl Rxplvl {
+            #[doc = "Zero frames beyond packing ratio available"]
+            pub const ZEROFRAMES: Self = Self(0);
+            #[doc = "One frame beyond packing ratio available"]
+            pub const ONEFRAME: Self = Self(0x01);
+            #[doc = "Two frame beyond packing ratio available"]
+            pub const TWOFRAMES: Self = Self(0x02);
+            #[doc = "Three frame beyond packing ratio available"]
+            pub const THREEFRAMES: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ssom(pub u8);
+        impl Ssom {
+            #[doc = "SS is asserted until data transfer complete"]
+            pub const ASSERTED: Self = Self(0);
+            #[doc = "Data frames interleaved with SS not asserted during MIDI"]
+            pub const NOTASSERTED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Fthlv(pub u8);
+        impl Fthlv {
+            #[doc = "1 frame"]
+            pub const ONEFRAME: Self = Self(0);
+            #[doc = "2 frames"]
+            pub const TWOFRAMES: Self = Self(0x01);
+            #[doc = "3 frames"]
+            pub const THREEFRAMES: Self = Self(0x02);
+            #[doc = "4 frames"]
+            pub const FOURFRAMES: Self = Self(0x03);
+            #[doc = "5 frames"]
+            pub const FIVEFRAMES: Self = Self(0x04);
+            #[doc = "6 frames"]
+            pub const SIXFRAMES: Self = Self(0x05);
+            #[doc = "7 frames"]
+            pub const SEVENFRAMES: Self = Self(0x06);
+            #[doc = "8 frames"]
+            pub const EIGHTFRAMES: Self = Self(0x07);
+            #[doc = "9 frames"]
+            pub const NINEFRAMES: Self = Self(0x08);
+            #[doc = "10 frames"]
+            pub const TENFRAMES: Self = Self(0x09);
+            #[doc = "11 frames"]
+            pub const ELEVENFRAMES: Self = Self(0x0a);
+            #[doc = "12 frames"]
+            pub const TWELVEFRAMES: Self = Self(0x0b);
+            #[doc = "13 frames"]
+            pub const THIRTEENFRAMES: Self = Self(0x0c);
+            #[doc = "14 frames"]
+            pub const FOURTEENFRAMES: Self = Self(0x0d);
+            #[doc = "15 frames"]
+            pub const FIFTEENFRAMES: Self = Self(0x0e);
+            #[doc = "16 frames"]
+            pub const SIXTEENFRAMES: Self = Self(0x0f);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Afcntr(pub u8);
+        impl Afcntr {
+            #[doc = "Peripheral takes no control of GPIOs while disabled"]
+            pub const NOTCONTROLLED: Self = Self(0);
+            #[doc = "Peripheral controls GPIOs while disabled"]
+            pub const CONTROLLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Udrcfg(pub u8);
+        impl Udrcfg {
+            #[doc = "Slave sends a constant underrun pattern"]
+            pub const CONSTANT: Self = Self(0);
+            #[doc = "Slave repeats last received data frame from master"]
+            pub const REPEATRECEIVED: Self = Self(0x01);
+            #[doc = "Slave repeats last transmitted data frame"]
+            pub const REPEATTRANSMITTED: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Rcrcini(pub u8);
+        impl Rcrcini {
+            #[doc = "All zeros RX CRC initialization pattern"]
+            pub const ALLZEROS: Self = Self(0);
+            #[doc = "All ones RX CRC initialization pattern"]
+            pub const ALLONES: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Lsbfrst(pub u8);
+        impl Lsbfrst {
+            #[doc = "Data is transmitted/received with the MSB first"]
+            pub const MSBFIRST: Self = Self(0);
+            #[doc = "Data is transmitted/received with the LSB first"]
+            pub const LSBFIRST: Self = Self(0x01);
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "CFGR2"]
+        #[doc = "Underrun Data Register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cfgr2(pub u32);
-        impl Cfgr2 {
-            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
-            pub const fn cll(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
+        pub struct Udrdr(pub u32);
+        impl Udrdr {
+            #[doc = "Data at slave underrun condition"]
+            pub const fn udrdr(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
+            }
+            #[doc = "Data at slave underrun condition"]
+            pub fn set_udrdr(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
+            }
+        }
+        impl Default for Udrdr {
+            fn default() -> Udrdr {
+                Udrdr(0)
+            }
+        }
+        #[doc = "Polynomial Register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Crcpoly(pub u32);
+        impl Crcpoly {
+            #[doc = "CRC polynomial register"]
+            pub const fn crcpoly(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
+            }
+            #[doc = "CRC polynomial register"]
+            pub fn set_crcpoly(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
+            }
+        }
+        impl Default for Crcpoly {
+            fn default() -> Crcpoly {
+                Crcpoly(0)
+            }
+        }
+        #[doc = "Interrupt/Status Flags Clear Register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ifcr(pub u32);
+        impl Ifcr {
+            #[doc = "End Of Transfer flag clear"]
+            pub const fn eotc(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
-            pub fn set_cll(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "End Of Transfer flag clear"]
+            pub fn set_eotc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-            #[doc = "SRAM2 parity lock bit"]
-            pub const fn spl(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
+            #[doc = "Transmission Transfer Filled flag clear"]
+            pub const fn txtfc(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 parity lock bit"]
-            pub fn set_spl(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "Transmission Transfer Filled flag clear"]
+            pub fn set_txtfc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "PVD lock enable bit"]
-            pub const fn pvdl(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
+            #[doc = "Underrun flag clear"]
+            pub const fn udrc(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "PVD lock enable bit"]
-            pub fn set_pvdl(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            #[doc = "Underrun flag clear"]
+            pub fn set_udrc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "ECC Lock"]
-            pub const fn eccl(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
+            #[doc = "Overrun flag clear"]
+            pub const fn ovrc(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "ECC Lock"]
-            pub fn set_eccl(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "Overrun flag clear"]
+            pub fn set_ovrc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "SRAM2 parity error flag"]
-            pub const fn spf(&self) -> bool {
+            #[doc = "CRC Error flag clear"]
+            pub const fn crcec(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "CRC Error flag clear"]
+            pub fn set_crcec(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "TI frame format error flag clear"]
+            pub const fn tifrec(&self) -> bool {
                 let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 parity error flag"]
-            pub fn set_spf(&mut self, val: bool) {
+            #[doc = "TI frame format error flag clear"]
+            pub fn set_tifrec(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
+            #[doc = "Mode Fault flag clear"]
+            pub const fn modfc(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Mode Fault flag clear"]
+            pub fn set_modfc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            }
+            #[doc = "TSERFC flag clear"]
+            pub const fn tserfc(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
+                val != 0
+            }
+            #[doc = "TSERFC flag clear"]
+            pub fn set_tserfc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+            }
+            #[doc = "SUSPend flag clear"]
+            pub const fn suspc(&self) -> bool {
+                let val = (self.0 >> 11usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SUSPend flag clear"]
+            pub fn set_suspc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+            }
         }
-        impl Default for Cfgr2 {
-            fn default() -> Cfgr2 {
-                Cfgr2(0)
+        impl Default for Ifcr {
+            fn default() -> Ifcr {
+                Ifcr(0)
             }
         }
-        #[doc = "external interrupt configuration register 4"]
+        #[doc = "control register 2"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Exticr(pub u32);
-        impl Exticr {
-            #[doc = "EXTI12 configuration bits"]
-            pub fn exti(&self, n: usize) -> u8 {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x0f;
-                val as u8
+        pub struct Cr2(pub u32);
+        impl Cr2 {
+            #[doc = "Number of data at current transfer"]
+            pub const fn tsize(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
             }
-            #[doc = "EXTI12 configuration bits"]
-            pub fn set_exti(&mut self, n: usize, val: u8) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
+            #[doc = "Number of data at current transfer"]
+            pub fn set_tsize(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+            #[doc = "Number of data transfer extension to be reload into TSIZE just when a previous"]
+            pub const fn tser(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Number of data transfer extension to be reload into TSIZE just when a previous"]
+            pub fn set_tser(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
             }
         }
-        impl Default for Exticr {
-            fn default() -> Exticr {
-                Exticr(0)
+        impl Default for Cr2 {
+            fn default() -> Cr2 {
+                Cr2(0)
             }
         }
-        #[doc = "SWPR"]
+        #[doc = "Transmitter CRC Register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Swpr(pub u32);
-        impl Swpr {
-            #[doc = "SRAWM2 write protection."]
-            pub fn pwp(&self, n: usize) -> bool {
-                assert!(n < 32usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
+        pub struct Txcrc(pub u32);
+        impl Txcrc {
+            #[doc = "CRC register for transmitter"]
+            pub const fn txcrc(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "SRAWM2 write protection."]
-            pub fn set_pwp(&mut self, n: usize, val: bool) {
-                assert!(n < 32usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "CRC register for transmitter"]
+            pub fn set_txcrc(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Swpr {
-            fn default() -> Swpr {
-                Swpr(0)
+        impl Default for Txcrc {
+            fn default() -> Txcrc {
+                Txcrc(0)
             }
         }
-        #[doc = "SKR"]
+        #[doc = "Transmit Data Register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Skr(pub u32);
-        impl Skr {
-            #[doc = "SRAM2 write protection key for software erase"]
-            pub const fn key(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
+        pub struct Txdr(pub u32);
+        impl Txdr {
+            #[doc = "Transmit data register"]
+            pub const fn txdr(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "SRAM2 write protection key for software erase"]
-            pub fn set_key(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            #[doc = "Transmit data register"]
+            pub fn set_txdr(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for Skr {
-            fn default() -> Skr {
-                Skr(0)
+        impl Default for Txdr {
+            fn default() -> Txdr {
+                Txdr(0)
             }
         }
-        #[doc = "memory remap register"]
+        #[doc = "Status Register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Memrmp(pub u32);
-        impl Memrmp {
-            #[doc = "Memory mapping selection"]
-            pub const fn mem_mode(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x07;
-                val as u8
+        pub struct Sr(pub u32);
+        impl Sr {
+            #[doc = "Rx-Packet available"]
+            pub const fn rxp(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Memory mapping selection"]
-            pub fn set_mem_mode(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+            #[doc = "Rx-Packet available"]
+            pub fn set_rxp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "QUADSPI memory mapping swap"]
-            pub const fn qfs(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
+            #[doc = "Tx-Packet space available"]
+            pub const fn txp(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "QUADSPI memory mapping swap"]
-            pub fn set_qfs(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "Tx-Packet space available"]
+            pub fn set_txp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Flash Bank mode selection"]
-            pub const fn fb_mode(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+            #[doc = "Duplex Packet"]
+            pub const fn dxp(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Flash Bank mode selection"]
-            pub fn set_fb_mode(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Duplex Packet"]
+            pub fn set_dxp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-        }
-        impl Default for Memrmp {
-            fn default() -> Memrmp {
-                Memrmp(0)
+            #[doc = "End Of Transfer"]
+            pub const fn eot(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
             }
-        }
-        #[doc = "configuration register 1"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cfgr1(pub u32);
-        impl Cfgr1 {
-            #[doc = "Firewall disable"]
-            pub const fn fwdis(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
+            #[doc = "End Of Transfer"]
+            pub fn set_eot(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Transmission Transfer Filled"]
+            pub const fn txtf(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
                 val != 0
             }
-            #[doc = "Firewall disable"]
-            pub fn set_fwdis(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Transmission Transfer Filled"]
+            pub fn set_txtf(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "I/O analog switch voltage booster enable"]
-            pub const fn boosten(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+            #[doc = "Underrun at slave transmission mode"]
+            pub const fn udr(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "I/O analog switch voltage booster enable"]
-            pub fn set_boosten(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Underrun at slave transmission mode"]
+            pub fn set_udr(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
-            pub const fn i2c_pb6_fmp(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
+            #[doc = "Overrun"]
+            pub const fn ovr(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
-            pub fn set_i2c_pb6_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "Overrun"]
+            pub fn set_ovr(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
-            pub const fn i2c_pb7_fmp(&self) -> bool {
-                let val = (self.0 >> 17usize) & 0x01;
+            #[doc = "CRC Error"]
+            pub const fn crce(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
-            pub fn set_i2c_pb7_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+            #[doc = "CRC Error"]
+            pub fn set_crce(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
-            pub const fn i2c_pb8_fmp(&self) -> bool {
-                let val = (self.0 >> 18usize) & 0x01;
+            #[doc = "TI frame format error"]
+            pub const fn tifre(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
-            pub fn set_i2c_pb8_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+            #[doc = "TI frame format error"]
+            pub fn set_tifre(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
-            pub const fn i2c_pb9_fmp(&self) -> bool {
-                let val = (self.0 >> 19usize) & 0x01;
+            #[doc = "Mode Fault"]
+            pub const fn modf(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
                 val != 0
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
-            pub fn set_i2c_pb9_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+            #[doc = "Mode Fault"]
+            pub fn set_modf(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
             }
-            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
-            pub const fn i2c1_fmp(&self) -> bool {
-                let val = (self.0 >> 20usize) & 0x01;
+            #[doc = "Additional number of SPI data to be transacted was reload"]
+            pub const fn tserf(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
                 val != 0
             }
-            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
-            pub fn set_i2c1_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+            #[doc = "Additional number of SPI data to be transacted was reload"]
+            pub fn set_tserf(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
             }
-            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
-            pub const fn i2c2_fmp(&self) -> bool {
-                let val = (self.0 >> 21usize) & 0x01;
+            #[doc = "SUSPend"]
+            pub const fn susp(&self) -> bool {
+                let val = (self.0 >> 11usize) & 0x01;
                 val != 0
             }
-            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
-            pub fn set_i2c2_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+            #[doc = "SUSPend"]
+            pub fn set_susp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
             }
-            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
-            pub const fn i2c3_fmp(&self) -> bool {
-                let val = (self.0 >> 22usize) & 0x01;
+            #[doc = "TxFIFO transmission complete"]
+            pub const fn txc(&self) -> bool {
+                let val = (self.0 >> 12usize) & 0x01;
                 val != 0
             }
-            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
-            pub fn set_i2c3_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+            #[doc = "TxFIFO transmission complete"]
+            pub fn set_txc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
             }
-            #[doc = "Floating Point Unit interrupts enable bits"]
-            pub const fn fpu_ie(&self) -> u8 {
-                let val = (self.0 >> 26usize) & 0x3f;
-                val as u8
+            #[doc = "RxFIFO Packing LeVeL"]
+            pub const fn rxplvl(&self) -> super::vals::Rxplvl {
+                let val = (self.0 >> 13usize) & 0x03;
+                super::vals::Rxplvl(val as u8)
             }
-            #[doc = "Floating Point Unit interrupts enable bits"]
-            pub fn set_fpu_ie(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize);
+            #[doc = "RxFIFO Packing LeVeL"]
+            pub fn set_rxplvl(&mut self, val: super::vals::Rxplvl) {
+                self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
+            }
+            #[doc = "RxFIFO Word Not Empty"]
+            pub const fn rxwne(&self) -> super::vals::Rxwne {
+                let val = (self.0 >> 15usize) & 0x01;
+                super::vals::Rxwne(val as u8)
+            }
+            #[doc = "RxFIFO Word Not Empty"]
+            pub fn set_rxwne(&mut self, val: super::vals::Rxwne) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            }
+            #[doc = "Number of data frames remaining in current TSIZE session"]
+            pub const fn ctsize(&self) -> u16 {
+                let val = (self.0 >> 16usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Number of data frames remaining in current TSIZE session"]
+            pub fn set_ctsize(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
             }
         }
-        impl Default for Cfgr1 {
-            fn default() -> Cfgr1 {
-                Cfgr1(0)
+        impl Default for Sr {
+            fn default() -> Sr {
+                Sr(0)
             }
         }
-        #[doc = "SCSR"]
+        #[doc = "control register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Scsr(pub u32);
-        impl Scsr {
-            #[doc = "SRAM2 Erase"]
-            pub const fn sram2er(&self) -> bool {
+        pub struct Cr1(pub u32);
+        impl Cr1 {
+            #[doc = "Serial Peripheral Enable"]
+            pub const fn spe(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 Erase"]
-            pub fn set_sram2er(&mut self, val: bool) {
+            #[doc = "Serial Peripheral Enable"]
+            pub fn set_spe(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "SRAM2 busy by erase operation"]
-            pub const fn sram2bsy(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
+            #[doc = "Master automatic SUSP in Receive mode"]
+            pub const fn masrx(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 busy by erase operation"]
-            pub fn set_sram2bsy(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "Master automatic SUSP in Receive mode"]
+            pub fn set_masrx(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-        }
-        impl Default for Scsr {
-            fn default() -> Scsr {
-                Scsr(0)
+            #[doc = "Master transfer start"]
+            pub const fn cstart(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Master transfer start"]
+            pub fn set_cstart(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            }
+            #[doc = "Master SUSPend request"]
+            pub const fn csusp(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Master SUSPend request"]
+            pub fn set_csusp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+            }
+            #[doc = "Rx/Tx direction at Half-duplex mode"]
+            pub const fn hddir(&self) -> super::vals::Hddir {
+                let val = (self.0 >> 11usize) & 0x01;
+                super::vals::Hddir(val as u8)
+            }
+            #[doc = "Rx/Tx direction at Half-duplex mode"]
+            pub fn set_hddir(&mut self, val: super::vals::Hddir) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
+            }
+            #[doc = "Internal SS signal input level"]
+            pub const fn ssi(&self) -> bool {
+                let val = (self.0 >> 12usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Internal SS signal input level"]
+            pub fn set_ssi(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+            }
+            #[doc = "32-bit CRC polynomial configuration"]
+            pub const fn crc33_17(&self) -> super::vals::Crc {
+                let val = (self.0 >> 13usize) & 0x01;
+                super::vals::Crc(val as u8)
+            }
+            #[doc = "32-bit CRC polynomial configuration"]
+            pub fn set_crc33_17(&mut self, val: super::vals::Crc) {
+                self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize);
+            }
+            #[doc = "CRC calculation initialization pattern control for receiver"]
+            pub const fn rcrcini(&self) -> super::vals::Rcrcini {
+                let val = (self.0 >> 14usize) & 0x01;
+                super::vals::Rcrcini(val as u8)
+            }
+            #[doc = "CRC calculation initialization pattern control for receiver"]
+            pub fn set_rcrcini(&mut self, val: super::vals::Rcrcini) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
+            }
+            #[doc = "CRC calculation initialization pattern control for transmitter"]
+            pub const fn tcrcini(&self) -> super::vals::Tcrcini {
+                let val = (self.0 >> 15usize) & 0x01;
+                super::vals::Tcrcini(val as u8)
+            }
+            #[doc = "CRC calculation initialization pattern control for transmitter"]
+            pub fn set_tcrcini(&mut self, val: super::vals::Tcrcini) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            }
+            #[doc = "Locking the AF configuration of associated IOs"]
+            pub const fn iolock(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Locking the AF configuration of associated IOs"]
+            pub fn set_iolock(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
             }
         }
-    }
-}
-pub mod rng_v1 {
-    use crate::generic::*;
-    #[doc = "Random number generator"]
-    #[derive(Copy, Clone)]
-    pub struct Rng(pub *mut u8);
-    unsafe impl Send for Rng {}
-    unsafe impl Sync for Rng {}
-    impl Rng {
-        #[doc = "control register"]
-        pub fn cr(self) -> Reg<regs::Cr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::Sr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "data register"]
-        pub fn dr(self) -> Reg<u32, R> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        impl Default for Cr1 {
+            fn default() -> Cr1 {
+                Cr1(0)
+            }
         }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "status register"]
+        #[doc = "Interrupt Enable Register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Sr(pub u32);
-        impl Sr {
-            #[doc = "Data ready"]
-            pub const fn drdy(&self) -> bool {
+        pub struct Ier(pub u32);
+        impl Ier {
+            #[doc = "RXP Interrupt Enable"]
+            pub const fn rxpie(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Data ready"]
-            pub fn set_drdy(&mut self, val: bool) {
+            #[doc = "RXP Interrupt Enable"]
+            pub fn set_rxpie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Clock error current status"]
-            pub const fn cecs(&self) -> bool {
+            #[doc = "TXP interrupt enable"]
+            pub const fn txpie(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Clock error current status"]
-            pub fn set_cecs(&mut self, val: bool) {
+            #[doc = "TXP interrupt enable"]
+            pub fn set_txpie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Seed error current status"]
-            pub const fn secs(&self) -> bool {
+            #[doc = "DXP interrupt enabled"]
+            pub const fn dxpie(&self) -> bool {
                 let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Seed error current status"]
-            pub fn set_secs(&mut self, val: bool) {
+            #[doc = "DXP interrupt enabled"]
+            pub fn set_dxpie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Clock error interrupt status"]
-            pub const fn ceis(&self) -> bool {
+            #[doc = "EOT, SUSP and TXC interrupt enable"]
+            pub const fn eotie(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "EOT, SUSP and TXC interrupt enable"]
+            pub fn set_eotie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "TXTFIE interrupt enable"]
+            pub const fn txtfie(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
+                val != 0
+            }
+            #[doc = "TXTFIE interrupt enable"]
+            pub fn set_txtfie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            }
+            #[doc = "UDR interrupt enable"]
+            pub const fn udrie(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Clock error interrupt status"]
-            pub fn set_ceis(&mut self, val: bool) {
+            #[doc = "UDR interrupt enable"]
+            pub fn set_udrie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Seed error interrupt status"]
-            pub const fn seis(&self) -> bool {
+            #[doc = "OVR interrupt enable"]
+            pub const fn ovrie(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Seed error interrupt status"]
-            pub fn set_seis(&mut self, val: bool) {
+            #[doc = "OVR interrupt enable"]
+            pub fn set_ovrie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
+            #[doc = "CRC Interrupt enable"]
+            pub const fn crceie(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "CRC Interrupt enable"]
+            pub fn set_crceie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "TIFRE interrupt enable"]
+            pub const fn tifreie(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "TIFRE interrupt enable"]
+            pub fn set_tifreie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Mode Fault interrupt enable"]
+            pub const fn modfie(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Mode Fault interrupt enable"]
+            pub fn set_modfie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+            }
+            #[doc = "Additional number of transactions reload interrupt enable"]
+            pub const fn tserfie(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Additional number of transactions reload interrupt enable"]
+            pub fn set_tserfie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+            }
         }
-        impl Default for Sr {
-            fn default() -> Sr {
-                Sr(0)
+        impl Default for Ier {
+            fn default() -> Ier {
+                Ier(0)
             }
         }
-        #[doc = "control register"]
+        #[doc = "Receive Data Register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr(pub u32);
-        impl Cr {
-            #[doc = "Random number generator enable"]
-            pub const fn rngen(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
+        pub struct Rxdr(pub u32);
+        impl Rxdr {
+            #[doc = "Receive data register"]
+            pub const fn rxdr(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
+            }
+            #[doc = "Receive data register"]
+            pub fn set_rxdr(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
+            }
+        }
+        impl Default for Rxdr {
+            fn default() -> Rxdr {
+                Rxdr(0)
+            }
+        }
+        #[doc = "configuration register 2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cfg2(pub u32);
+        impl Cfg2 {
+            #[doc = "Master SS Idleness"]
+            pub const fn mssi(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "Master SS Idleness"]
+            pub fn set_mssi(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+            }
+            #[doc = "Master Inter-Data Idleness"]
+            pub const fn midi(&self) -> u8 {
+                let val = (self.0 >> 4usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "Master Inter-Data Idleness"]
+            pub fn set_midi(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+            }
+            #[doc = "Swap functionality of MISO and MOSI pins"]
+            pub const fn ioswp(&self) -> bool {
+                let val = (self.0 >> 15usize) & 0x01;
                 val != 0
             }
-            #[doc = "Random number generator enable"]
-            pub fn set_rngen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            #[doc = "Swap functionality of MISO and MOSI pins"]
+            pub fn set_ioswp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
             }
-            #[doc = "Interrupt enable"]
-            pub const fn ie(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
+            #[doc = "SPI Communication Mode"]
+            pub const fn comm(&self) -> super::vals::Comm {
+                let val = (self.0 >> 17usize) & 0x03;
+                super::vals::Comm(val as u8)
+            }
+            #[doc = "SPI Communication Mode"]
+            pub fn set_comm(&mut self, val: super::vals::Comm) {
+                self.0 = (self.0 & !(0x03 << 17usize)) | (((val.0 as u32) & 0x03) << 17usize);
+            }
+            #[doc = "Serial Protocol"]
+            pub const fn sp(&self) -> super::vals::Sp {
+                let val = (self.0 >> 19usize) & 0x07;
+                super::vals::Sp(val as u8)
+            }
+            #[doc = "Serial Protocol"]
+            pub fn set_sp(&mut self, val: super::vals::Sp) {
+                self.0 = (self.0 & !(0x07 << 19usize)) | (((val.0 as u32) & 0x07) << 19usize);
+            }
+            #[doc = "SPI Master"]
+            pub const fn master(&self) -> super::vals::Master {
+                let val = (self.0 >> 22usize) & 0x01;
+                super::vals::Master(val as u8)
+            }
+            #[doc = "SPI Master"]
+            pub fn set_master(&mut self, val: super::vals::Master) {
+                self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
+            }
+            #[doc = "Data frame format"]
+            pub const fn lsbfrst(&self) -> super::vals::Lsbfrst {
+                let val = (self.0 >> 23usize) & 0x01;
+                super::vals::Lsbfrst(val as u8)
+            }
+            #[doc = "Data frame format"]
+            pub fn set_lsbfrst(&mut self, val: super::vals::Lsbfrst) {
+                self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
+            }
+            #[doc = "Clock phase"]
+            pub const fn cpha(&self) -> super::vals::Cpha {
+                let val = (self.0 >> 24usize) & 0x01;
+                super::vals::Cpha(val as u8)
+            }
+            #[doc = "Clock phase"]
+            pub fn set_cpha(&mut self, val: super::vals::Cpha) {
+                self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
+            }
+            #[doc = "Clock polarity"]
+            pub const fn cpol(&self) -> super::vals::Cpol {
+                let val = (self.0 >> 25usize) & 0x01;
+                super::vals::Cpol(val as u8)
+            }
+            #[doc = "Clock polarity"]
+            pub fn set_cpol(&mut self, val: super::vals::Cpol) {
+                self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
+            }
+            #[doc = "Software management of SS signal input"]
+            pub const fn ssm(&self) -> bool {
+                let val = (self.0 >> 26usize) & 0x01;
                 val != 0
             }
-            #[doc = "Interrupt enable"]
-            pub fn set_ie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "Software management of SS signal input"]
+            pub fn set_ssm(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+            }
+            #[doc = "SS input/output polarity"]
+            pub const fn ssiop(&self) -> super::vals::Ssiop {
+                let val = (self.0 >> 28usize) & 0x01;
+                super::vals::Ssiop(val as u8)
+            }
+            #[doc = "SS input/output polarity"]
+            pub fn set_ssiop(&mut self, val: super::vals::Ssiop) {
+                self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
+            }
+            #[doc = "SS output enable"]
+            pub const fn ssoe(&self) -> bool {
+                let val = (self.0 >> 29usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SS output enable"]
+            pub fn set_ssoe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+            }
+            #[doc = "SS output management in master mode"]
+            pub const fn ssom(&self) -> super::vals::Ssom {
+                let val = (self.0 >> 30usize) & 0x01;
+                super::vals::Ssom(val as u8)
+            }
+            #[doc = "SS output management in master mode"]
+            pub fn set_ssom(&mut self, val: super::vals::Ssom) {
+                self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
+            }
+            #[doc = "Alternate function GPIOs control"]
+            pub const fn afcntr(&self) -> super::vals::Afcntr {
+                let val = (self.0 >> 31usize) & 0x01;
+                super::vals::Afcntr(val as u8)
+            }
+            #[doc = "Alternate function GPIOs control"]
+            pub fn set_afcntr(&mut self, val: super::vals::Afcntr) {
+                self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
             }
         }
-        impl Default for Cr {
-            fn default() -> Cr {
-                Cr(0)
+        impl Default for Cfg2 {
+            fn default() -> Cfg2 {
+                Cfg2(0)
+            }
+        }
+        #[doc = "Receiver CRC Register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Rxcrc(pub u32);
+        impl Rxcrc {
+            #[doc = "CRC register for receiver"]
+            pub const fn rxcrc(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
+            }
+            #[doc = "CRC register for receiver"]
+            pub fn set_rxcrc(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
+            }
+        }
+        impl Default for Rxcrc {
+            fn default() -> Rxcrc {
+                Rxcrc(0)
+            }
+        }
+        #[doc = "configuration register 1"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cfg1(pub u32);
+        impl Cfg1 {
+            #[doc = "Number of bits in at single SPI data frame"]
+            pub const fn dsize(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x1f;
+                val as u8
+            }
+            #[doc = "Number of bits in at single SPI data frame"]
+            pub fn set_dsize(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+            }
+            #[doc = "threshold level"]
+            pub const fn fthlv(&self) -> super::vals::Fthlv {
+                let val = (self.0 >> 5usize) & 0x0f;
+                super::vals::Fthlv(val as u8)
+            }
+            #[doc = "threshold level"]
+            pub fn set_fthlv(&mut self, val: super::vals::Fthlv) {
+                self.0 = (self.0 & !(0x0f << 5usize)) | (((val.0 as u32) & 0x0f) << 5usize);
+            }
+            #[doc = "Behavior of slave transmitter at underrun condition"]
+            pub const fn udrcfg(&self) -> super::vals::Udrcfg {
+                let val = (self.0 >> 9usize) & 0x03;
+                super::vals::Udrcfg(val as u8)
+            }
+            #[doc = "Behavior of slave transmitter at underrun condition"]
+            pub fn set_udrcfg(&mut self, val: super::vals::Udrcfg) {
+                self.0 = (self.0 & !(0x03 << 9usize)) | (((val.0 as u32) & 0x03) << 9usize);
+            }
+            #[doc = "Detection of underrun condition at slave transmitter"]
+            pub const fn udrdet(&self) -> super::vals::Udrdet {
+                let val = (self.0 >> 11usize) & 0x03;
+                super::vals::Udrdet(val as u8)
+            }
+            #[doc = "Detection of underrun condition at slave transmitter"]
+            pub fn set_udrdet(&mut self, val: super::vals::Udrdet) {
+                self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
+            }
+            #[doc = "Rx DMA stream enable"]
+            pub const fn rxdmaen(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Rx DMA stream enable"]
+            pub fn set_rxdmaen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            }
+            #[doc = "Tx DMA stream enable"]
+            pub const fn txdmaen(&self) -> bool {
+                let val = (self.0 >> 15usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Tx DMA stream enable"]
+            pub fn set_txdmaen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+            }
+            #[doc = "Length of CRC frame to be transacted and compared"]
+            pub const fn crcsize(&self) -> u8 {
+                let val = (self.0 >> 16usize) & 0x1f;
+                val as u8
+            }
+            #[doc = "Length of CRC frame to be transacted and compared"]
+            pub fn set_crcsize(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
+            }
+            #[doc = "Hardware CRC computation enable"]
+            pub const fn crcen(&self) -> bool {
+                let val = (self.0 >> 22usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Hardware CRC computation enable"]
+            pub fn set_crcen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+            }
+            #[doc = "Master baud rate"]
+            pub const fn mbr(&self) -> super::vals::Mbr {
+                let val = (self.0 >> 28usize) & 0x07;
+                super::vals::Mbr(val as u8)
+            }
+            #[doc = "Master baud rate"]
+            pub fn set_mbr(&mut self, val: super::vals::Mbr) {
+                self.0 = (self.0 & !(0x07 << 28usize)) | (((val.0 as u32) & 0x07) << 28usize);
+            }
+        }
+        impl Default for Cfg1 {
+            fn default() -> Cfg1 {
+                Cfg1(0)
             }
         }
     }
 }
-pub mod spi_v2 {
+pub mod exti_v1 {
     use crate::generic::*;
-    #[doc = "Serial peripheral interface"]
+    #[doc = "External interrupt/event controller"]
     #[derive(Copy, Clone)]
-    pub struct Spi(pub *mut u8);
-    unsafe impl Send for Spi {}
-    unsafe impl Sync for Spi {}
-    impl Spi {
-        #[doc = "control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
+    pub struct Exti(pub *mut u8);
+    unsafe impl Send for Exti {}
+    unsafe impl Sync for Exti {}
+    impl Exti {
+        #[doc = "Interrupt mask register (EXTI_IMR)"]
+        pub fn imr(self) -> Reg<regs::Imr, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        #[doc = "control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
+        #[doc = "Event mask register (EXTI_EMR)"]
+        pub fn emr(self) -> Reg<regs::Emr, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::Sr, RW> {
+        #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
+        pub fn rtsr(self) -> Reg<regs::Rtsr, RW> {
             unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
-        #[doc = "data register"]
-        pub fn dr(self) -> Reg<regs::Dr, RW> {
+        #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
+        pub fn ftsr(self) -> Reg<regs::Ftsr, RW> {
             unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
-        #[doc = "CRC polynomial register"]
-        pub fn crcpr(self) -> Reg<regs::Crcpr, RW> {
+        #[doc = "Software interrupt event register (EXTI_SWIER)"]
+        pub fn swier(self) -> Reg<regs::Swier, RW> {
             unsafe { Reg::from_ptr(self.0.add(16usize)) }
         }
-        #[doc = "RX CRC register"]
-        pub fn rxcrcr(self) -> Reg<regs::Rxcrcr, R> {
+        #[doc = "Pending register (EXTI_PR)"]
+        pub fn pr(self) -> Reg<regs::Pr, RW> {
             unsafe { Reg::from_ptr(self.0.add(20usize)) }
         }
-        #[doc = "TX CRC register"]
-        pub fn txcrcr(self) -> Reg<regs::Txcrcr, R> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
-        }
     }
-    pub mod vals {
+    pub mod regs {
         use crate::generic::*;
+        #[doc = "Pending register (EXTI_PR)"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ftlvlr(pub u8);
-        impl Ftlvlr {
-            #[doc = "Tx FIFO Empty"]
-            pub const EMPTY: Self = Self(0);
-            #[doc = "Tx 1/4 FIFO"]
-            pub const QUARTER: Self = Self(0x01);
-            #[doc = "Tx 1/2 FIFO"]
-            pub const HALF: Self = Self(0x02);
-            #[doc = "Tx FIFO full"]
-            pub const FULL: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Crcnext(pub u8);
-        impl Crcnext {
-            #[doc = "Next transmit value is from Tx buffer"]
-            pub const TXBUFFER: Self = Self(0);
-            #[doc = "Next transmit value is from Tx CRC register"]
-            pub const CRC: Self = Self(0x01);
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Pr(pub u32);
+        impl Pr {
+            #[doc = "Pending bit 0"]
+            pub fn pr(&self, n: usize) -> bool {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Pending bit 0"]
+            pub fn set_pr(&mut self, n: usize, val: bool) {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Rxonly(pub u8);
-        impl Rxonly {
-            #[doc = "Full duplex (Transmit and receive)"]
-            pub const FULLDUPLEX: Self = Self(0);
-            #[doc = "Output disabled (Receive-only mode)"]
-            pub const OUTPUTDISABLED: Self = Self(0x01);
+        impl Default for Pr {
+            fn default() -> Pr {
+                Pr(0)
+            }
         }
+        #[doc = "Interrupt mask register (EXTI_IMR)"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cpol(pub u8);
-        impl Cpol {
-            #[doc = "CK to 0 when idle"]
-            pub const IDLELOW: Self = Self(0);
-            #[doc = "CK to 1 when idle"]
-            pub const IDLEHIGH: Self = Self(0x01);
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Imr(pub u32);
+        impl Imr {
+            #[doc = "Interrupt Mask on line 0"]
+            pub fn mr(&self, n: usize) -> super::vals::Mr {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Mr(val as u8)
+            }
+            #[doc = "Interrupt Mask on line 0"]
+            pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Frlvlr(pub u8);
-        impl Frlvlr {
-            #[doc = "Rx FIFO Empty"]
-            pub const EMPTY: Self = Self(0);
-            #[doc = "Rx 1/4 FIFO"]
-            pub const QUARTER: Self = Self(0x01);
-            #[doc = "Rx 1/2 FIFO"]
-            pub const HALF: Self = Self(0x02);
-            #[doc = "Rx FIFO full"]
-            pub const FULL: Self = Self(0x03);
+        impl Default for Imr {
+            fn default() -> Imr {
+                Imr(0)
+            }
         }
+        #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ds(pub u8);
-        impl Ds {
-            #[doc = "4-bit"]
-            pub const FOURBIT: Self = Self(0x03);
-            #[doc = "5-bit"]
-            pub const FIVEBIT: Self = Self(0x04);
-            #[doc = "6-bit"]
-            pub const SIXBIT: Self = Self(0x05);
-            #[doc = "7-bit"]
-            pub const SEVENBIT: Self = Self(0x06);
-            #[doc = "8-bit"]
-            pub const EIGHTBIT: Self = Self(0x07);
-            #[doc = "9-bit"]
-            pub const NINEBIT: Self = Self(0x08);
-            #[doc = "10-bit"]
-            pub const TENBIT: Self = Self(0x09);
-            #[doc = "11-bit"]
-            pub const ELEVENBIT: Self = Self(0x0a);
-            #[doc = "12-bit"]
-            pub const TWELVEBIT: Self = Self(0x0b);
-            #[doc = "13-bit"]
-            pub const THIRTEENBIT: Self = Self(0x0c);
-            #[doc = "14-bit"]
-            pub const FOURTEENBIT: Self = Self(0x0d);
-            #[doc = "15-bit"]
-            pub const FIFTEENBIT: Self = Self(0x0e);
-            #[doc = "16-bit"]
-            pub const SIXTEENBIT: Self = Self(0x0f);
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Rtsr(pub u32);
+        impl Rtsr {
+            #[doc = "Rising trigger event configuration of line 0"]
+            pub fn tr(&self, n: usize) -> super::vals::Tr {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Tr(val as u8)
+            }
+            #[doc = "Rising trigger event configuration of line 0"]
+            pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct LdmaRx(pub u8);
-        impl LdmaRx {
-            #[doc = "Number of data to transfer for receive is even"]
-            pub const EVEN: Self = Self(0);
-            #[doc = "Number of data to transfer for receive is odd"]
-            pub const ODD: Self = Self(0x01);
+        impl Default for Rtsr {
+            fn default() -> Rtsr {
+                Rtsr(0)
+            }
         }
+        #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mstr(pub u8);
-        impl Mstr {
-            #[doc = "Slave configuration"]
-            pub const SLAVE: Self = Self(0);
-            #[doc = "Master configuration"]
-            pub const MASTER: Self = Self(0x01);
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ftsr(pub u32);
+        impl Ftsr {
+            #[doc = "Falling trigger event configuration of line 0"]
+            pub fn tr(&self, n: usize) -> super::vals::Tr {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Tr(val as u8)
+            }
+            #[doc = "Falling trigger event configuration of line 0"]
+            pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Crcl(pub u8);
-        impl Crcl {
-            #[doc = "8-bit CRC length"]
-            pub const EIGHTBIT: Self = Self(0);
-            #[doc = "16-bit CRC length"]
-            pub const SIXTEENBIT: Self = Self(0x01);
+        impl Default for Ftsr {
+            fn default() -> Ftsr {
+                Ftsr(0)
+            }
         }
+        #[doc = "Software interrupt event register (EXTI_SWIER)"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Bidioe(pub u8);
-        impl Bidioe {
-            #[doc = "Output disabled (receive-only mode)"]
-            pub const OUTPUTDISABLED: Self = Self(0);
-            #[doc = "Output enabled (transmit-only mode)"]
-            pub const OUTPUTENABLED: Self = Self(0x01);
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Swier(pub u32);
+        impl Swier {
+            #[doc = "Software Interrupt on line 0"]
+            pub fn swier(&self, n: usize) -> bool {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Software Interrupt on line 0"]
+            pub fn set_swier(&mut self, n: usize, val: bool) {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Frer(pub u8);
-        impl Frer {
-            #[doc = "No frame format error"]
-            pub const NOERROR: Self = Self(0);
-            #[doc = "A frame format error occurred"]
-            pub const ERROR: Self = Self(0x01);
+        impl Default for Swier {
+            fn default() -> Swier {
+                Swier(0)
+            }
         }
+        #[doc = "Event mask register (EXTI_EMR)"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Bidimode(pub u8);
-        impl Bidimode {
-            #[doc = "2-line unidirectional data mode selected"]
-            pub const UNIDIRECTIONAL: Self = Self(0);
-            #[doc = "1-line bidirectional data mode selected"]
-            pub const BIDIRECTIONAL: Self = Self(0x01);
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Emr(pub u32);
+        impl Emr {
+            #[doc = "Event Mask on line 0"]
+            pub fn mr(&self, n: usize) -> super::vals::Mr {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Mr(val as u8)
+            }
+            #[doc = "Event Mask on line 0"]
+            pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Br(pub u8);
-        impl Br {
-            #[doc = "f_PCLK / 2"]
-            pub const DIV2: Self = Self(0);
-            #[doc = "f_PCLK / 4"]
-            pub const DIV4: Self = Self(0x01);
-            #[doc = "f_PCLK / 8"]
-            pub const DIV8: Self = Self(0x02);
-            #[doc = "f_PCLK / 16"]
-            pub const DIV16: Self = Self(0x03);
-            #[doc = "f_PCLK / 32"]
-            pub const DIV32: Self = Self(0x04);
-            #[doc = "f_PCLK / 64"]
-            pub const DIV64: Self = Self(0x05);
-            #[doc = "f_PCLK / 128"]
-            pub const DIV128: Self = Self(0x06);
-            #[doc = "f_PCLK / 256"]
-            pub const DIV256: Self = Self(0x07);
+        impl Default for Emr {
+            fn default() -> Emr {
+                Emr(0)
+            }
         }
+    }
+    pub mod vals {
+        use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cpha(pub u8);
-        impl Cpha {
-            #[doc = "The first clock transition is the first data capture edge"]
-            pub const FIRSTEDGE: Self = Self(0);
-            #[doc = "The second clock transition is the first data capture edge"]
-            pub const SECONDEDGE: Self = Self(0x01);
+        pub struct Prw(pub u8);
+        impl Prw {
+            #[doc = "Clears pending bit"]
+            pub const CLEAR: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Frxth(pub u8);
-        impl Frxth {
-            #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"]
-            pub const HALF: Self = Self(0);
-            #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"]
-            pub const QUARTER: Self = Self(0x01);
+        pub struct Mr(pub u8);
+        impl Mr {
+            #[doc = "Interrupt request line is masked"]
+            pub const MASKED: Self = Self(0);
+            #[doc = "Interrupt request line is unmasked"]
+            pub const UNMASKED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Frf(pub u8);
-        impl Frf {
-            #[doc = "SPI Motorola mode"]
-            pub const MOTOROLA: Self = Self(0);
-            #[doc = "SPI TI mode"]
-            pub const TI: Self = Self(0x01);
+        pub struct Tr(pub u8);
+        impl Tr {
+            #[doc = "Falling edge trigger is disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Falling edge trigger is enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct LdmaTx(pub u8);
-        impl LdmaTx {
-            #[doc = "Number of data to transfer for transmit is even"]
-            pub const EVEN: Self = Self(0);
-            #[doc = "Number of data to transfer for transmit is odd"]
-            pub const ODD: Self = Self(0x01);
+        pub struct Swierw(pub u8);
+        impl Swierw {
+            #[doc = "Generates an interrupt request"]
+            pub const PEND: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lsbfirst(pub u8);
-        impl Lsbfirst {
-            #[doc = "Data is transmitted/received with the MSB first"]
-            pub const MSBFIRST: Self = Self(0);
-            #[doc = "Data is transmitted/received with the LSB first"]
-            pub const LSBFIRST: Self = Self(0x01);
+        pub struct Prr(pub u8);
+        impl Prr {
+            #[doc = "No trigger request occurred"]
+            pub const NOTPENDING: Self = Self(0);
+            #[doc = "Selected trigger request occurred"]
+            pub const PENDING: Self = Self(0x01);
         }
     }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "TX CRC register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Txcrcr(pub u32);
-        impl Txcrcr {
-            #[doc = "Tx CRC register"]
-            pub const fn tx_crc(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "Tx CRC register"]
-            pub fn set_tx_crc(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
+}
+pub mod spi_v2 {
+    use crate::generic::*;
+    #[doc = "Serial peripheral interface"]
+    #[derive(Copy, Clone)]
+    pub struct Spi(pub *mut u8);
+    unsafe impl Send for Spi {}
+    unsafe impl Sync for Spi {}
+    impl Spi {
+        #[doc = "control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        impl Default for Txcrcr {
-            fn default() -> Txcrcr {
-                Txcrcr(0)
-            }
+        #[doc = "control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::Sr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "data register"]
+        pub fn dr(self) -> Reg<regs::Dr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "CRC polynomial register"]
+        pub fn crcpr(self) -> Reg<regs::Crcpr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
         }
         #[doc = "RX CRC register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Rxcrcr(pub u32);
-        impl Rxcrcr {
-            #[doc = "Rx CRC register"]
-            pub const fn rx_crc(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "Rx CRC register"]
-            pub fn set_rx_crc(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
+        pub fn rxcrcr(self) -> Reg<regs::Rxcrcr, R> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
         }
-        impl Default for Rxcrcr {
-            fn default() -> Rxcrcr {
-                Rxcrcr(0)
-            }
+        #[doc = "TX CRC register"]
+        pub fn txcrcr(self) -> Reg<regs::Txcrcr, R> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
         }
+    }
+    pub mod regs {
+        use crate::generic::*;
         #[doc = "status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -9447,24 +8887,64 @@ pub mod spi_v2 {
                 Sr(0)
             }
         }
-        #[doc = "data register"]
+        #[doc = "TX CRC register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dr(pub u32);
-        impl Dr {
-            #[doc = "Data register"]
-            pub const fn dr(&self) -> u16 {
+        pub struct Txcrcr(pub u32);
+        impl Txcrcr {
+            #[doc = "Tx CRC register"]
+            pub const fn tx_crc(&self) -> u16 {
                 let val = (self.0 >> 0usize) & 0xffff;
                 val as u16
             }
-            #[doc = "Data register"]
-            pub fn set_dr(&mut self, val: u16) {
+            #[doc = "Tx CRC register"]
+            pub fn set_tx_crc(&mut self, val: u16) {
                 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Dr {
-            fn default() -> Dr {
-                Dr(0)
+        impl Default for Txcrcr {
+            fn default() -> Txcrcr {
+                Txcrcr(0)
+            }
+        }
+        #[doc = "RX CRC register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Rxcrcr(pub u32);
+        impl Rxcrcr {
+            #[doc = "Rx CRC register"]
+            pub const fn rx_crc(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Rx CRC register"]
+            pub fn set_rx_crc(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Rxcrcr {
+            fn default() -> Rxcrcr {
+                Rxcrcr(0)
+            }
+        }
+        #[doc = "CRC polynomial register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Crcpr(pub u32);
+        impl Crcpr {
+            #[doc = "CRC polynomial register"]
+            pub const fn crcpoly(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "CRC polynomial register"]
+            pub fn set_crcpoly(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Crcpr {
+            fn default() -> Crcpr {
+                Crcpr(0)
             }
         }
         #[doc = "control register 2"]
@@ -9723,552 +9203,2225 @@ pub mod spi_v2 {
                 Cr1(0)
             }
         }
-        #[doc = "CRC polynomial register"]
+        #[doc = "data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Crcpr(pub u32);
-        impl Crcpr {
-            #[doc = "CRC polynomial register"]
-            pub const fn crcpoly(&self) -> u16 {
+        pub struct Dr(pub u32);
+        impl Dr {
+            #[doc = "Data register"]
+            pub const fn dr(&self) -> u16 {
                 let val = (self.0 >> 0usize) & 0xffff;
                 val as u16
             }
-            #[doc = "CRC polynomial register"]
-            pub fn set_crcpoly(&mut self, val: u16) {
+            #[doc = "Data register"]
+            pub fn set_dr(&mut self, val: u16) {
                 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Crcpr {
-            fn default() -> Crcpr {
-                Crcpr(0)
+        impl Default for Dr {
+            fn default() -> Dr {
+                Dr(0)
             }
         }
     }
+    pub mod vals {
+        use crate::generic::*;
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Lsbfirst(pub u8);
+        impl Lsbfirst {
+            #[doc = "Data is transmitted/received with the MSB first"]
+            pub const MSBFIRST: Self = Self(0);
+            #[doc = "Data is transmitted/received with the LSB first"]
+            pub const LSBFIRST: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Frer(pub u8);
+        impl Frer {
+            #[doc = "No frame format error"]
+            pub const NOERROR: Self = Self(0);
+            #[doc = "A frame format error occurred"]
+            pub const ERROR: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct LdmaTx(pub u8);
+        impl LdmaTx {
+            #[doc = "Number of data to transfer for transmit is even"]
+            pub const EVEN: Self = Self(0);
+            #[doc = "Number of data to transfer for transmit is odd"]
+            pub const ODD: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Bidioe(pub u8);
+        impl Bidioe {
+            #[doc = "Output disabled (receive-only mode)"]
+            pub const OUTPUTDISABLED: Self = Self(0);
+            #[doc = "Output enabled (transmit-only mode)"]
+            pub const OUTPUTENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Cpol(pub u8);
+        impl Cpol {
+            #[doc = "CK to 0 when idle"]
+            pub const IDLELOW: Self = Self(0);
+            #[doc = "CK to 1 when idle"]
+            pub const IDLEHIGH: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Frf(pub u8);
+        impl Frf {
+            #[doc = "SPI Motorola mode"]
+            pub const MOTOROLA: Self = Self(0);
+            #[doc = "SPI TI mode"]
+            pub const TI: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Crcnext(pub u8);
+        impl Crcnext {
+            #[doc = "Next transmit value is from Tx buffer"]
+            pub const TXBUFFER: Self = Self(0);
+            #[doc = "Next transmit value is from Tx CRC register"]
+            pub const CRC: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ftlvlr(pub u8);
+        impl Ftlvlr {
+            #[doc = "Tx FIFO Empty"]
+            pub const EMPTY: Self = Self(0);
+            #[doc = "Tx 1/4 FIFO"]
+            pub const QUARTER: Self = Self(0x01);
+            #[doc = "Tx 1/2 FIFO"]
+            pub const HALF: Self = Self(0x02);
+            #[doc = "Tx FIFO full"]
+            pub const FULL: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Bidimode(pub u8);
+        impl Bidimode {
+            #[doc = "2-line unidirectional data mode selected"]
+            pub const UNIDIRECTIONAL: Self = Self(0);
+            #[doc = "1-line bidirectional data mode selected"]
+            pub const BIDIRECTIONAL: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Cpha(pub u8);
+        impl Cpha {
+            #[doc = "The first clock transition is the first data capture edge"]
+            pub const FIRSTEDGE: Self = Self(0);
+            #[doc = "The second clock transition is the first data capture edge"]
+            pub const SECONDEDGE: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Crcl(pub u8);
+        impl Crcl {
+            #[doc = "8-bit CRC length"]
+            pub const EIGHTBIT: Self = Self(0);
+            #[doc = "16-bit CRC length"]
+            pub const SIXTEENBIT: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct LdmaRx(pub u8);
+        impl LdmaRx {
+            #[doc = "Number of data to transfer for receive is even"]
+            pub const EVEN: Self = Self(0);
+            #[doc = "Number of data to transfer for receive is odd"]
+            pub const ODD: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Frxth(pub u8);
+        impl Frxth {
+            #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"]
+            pub const HALF: Self = Self(0);
+            #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"]
+            pub const QUARTER: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Mstr(pub u8);
+        impl Mstr {
+            #[doc = "Slave configuration"]
+            pub const SLAVE: Self = Self(0);
+            #[doc = "Master configuration"]
+            pub const MASTER: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ds(pub u8);
+        impl Ds {
+            #[doc = "4-bit"]
+            pub const FOURBIT: Self = Self(0x03);
+            #[doc = "5-bit"]
+            pub const FIVEBIT: Self = Self(0x04);
+            #[doc = "6-bit"]
+            pub const SIXBIT: Self = Self(0x05);
+            #[doc = "7-bit"]
+            pub const SEVENBIT: Self = Self(0x06);
+            #[doc = "8-bit"]
+            pub const EIGHTBIT: Self = Self(0x07);
+            #[doc = "9-bit"]
+            pub const NINEBIT: Self = Self(0x08);
+            #[doc = "10-bit"]
+            pub const TENBIT: Self = Self(0x09);
+            #[doc = "11-bit"]
+            pub const ELEVENBIT: Self = Self(0x0a);
+            #[doc = "12-bit"]
+            pub const TWELVEBIT: Self = Self(0x0b);
+            #[doc = "13-bit"]
+            pub const THIRTEENBIT: Self = Self(0x0c);
+            #[doc = "14-bit"]
+            pub const FOURTEENBIT: Self = Self(0x0d);
+            #[doc = "15-bit"]
+            pub const FIFTEENBIT: Self = Self(0x0e);
+            #[doc = "16-bit"]
+            pub const SIXTEENBIT: Self = Self(0x0f);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Frlvlr(pub u8);
+        impl Frlvlr {
+            #[doc = "Rx FIFO Empty"]
+            pub const EMPTY: Self = Self(0);
+            #[doc = "Rx 1/4 FIFO"]
+            pub const QUARTER: Self = Self(0x01);
+            #[doc = "Rx 1/2 FIFO"]
+            pub const HALF: Self = Self(0x02);
+            #[doc = "Rx FIFO full"]
+            pub const FULL: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Rxonly(pub u8);
+        impl Rxonly {
+            #[doc = "Full duplex (Transmit and receive)"]
+            pub const FULLDUPLEX: Self = Self(0);
+            #[doc = "Output disabled (Receive-only mode)"]
+            pub const OUTPUTDISABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Br(pub u8);
+        impl Br {
+            #[doc = "f_PCLK / 2"]
+            pub const DIV2: Self = Self(0);
+            #[doc = "f_PCLK / 4"]
+            pub const DIV4: Self = Self(0x01);
+            #[doc = "f_PCLK / 8"]
+            pub const DIV8: Self = Self(0x02);
+            #[doc = "f_PCLK / 16"]
+            pub const DIV16: Self = Self(0x03);
+            #[doc = "f_PCLK / 32"]
+            pub const DIV32: Self = Self(0x04);
+            #[doc = "f_PCLK / 64"]
+            pub const DIV64: Self = Self(0x05);
+            #[doc = "f_PCLK / 128"]
+            pub const DIV128: Self = Self(0x06);
+            #[doc = "f_PCLK / 256"]
+            pub const DIV256: Self = Self(0x07);
+        }
+    }
 }
-pub mod dma_v2 {
+pub mod timer_v1 {
     use crate::generic::*;
-    #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
+    #[doc = "General purpose 32-bit timer"]
     #[derive(Copy, Clone)]
-    pub struct St(pub *mut u8);
-    unsafe impl Send for St {}
-    unsafe impl Sync for St {}
-    impl St {
-        #[doc = "stream x configuration register"]
-        pub fn cr(self) -> Reg<regs::Cr, RW> {
+    pub struct TimGp32(pub *mut u8);
+    unsafe impl Send for TimGp32 {}
+    unsafe impl Sync for TimGp32 {}
+    impl TimGp32 {
+        #[doc = "control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        #[doc = "stream x number of data register"]
-        pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
+        #[doc = "control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2Gp, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "stream x peripheral address register"]
-        pub fn par(self) -> Reg<u32, RW> {
+        #[doc = "slave mode control register"]
+        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
             unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
-        #[doc = "stream x memory 0 address register"]
-        pub fn m0ar(self) -> Reg<u32, RW> {
+        #[doc = "DMA/Interrupt enable register"]
+        pub fn dier(self) -> Reg<regs::DierGp, RW> {
             unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
-        #[doc = "stream x memory 1 address register"]
-        pub fn m1ar(self) -> Reg<u32, RW> {
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::SrGp, RW> {
             unsafe { Reg::from_ptr(self.0.add(16usize)) }
         }
-        #[doc = "stream x FIFO control register"]
-        pub fn fcr(self) -> Reg<regs::Fcr, RW> {
+        #[doc = "event generation register"]
+        pub fn egr(self) -> Reg<regs::EgrGp, W> {
             unsafe { Reg::from_ptr(self.0.add(20usize)) }
         }
+        #[doc = "capture/compare mode register 1 (input mode)"]
+        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
+        }
+        #[doc = "capture/compare mode register 1 (output mode)"]
+        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
+        }
+        #[doc = "capture/compare enable register"]
+        pub fn ccer(self) -> Reg<regs::CcerGp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        }
+        #[doc = "counter"]
+        pub fn cnt(self) -> Reg<regs::Cnt32, RW> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        }
+        #[doc = "prescaler"]
+        pub fn psc(self) -> Reg<regs::Psc, RW> {
+            unsafe { Reg::from_ptr(self.0.add(40usize)) }
+        }
+        #[doc = "auto-reload register"]
+        pub fn arr(self) -> Reg<regs::Arr32, RW> {
+            unsafe { Reg::from_ptr(self.0.add(44usize)) }
+        }
+        #[doc = "capture/compare register"]
+        pub fn ccr(self, n: usize) -> Reg<regs::Ccr32, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
+        }
+        #[doc = "DMA control register"]
+        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(72usize)) }
+        }
+        #[doc = "DMA address for full transfer"]
+        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
+            unsafe { Reg::from_ptr(self.0.add(76usize)) }
+        }
     }
-    #[doc = "DMA controller"]
+    #[doc = "Advanced-timers"]
     #[derive(Copy, Clone)]
-    pub struct Dma(pub *mut u8);
-    unsafe impl Send for Dma {}
-    unsafe impl Sync for Dma {}
-    impl Dma {
-        #[doc = "low interrupt status register"]
-        pub fn isr(self, n: usize) -> Reg<regs::Ixr, R> {
+    pub struct TimAdv(pub *mut u8);
+    unsafe impl Send for TimAdv {}
+    unsafe impl Sync for TimAdv {}
+    impl TimAdv {
+        #[doc = "control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2Adv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "slave mode control register"]
+        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        pub fn dier(self) -> Reg<regs::DierAdv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::SrAdv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "event generation register"]
+        pub fn egr(self) -> Reg<regs::EgrAdv, W> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "capture/compare mode register 1 (input mode)"]
+        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
             assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
         }
-        #[doc = "low interrupt flag clear register"]
-        pub fn ifcr(self, n: usize) -> Reg<regs::Ixr, W> {
+        #[doc = "capture/compare mode register 1 (output mode)"]
+        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
             assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
         }
-        #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
-        pub fn st(self, n: usize) -> St {
-            assert!(n < 8usize);
-            unsafe { St(self.0.add(16usize + n * 24usize)) }
+        #[doc = "capture/compare enable register"]
+        pub fn ccer(self) -> Reg<regs::CcerAdv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        }
+        #[doc = "counter"]
+        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        }
+        #[doc = "prescaler"]
+        pub fn psc(self) -> Reg<regs::Psc, RW> {
+            unsafe { Reg::from_ptr(self.0.add(40usize)) }
+        }
+        #[doc = "auto-reload register"]
+        pub fn arr(self) -> Reg<regs::Arr16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(44usize)) }
+        }
+        #[doc = "repetition counter register"]
+        pub fn rcr(self) -> Reg<regs::Rcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(48usize)) }
+        }
+        #[doc = "capture/compare register"]
+        pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
+        }
+        #[doc = "break and dead-time register"]
+        pub fn bdtr(self) -> Reg<regs::Bdtr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(68usize)) }
+        }
+        #[doc = "DMA control register"]
+        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(72usize)) }
+        }
+        #[doc = "DMA address for full transfer"]
+        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
+            unsafe { Reg::from_ptr(self.0.add(76usize)) }
+        }
+    }
+    #[doc = "Basic timer"]
+    #[derive(Copy, Clone)]
+    pub struct TimBasic(pub *mut u8);
+    unsafe impl Send for TimBasic {}
+    unsafe impl Sync for TimBasic {}
+    impl TimBasic {
+        #[doc = "control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1Basic, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2Basic, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        pub fn dier(self) -> Reg<regs::DierBasic, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::SrBasic, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "event generation register"]
+        pub fn egr(self) -> Reg<regs::EgrBasic, W> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "counter"]
+        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        }
+        #[doc = "prescaler"]
+        pub fn psc(self) -> Reg<regs::Psc, RW> {
+            unsafe { Reg::from_ptr(self.0.add(40usize)) }
+        }
+        #[doc = "auto-reload register"]
+        pub fn arr(self) -> Reg<regs::Arr16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(44usize)) }
+        }
+    }
+    #[doc = "General purpose 16-bit timer"]
+    #[derive(Copy, Clone)]
+    pub struct TimGp16(pub *mut u8);
+    unsafe impl Send for TimGp16 {}
+    unsafe impl Sync for TimGp16 {}
+    impl TimGp16 {
+        #[doc = "control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2Gp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "slave mode control register"]
+        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        pub fn dier(self) -> Reg<regs::DierGp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::SrGp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "event generation register"]
+        pub fn egr(self) -> Reg<regs::EgrGp, W> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "capture/compare mode register 1 (input mode)"]
+        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
+        }
+        #[doc = "capture/compare mode register 1 (output mode)"]
+        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
+        }
+        #[doc = "capture/compare enable register"]
+        pub fn ccer(self) -> Reg<regs::CcerGp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        }
+        #[doc = "counter"]
+        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        }
+        #[doc = "prescaler"]
+        pub fn psc(self) -> Reg<regs::Psc, RW> {
+            unsafe { Reg::from_ptr(self.0.add(40usize)) }
+        }
+        #[doc = "auto-reload register"]
+        pub fn arr(self) -> Reg<regs::Arr16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(44usize)) }
+        }
+        #[doc = "capture/compare register"]
+        pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
+        }
+        #[doc = "DMA control register"]
+        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(72usize)) }
+        }
+        #[doc = "DMA address for full transfer"]
+        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
+            unsafe { Reg::from_ptr(self.0.add(76usize)) }
         }
     }
     pub mod vals {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Fs(pub u8);
-        impl Fs {
-            #[doc = "0 < fifo_level < 1/4"]
-            pub const QUARTER1: Self = Self(0);
-            #[doc = "1/4 <= fifo_level < 1/2"]
-            pub const QUARTER2: Self = Self(0x01);
-            #[doc = "1/2 <= fifo_level < 3/4"]
-            pub const QUARTER3: Self = Self(0x02);
-            #[doc = "3/4 <= fifo_level < full"]
-            pub const QUARTER4: Self = Self(0x03);
-            #[doc = "FIFO is empty"]
-            pub const EMPTY: Self = Self(0x04);
-            #[doc = "FIFO is full"]
-            pub const FULL: Self = Self(0x05);
+        pub struct Ckd(pub u8);
+        impl Ckd {
+            #[doc = "t_DTS = t_CK_INT"]
+            pub const DIV1: Self = Self(0);
+            #[doc = "t_DTS = 2 × t_CK_INT"]
+            pub const DIV2: Self = Self(0x01);
+            #[doc = "t_DTS = 4 × t_CK_INT"]
+            pub const DIV4: Self = Self(0x02);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pfctrl(pub u8);
-        impl Pfctrl {
-            #[doc = "The DMA is the flow controller"]
-            pub const DMA: Self = Self(0);
-            #[doc = "The peripheral is the flow controller"]
-            pub const PERIPHERAL: Self = Self(0x01);
+        pub struct Ts(pub u8);
+        impl Ts {
+            #[doc = "Internal Trigger 0 (ITR0)"]
+            pub const ITR0: Self = Self(0);
+            #[doc = "Internal Trigger 1 (ITR1)"]
+            pub const ITR1: Self = Self(0x01);
+            #[doc = "Internal Trigger 2 (ITR2)"]
+            pub const ITR2: Self = Self(0x02);
+            #[doc = "TI1 Edge Detector (TI1F_ED)"]
+            pub const TI1F_ED: Self = Self(0x04);
+            #[doc = "Filtered Timer Input 1 (TI1FP1)"]
+            pub const TI1FP1: Self = Self(0x05);
+            #[doc = "Filtered Timer Input 2 (TI2FP2)"]
+            pub const TI2FP2: Self = Self(0x06);
+            #[doc = "External Trigger input (ETRF)"]
+            pub const ETRF: Self = Self(0x07);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pl(pub u8);
-        impl Pl {
-            #[doc = "Low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Medium"]
-            pub const MEDIUM: Self = Self(0x01);
-            #[doc = "High"]
-            pub const HIGH: Self = Self(0x02);
-            #[doc = "Very high"]
-            pub const VERYHIGH: Self = Self(0x03);
+        pub struct Tis(pub u8);
+        impl Tis {
+            #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
+            pub const NORMAL: Self = Self(0);
+            #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
+            pub const XOR: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Size(pub u8);
-        impl Size {
-            #[doc = "Byte (8-bit)"]
-            pub const BITS8: Self = Self(0);
-            #[doc = "Half-word (16-bit)"]
-            pub const BITS16: Self = Self(0x01);
-            #[doc = "Word (32-bit)"]
-            pub const BITS32: Self = Self(0x02);
+        pub struct Etf(pub u8);
+        impl Etf {
+            #[doc = "No filter, sampling is done at fDTS"]
+            pub const NOFILTER: Self = Self(0);
+            #[doc = "fSAMPLING=fCK_INT, N=2"]
+            pub const FCK_INT_N2: Self = Self(0x01);
+            #[doc = "fSAMPLING=fCK_INT, N=4"]
+            pub const FCK_INT_N4: Self = Self(0x02);
+            #[doc = "fSAMPLING=fCK_INT, N=8"]
+            pub const FCK_INT_N8: Self = Self(0x03);
+            #[doc = "fSAMPLING=fDTS/2, N=6"]
+            pub const FDTS_DIV2_N6: Self = Self(0x04);
+            #[doc = "fSAMPLING=fDTS/2, N=8"]
+            pub const FDTS_DIV2_N8: Self = Self(0x05);
+            #[doc = "fSAMPLING=fDTS/4, N=6"]
+            pub const FDTS_DIV4_N6: Self = Self(0x06);
+            #[doc = "fSAMPLING=fDTS/4, N=8"]
+            pub const FDTS_DIV4_N8: Self = Self(0x07);
+            #[doc = "fSAMPLING=fDTS/8, N=6"]
+            pub const FDTS_DIV8_N6: Self = Self(0x08);
+            #[doc = "fSAMPLING=fDTS/8, N=8"]
+            pub const FDTS_DIV8_N8: Self = Self(0x09);
+            #[doc = "fSAMPLING=fDTS/16, N=5"]
+            pub const FDTS_DIV16_N5: Self = Self(0x0a);
+            #[doc = "fSAMPLING=fDTS/16, N=6"]
+            pub const FDTS_DIV16_N6: Self = Self(0x0b);
+            #[doc = "fSAMPLING=fDTS/16, N=8"]
+            pub const FDTS_DIV16_N8: Self = Self(0x0c);
+            #[doc = "fSAMPLING=fDTS/32, N=5"]
+            pub const FDTS_DIV32_N5: Self = Self(0x0d);
+            #[doc = "fSAMPLING=fDTS/32, N=6"]
+            pub const FDTS_DIV32_N6: Self = Self(0x0e);
+            #[doc = "fSAMPLING=fDTS/32, N=8"]
+            pub const FDTS_DIV32_N8: Self = Self(0x0f);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Circ(pub u8);
-        impl Circ {
-            #[doc = "Circular mode disabled"]
+        pub struct Ocpe(pub u8);
+        impl Ocpe {
+            #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
             pub const DISABLED: Self = Self(0);
-            #[doc = "Circular mode enabled"]
+            #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
             pub const ENABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dmdis(pub u8);
-        impl Dmdis {
-            #[doc = "Direct mode is enabled"]
-            pub const ENABLED: Self = Self(0);
-            #[doc = "Direct mode is disabled"]
-            pub const DISABLED: Self = Self(0x01);
+        pub struct Ocm(pub u8);
+        impl Ocm {
+            #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
+            pub const FROZEN: Self = Self(0);
+            #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
+            pub const ACTIVEONMATCH: Self = Self(0x01);
+            #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
+            pub const INACTIVEONMATCH: Self = Self(0x02);
+            #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
+            pub const TOGGLE: Self = Self(0x03);
+            #[doc = "OCyREF is forced low"]
+            pub const FORCEINACTIVE: Self = Self(0x04);
+            #[doc = "OCyREF is forced high"]
+            pub const FORCEACTIVE: Self = Self(0x05);
+            #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
+            pub const PWMMODE1: Self = Self(0x06);
+            #[doc = "Inversely to PwmMode1"]
+            pub const PWMMODE2: Self = Self(0x07);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Mms(pub u8);
+        impl Mms {
+            #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
+            pub const RESET: Self = Self(0);
+            #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
+            pub const ENABLE: Self = Self(0x01);
+            #[doc = "The update event is selected as trigger output"]
+            pub const UPDATE: Self = Self(0x02);
+            #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
+            pub const COMPAREPULSE: Self = Self(0x03);
+            #[doc = "OC1REF signal is used as trigger output"]
+            pub const COMPAREOC1: Self = Self(0x04);
+            #[doc = "OC2REF signal is used as trigger output"]
+            pub const COMPAREOC2: Self = Self(0x05);
+            #[doc = "OC3REF signal is used as trigger output"]
+            pub const COMPAREOC3: Self = Self(0x06);
+            #[doc = "OC4REF signal is used as trigger output"]
+            pub const COMPAREOC4: Self = Self(0x07);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct CcmrOutputCcs(pub u8);
+        impl CcmrOutputCcs {
+            #[doc = "CCx channel is configured as output"]
+            pub const OUTPUT: Self = Self(0);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Arpe(pub u8);
+        impl Arpe {
+            #[doc = "TIMx_APRR register is not buffered"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "TIMx_APRR register is buffered"]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Etps(pub u8);
+        impl Etps {
+            #[doc = "Prescaler OFF"]
+            pub const DIV1: Self = Self(0);
+            #[doc = "ETRP frequency divided by 2"]
+            pub const DIV2: Self = Self(0x01);
+            #[doc = "ETRP frequency divided by 4"]
+            pub const DIV4: Self = Self(0x02);
+            #[doc = "ETRP frequency divided by 8"]
+            pub const DIV8: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Dir(pub u8);
         impl Dir {
-            #[doc = "Peripheral-to-memory"]
-            pub const PERIPHERALTOMEMORY: Self = Self(0);
-            #[doc = "Memory-to-peripheral"]
-            pub const MEMORYTOPERIPHERAL: Self = Self(0x01);
-            #[doc = "Memory-to-memory"]
-            pub const MEMORYTOMEMORY: Self = Self(0x02);
+            #[doc = "Counter used as upcounter"]
+            pub const UP: Self = Self(0);
+            #[doc = "Counter used as downcounter"]
+            pub const DOWN: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Fth(pub u8);
-        impl Fth {
-            #[doc = "1/4 full FIFO"]
-            pub const QUARTER: Self = Self(0);
-            #[doc = "1/2 full FIFO"]
-            pub const HALF: Self = Self(0x01);
-            #[doc = "3/4 full FIFO"]
-            pub const THREEQUARTERS: Self = Self(0x02);
-            #[doc = "Full FIFO"]
-            pub const FULL: Self = Self(0x03);
+        pub struct Sms(pub u8);
+        impl Sms {
+            #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
+            pub const ENCODER_MODE_1: Self = Self(0x01);
+            #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
+            pub const ENCODER_MODE_2: Self = Self(0x02);
+            #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
+            pub const ENCODER_MODE_3: Self = Self(0x03);
+            #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
+            pub const RESET_MODE: Self = Self(0x04);
+            #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
+            pub const GATED_MODE: Self = Self(0x05);
+            #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
+            pub const TRIGGER_MODE: Self = Self(0x06);
+            #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
+            pub const EXT_CLOCK_MODE: Self = Self(0x07);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Inc(pub u8);
-        impl Inc {
-            #[doc = "Address pointer is fixed"]
-            pub const FIXED: Self = Self(0);
-            #[doc = "Address pointer is incremented after each data transfer"]
-            pub const INCREMENTED: Self = Self(0x01);
+        pub struct Cms(pub u8);
+        impl Cms {
+            #[doc = "The counter counts up or down depending on the direction bit"]
+            pub const EDGEALIGNED: Self = Self(0);
+            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
+            pub const CENTERALIGNED1: Self = Self(0x01);
+            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
+            pub const CENTERALIGNED2: Self = Self(0x02);
+            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
+            pub const CENTERALIGNED3: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Burst(pub u8);
-        impl Burst {
-            #[doc = "Single transfer"]
-            pub const SINGLE: Self = Self(0);
-            #[doc = "Incremental burst of 4 beats"]
-            pub const INCR4: Self = Self(0x01);
-            #[doc = "Incremental burst of 8 beats"]
-            pub const INCR8: Self = Self(0x02);
-            #[doc = "Incremental burst of 16 beats"]
-            pub const INCR16: Self = Self(0x03);
+        pub struct Ccds(pub u8);
+        impl Ccds {
+            #[doc = "CCx DMA request sent when CCx event occurs"]
+            pub const ONCOMPARE: Self = Self(0);
+            #[doc = "CCx DMA request sent when update event occurs"]
+            pub const ONUPDATE: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pincos(pub u8);
-        impl Pincos {
-            #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"]
-            pub const PSIZE: Self = Self(0);
-            #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"]
-            pub const FIXED4: Self = Self(0x01);
+        pub struct Opm(pub u8);
+        impl Opm {
+            #[doc = "Counter is not stopped at update event"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
+            pub const ENABLED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dbm(pub u8);
-        impl Dbm {
-            #[doc = "No buffer switching at the end of transfer"]
+        pub struct Etp(pub u8);
+        impl Etp {
+            #[doc = "ETR is noninverted, active at high level or rising edge"]
+            pub const NOTINVERTED: Self = Self(0);
+            #[doc = "ETR is inverted, active at low level or falling edge"]
+            pub const INVERTED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Urs(pub u8);
+        impl Urs {
+            #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
+            pub const ANYEVENT: Self = Self(0);
+            #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
+            pub const COUNTERONLY: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ossr(pub u8);
+        impl Ossr {
+            #[doc = "When inactive, OC/OCN outputs are disabled"]
             pub const DISABLED: Self = Self(0);
-            #[doc = "Memory target switched at the end of the DMA transfer"]
-            pub const ENABLED: Self = Self(0x01);
+            #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"]
+            pub const IDLELEVEL: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ct(pub u8);
-        impl Ct {
-            #[doc = "The current target memory is Memory 0"]
-            pub const MEMORY0: Self = Self(0);
-            #[doc = "The current target memory is Memory 1"]
-            pub const MEMORY1: Self = Self(0x01);
+        pub struct CcmrInputCcs(pub u8);
+        impl CcmrInputCcs {
+            #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
+            pub const TI4: Self = Self(0x01);
+            #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
+            pub const TI3: Self = Self(0x02);
+            #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
+            pub const TRC: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ossi(pub u8);
+        impl Ossi {
+            #[doc = "When inactive, OC/OCN outputs are disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "When inactive, OC/OCN outputs are forced to idle level"]
+            pub const IDLELEVEL: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Msm(pub u8);
+        impl Msm {
+            #[doc = "No action"]
+            pub const NOSYNC: Self = Self(0);
+            #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
+            pub const SYNC: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Icf(pub u8);
+        impl Icf {
+            #[doc = "No filter, sampling is done at fDTS"]
+            pub const NOFILTER: Self = Self(0);
+            #[doc = "fSAMPLING=fCK_INT, N=2"]
+            pub const FCK_INT_N2: Self = Self(0x01);
+            #[doc = "fSAMPLING=fCK_INT, N=4"]
+            pub const FCK_INT_N4: Self = Self(0x02);
+            #[doc = "fSAMPLING=fCK_INT, N=8"]
+            pub const FCK_INT_N8: Self = Self(0x03);
+            #[doc = "fSAMPLING=fDTS/2, N=6"]
+            pub const FDTS_DIV2_N6: Self = Self(0x04);
+            #[doc = "fSAMPLING=fDTS/2, N=8"]
+            pub const FDTS_DIV2_N8: Self = Self(0x05);
+            #[doc = "fSAMPLING=fDTS/4, N=6"]
+            pub const FDTS_DIV4_N6: Self = Self(0x06);
+            #[doc = "fSAMPLING=fDTS/4, N=8"]
+            pub const FDTS_DIV4_N8: Self = Self(0x07);
+            #[doc = "fSAMPLING=fDTS/8, N=6"]
+            pub const FDTS_DIV8_N6: Self = Self(0x08);
+            #[doc = "fSAMPLING=fDTS/8, N=8"]
+            pub const FDTS_DIV8_N8: Self = Self(0x09);
+            #[doc = "fSAMPLING=fDTS/16, N=5"]
+            pub const FDTS_DIV16_N5: Self = Self(0x0a);
+            #[doc = "fSAMPLING=fDTS/16, N=6"]
+            pub const FDTS_DIV16_N6: Self = Self(0x0b);
+            #[doc = "fSAMPLING=fDTS/16, N=8"]
+            pub const FDTS_DIV16_N8: Self = Self(0x0c);
+            #[doc = "fSAMPLING=fDTS/32, N=5"]
+            pub const FDTS_DIV32_N5: Self = Self(0x0d);
+            #[doc = "fSAMPLING=fDTS/32, N=6"]
+            pub const FDTS_DIV32_N6: Self = Self(0x0e);
+            #[doc = "fSAMPLING=fDTS/32, N=8"]
+            pub const FDTS_DIV32_N8: Self = Self(0x0f);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ece(pub u8);
+        impl Ece {
+            #[doc = "External clock mode 2 disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
+            pub const ENABLED: Self = Self(0x01);
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "stream x FIFO control register"]
+        #[doc = "capture/compare register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Fcr(pub u32);
-        impl Fcr {
-            #[doc = "FIFO threshold selection"]
-            pub const fn fth(&self) -> super::vals::Fth {
-                let val = (self.0 >> 0usize) & 0x03;
-                super::vals::Fth(val as u8)
+        pub struct Ccr32(pub u32);
+        impl Ccr32 {
+            #[doc = "Capture/Compare 1 value"]
+            pub const fn ccr(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "FIFO threshold selection"]
-            pub fn set_fth(&mut self, val: super::vals::Fth) {
-                self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
+            #[doc = "Capture/Compare 1 value"]
+            pub fn set_ccr(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
-            #[doc = "Direct mode disable"]
-            pub const fn dmdis(&self) -> super::vals::Dmdis {
+        }
+        impl Default for Ccr32 {
+            fn default() -> Ccr32 {
+                Ccr32(0)
+            }
+        }
+        #[doc = "control register 1"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr1Basic(pub u32);
+        impl Cr1Basic {
+            #[doc = "Counter enable"]
+            pub const fn cen(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Counter enable"]
+            pub fn set_cen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Update disable"]
+            pub const fn udis(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update disable"]
+            pub fn set_udis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Update request source"]
+            pub const fn urs(&self) -> super::vals::Urs {
                 let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Dmdis(val as u8)
+                super::vals::Urs(val as u8)
             }
-            #[doc = "Direct mode disable"]
-            pub fn set_dmdis(&mut self, val: super::vals::Dmdis) {
+            #[doc = "Update request source"]
+            pub fn set_urs(&mut self, val: super::vals::Urs) {
                 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
             }
-            #[doc = "FIFO status"]
-            pub const fn fs(&self) -> super::vals::Fs {
-                let val = (self.0 >> 3usize) & 0x07;
-                super::vals::Fs(val as u8)
+            #[doc = "One-pulse mode"]
+            pub const fn opm(&self) -> super::vals::Opm {
+                let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Opm(val as u8)
             }
-            #[doc = "FIFO status"]
-            pub fn set_fs(&mut self, val: super::vals::Fs) {
-                self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
+            #[doc = "One-pulse mode"]
+            pub fn set_opm(&mut self, val: super::vals::Opm) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
             }
-            #[doc = "FIFO error interrupt enable"]
-            pub const fn feie(&self) -> bool {
+            #[doc = "Auto-reload preload enable"]
+            pub const fn arpe(&self) -> super::vals::Arpe {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Arpe(val as u8)
+            }
+            #[doc = "Auto-reload preload enable"]
+            pub fn set_arpe(&mut self, val: super::vals::Arpe) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+        }
+        impl Default for Cr1Basic {
+            fn default() -> Cr1Basic {
+                Cr1Basic(0)
+            }
+        }
+        #[doc = "capture/compare mode register 1 (input mode)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct CcmrInput(pub u32);
+        impl CcmrInput {
+            #[doc = "Capture/Compare 1 selection"]
+            pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
+                assert!(n < 2usize);
+                let offs = 0usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::CcmrInputCcs(val as u8)
+            }
+            #[doc = "Capture/Compare 1 selection"]
+            pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
+                assert!(n < 2usize);
+                let offs = 0usize + n * 8usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            }
+            #[doc = "Input capture 1 prescaler"]
+            pub fn icpsc(&self, n: usize) -> u8 {
+                assert!(n < 2usize);
+                let offs = 2usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x03;
+                val as u8
+            }
+            #[doc = "Input capture 1 prescaler"]
+            pub fn set_icpsc(&mut self, n: usize, val: u8) {
+                assert!(n < 2usize);
+                let offs = 2usize + n * 8usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
+            }
+            #[doc = "Input capture 1 filter"]
+            pub fn icf(&self, n: usize) -> super::vals::Icf {
+                assert!(n < 2usize);
+                let offs = 4usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x0f;
+                super::vals::Icf(val as u8)
+            }
+            #[doc = "Input capture 1 filter"]
+            pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) {
+                assert!(n < 2usize);
+                let offs = 4usize + n * 8usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
+            }
+        }
+        impl Default for CcmrInput {
+            fn default() -> CcmrInput {
+                CcmrInput(0)
+            }
+        }
+        #[doc = "slave mode control register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Smcr(pub u32);
+        impl Smcr {
+            #[doc = "Slave mode selection"]
+            pub const fn sms(&self) -> super::vals::Sms {
+                let val = (self.0 >> 0usize) & 0x07;
+                super::vals::Sms(val as u8)
+            }
+            #[doc = "Slave mode selection"]
+            pub fn set_sms(&mut self, val: super::vals::Sms) {
+                self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
+            }
+            #[doc = "Trigger selection"]
+            pub const fn ts(&self) -> super::vals::Ts {
+                let val = (self.0 >> 4usize) & 0x07;
+                super::vals::Ts(val as u8)
+            }
+            #[doc = "Trigger selection"]
+            pub fn set_ts(&mut self, val: super::vals::Ts) {
+                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
+            }
+            #[doc = "Master/Slave mode"]
+            pub const fn msm(&self) -> super::vals::Msm {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Msm(val as u8)
+            }
+            #[doc = "Master/Slave mode"]
+            pub fn set_msm(&mut self, val: super::vals::Msm) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+            #[doc = "External trigger filter"]
+            pub const fn etf(&self) -> super::vals::Etf {
+                let val = (self.0 >> 8usize) & 0x0f;
+                super::vals::Etf(val as u8)
+            }
+            #[doc = "External trigger filter"]
+            pub fn set_etf(&mut self, val: super::vals::Etf) {
+                self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
+            }
+            #[doc = "External trigger prescaler"]
+            pub const fn etps(&self) -> super::vals::Etps {
+                let val = (self.0 >> 12usize) & 0x03;
+                super::vals::Etps(val as u8)
+            }
+            #[doc = "External trigger prescaler"]
+            pub fn set_etps(&mut self, val: super::vals::Etps) {
+                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+            }
+            #[doc = "External clock enable"]
+            pub const fn ece(&self) -> super::vals::Ece {
+                let val = (self.0 >> 14usize) & 0x01;
+                super::vals::Ece(val as u8)
+            }
+            #[doc = "External clock enable"]
+            pub fn set_ece(&mut self, val: super::vals::Ece) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
+            }
+            #[doc = "External trigger polarity"]
+            pub const fn etp(&self) -> super::vals::Etp {
+                let val = (self.0 >> 15usize) & 0x01;
+                super::vals::Etp(val as u8)
+            }
+            #[doc = "External trigger polarity"]
+            pub fn set_etp(&mut self, val: super::vals::Etp) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            }
+        }
+        impl Default for Smcr {
+            fn default() -> Smcr {
+                Smcr(0)
+            }
+        }
+        #[doc = "counter"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cnt16(pub u32);
+        impl Cnt16 {
+            #[doc = "counter value"]
+            pub const fn cnt(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "counter value"]
+            pub fn set_cnt(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Cnt16 {
+            fn default() -> Cnt16 {
+                Cnt16(0)
+            }
+        }
+        #[doc = "prescaler"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Psc(pub u32);
+        impl Psc {
+            #[doc = "Prescaler value"]
+            pub const fn psc(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Prescaler value"]
+            pub fn set_psc(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Psc {
+            fn default() -> Psc {
+                Psc(0)
+            }
+        }
+        #[doc = "control register 2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr2Gp(pub u32);
+        impl Cr2Gp {
+            #[doc = "Capture/compare DMA selection"]
+            pub const fn ccds(&self) -> super::vals::Ccds {
+                let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Ccds(val as u8)
+            }
+            #[doc = "Capture/compare DMA selection"]
+            pub fn set_ccds(&mut self, val: super::vals::Ccds) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Master mode selection"]
+            pub const fn mms(&self) -> super::vals::Mms {
+                let val = (self.0 >> 4usize) & 0x07;
+                super::vals::Mms(val as u8)
+            }
+            #[doc = "Master mode selection"]
+            pub fn set_mms(&mut self, val: super::vals::Mms) {
+                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
+            }
+            #[doc = "TI1 selection"]
+            pub const fn ti1s(&self) -> super::vals::Tis {
                 let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Tis(val as u8)
+            }
+            #[doc = "TI1 selection"]
+            pub fn set_ti1s(&mut self, val: super::vals::Tis) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+        }
+        impl Default for Cr2Gp {
+            fn default() -> Cr2Gp {
+                Cr2Gp(0)
+            }
+        }
+        #[doc = "repetition counter register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Rcr(pub u32);
+        impl Rcr {
+            #[doc = "Repetition counter value"]
+            pub const fn rep(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
+            }
+            #[doc = "Repetition counter value"]
+            pub fn set_rep(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            }
+        }
+        impl Default for Rcr {
+            fn default() -> Rcr {
+                Rcr(0)
+            }
+        }
+        #[doc = "capture/compare mode register 2 (output mode)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct CcmrOutput(pub u32);
+        impl CcmrOutput {
+            #[doc = "Capture/Compare 3 selection"]
+            pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs {
+                assert!(n < 2usize);
+                let offs = 0usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::CcmrOutputCcs(val as u8)
+            }
+            #[doc = "Capture/Compare 3 selection"]
+            pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) {
+                assert!(n < 2usize);
+                let offs = 0usize + n * 8usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            }
+            #[doc = "Output compare 3 fast enable"]
+            pub fn ocfe(&self, n: usize) -> bool {
+                assert!(n < 2usize);
+                let offs = 2usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "FIFO error interrupt enable"]
-            pub fn set_feie(&mut self, val: bool) {
+            #[doc = "Output compare 3 fast enable"]
+            pub fn set_ocfe(&mut self, n: usize, val: bool) {
+                assert!(n < 2usize);
+                let offs = 2usize + n * 8usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Output compare 3 preload enable"]
+            pub fn ocpe(&self, n: usize) -> super::vals::Ocpe {
+                assert!(n < 2usize);
+                let offs = 3usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Ocpe(val as u8)
+            }
+            #[doc = "Output compare 3 preload enable"]
+            pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) {
+                assert!(n < 2usize);
+                let offs = 3usize + n * 8usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
+            #[doc = "Output compare 3 mode"]
+            pub fn ocm(&self, n: usize) -> super::vals::Ocm {
+                assert!(n < 2usize);
+                let offs = 4usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x07;
+                super::vals::Ocm(val as u8)
+            }
+            #[doc = "Output compare 3 mode"]
+            pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) {
+                assert!(n < 2usize);
+                let offs = 4usize + n * 8usize;
+                self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs);
+            }
+            #[doc = "Output compare 3 clear enable"]
+            pub fn occe(&self, n: usize) -> bool {
+                assert!(n < 2usize);
+                let offs = 7usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Output compare 3 clear enable"]
+            pub fn set_occe(&mut self, n: usize, val: bool) {
+                assert!(n < 2usize);
+                let offs = 7usize + n * 8usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for CcmrOutput {
+            fn default() -> CcmrOutput {
+                CcmrOutput(0)
+            }
+        }
+        #[doc = "event generation register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct EgrGp(pub u32);
+        impl EgrGp {
+            #[doc = "Update generation"]
+            pub const fn ug(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update generation"]
+            pub fn set_ug(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Capture/compare 1 generation"]
+            pub fn ccg(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/compare 1 generation"]
+            pub fn set_ccg(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare control update generation"]
+            pub const fn comg(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare control update generation"]
+            pub fn set_comg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Trigger generation"]
+            pub const fn tg(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger generation"]
+            pub fn set_tg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Break generation"]
+            pub const fn bg(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break generation"]
+            pub fn set_bg(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
         }
-        impl Default for Fcr {
-            fn default() -> Fcr {
-                Fcr(0)
+        impl Default for EgrGp {
+            fn default() -> EgrGp {
+                EgrGp(0)
             }
         }
-        #[doc = "stream x number of data register"]
+        #[doc = "capture/compare enable register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ndtr(pub u32);
-        impl Ndtr {
-            #[doc = "Number of data items to transfer"]
-            pub const fn ndt(&self) -> u16 {
+        pub struct CcerAdv(pub u32);
+        impl CcerAdv {
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn cce(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn set_cce(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccp(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccp(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare 1 complementary output enable"]
+            pub fn ccne(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 2usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 complementary output enable"]
+            pub fn set_ccne(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 2usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccnp(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 3usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccnp(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 3usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for CcerAdv {
+            fn default() -> CcerAdv {
+                CcerAdv(0)
+            }
+        }
+        #[doc = "status register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct SrBasic(pub u32);
+        impl SrBasic {
+            #[doc = "Update interrupt flag"]
+            pub const fn uif(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update interrupt flag"]
+            pub fn set_uif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+        }
+        impl Default for SrBasic {
+            fn default() -> SrBasic {
+                SrBasic(0)
+            }
+        }
+        #[doc = "status register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct SrAdv(pub u32);
+        impl SrAdv {
+            #[doc = "Update interrupt flag"]
+            pub const fn uif(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update interrupt flag"]
+            pub fn set_uif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Capture/compare 1 interrupt flag"]
+            pub fn ccif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/compare 1 interrupt flag"]
+            pub fn set_ccif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "COM interrupt flag"]
+            pub const fn comif(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "COM interrupt flag"]
+            pub fn set_comif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Trigger interrupt flag"]
+            pub const fn tif(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger interrupt flag"]
+            pub fn set_tif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Break interrupt flag"]
+            pub const fn bif(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break interrupt flag"]
+            pub fn set_bif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "Capture/Compare 1 overcapture flag"]
+            pub fn ccof(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 overcapture flag"]
+            pub fn set_ccof(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for SrAdv {
+            fn default() -> SrAdv {
+                SrAdv(0)
+            }
+        }
+        #[doc = "auto-reload register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Arr16(pub u32);
+        impl Arr16 {
+            #[doc = "Auto-reload value"]
+            pub const fn arr(&self) -> u16 {
                 let val = (self.0 >> 0usize) & 0xffff;
                 val as u16
             }
-            #[doc = "Number of data items to transfer"]
-            pub fn set_ndt(&mut self, val: u16) {
+            #[doc = "Auto-reload value"]
+            pub fn set_arr(&mut self, val: u16) {
                 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Ndtr {
-            fn default() -> Ndtr {
-                Ndtr(0)
+        impl Default for Arr16 {
+            fn default() -> Arr16 {
+                Arr16(0)
             }
         }
-        #[doc = "stream x configuration register"]
+        #[doc = "status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr(pub u32);
-        impl Cr {
-            #[doc = "Stream enable / flag stream ready when read low"]
-            pub const fn en(&self) -> bool {
+        pub struct SrGp(pub u32);
+        impl SrGp {
+            #[doc = "Update interrupt flag"]
+            pub const fn uif(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Stream enable / flag stream ready when read low"]
-            pub fn set_en(&mut self, val: bool) {
+            #[doc = "Update interrupt flag"]
+            pub fn set_uif(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Direct mode error interrupt enable"]
-            pub const fn dmeie(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
+            #[doc = "Capture/compare 1 interrupt flag"]
+            pub fn ccif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Direct mode error interrupt enable"]
-            pub fn set_dmeie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "Capture/compare 1 interrupt flag"]
+            pub fn set_ccif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Transfer error interrupt enable"]
-            pub const fn teie(&self) -> bool {
+            #[doc = "COM interrupt flag"]
+            pub const fn comif(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "COM interrupt flag"]
+            pub fn set_comif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Trigger interrupt flag"]
+            pub const fn tif(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger interrupt flag"]
+            pub fn set_tif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Break interrupt flag"]
+            pub const fn bif(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break interrupt flag"]
+            pub fn set_bif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "Capture/Compare 1 overcapture flag"]
+            pub fn ccof(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 overcapture flag"]
+            pub fn set_ccof(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for SrGp {
+            fn default() -> SrGp {
+                SrGp(0)
+            }
+        }
+        #[doc = "event generation register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct EgrBasic(pub u32);
+        impl EgrBasic {
+            #[doc = "Update generation"]
+            pub const fn ug(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update generation"]
+            pub fn set_ug(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+        }
+        impl Default for EgrBasic {
+            fn default() -> EgrBasic {
+                EgrBasic(0)
+            }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct DierGp(pub u32);
+        impl DierGp {
+            #[doc = "Update interrupt enable"]
+            pub const fn uie(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update interrupt enable"]
+            pub fn set_uie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Capture/Compare 1 interrupt enable"]
+            pub fn ccie(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 interrupt enable"]
+            pub fn set_ccie(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Trigger interrupt enable"]
+            pub const fn tie(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger interrupt enable"]
+            pub fn set_tie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Update DMA request enable"]
+            pub const fn ude(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update DMA request enable"]
+            pub fn set_ude(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Capture/Compare 1 DMA request enable"]
+            pub fn ccde(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 DMA request enable"]
+            pub fn set_ccde(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Trigger DMA request enable"]
+            pub const fn tde(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger DMA request enable"]
+            pub fn set_tde(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            }
+        }
+        impl Default for DierGp {
+            fn default() -> DierGp {
+                DierGp(0)
+            }
+        }
+        #[doc = "control register 2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr2Adv(pub u32);
+        impl Cr2Adv {
+            #[doc = "Capture/compare preloaded control"]
+            pub const fn ccpc(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/compare preloaded control"]
+            pub fn set_ccpc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Capture/compare control update selection"]
+            pub const fn ccus(&self) -> bool {
                 let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transfer error interrupt enable"]
-            pub fn set_teie(&mut self, val: bool) {
+            #[doc = "Capture/compare control update selection"]
+            pub fn set_ccus(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Half transfer interrupt enable"]
-            pub const fn htie(&self) -> bool {
+            #[doc = "Capture/compare DMA selection"]
+            pub const fn ccds(&self) -> super::vals::Ccds {
                 let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Ccds(val as u8)
+            }
+            #[doc = "Capture/compare DMA selection"]
+            pub fn set_ccds(&mut self, val: super::vals::Ccds) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Master mode selection"]
+            pub const fn mms(&self) -> super::vals::Mms {
+                let val = (self.0 >> 4usize) & 0x07;
+                super::vals::Mms(val as u8)
+            }
+            #[doc = "Master mode selection"]
+            pub fn set_mms(&mut self, val: super::vals::Mms) {
+                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
+            }
+            #[doc = "TI1 selection"]
+            pub const fn ti1s(&self) -> super::vals::Tis {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Tis(val as u8)
+            }
+            #[doc = "TI1 selection"]
+            pub fn set_ti1s(&mut self, val: super::vals::Tis) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+            #[doc = "Output Idle state 1"]
+            pub fn ois(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 8usize + n * 2usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Half transfer interrupt enable"]
-            pub fn set_htie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "Output Idle state 1"]
+            pub fn set_ois(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 8usize + n * 2usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Transfer complete interrupt enable"]
-            pub const fn tcie(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
+            #[doc = "Output Idle state 1"]
+            pub const fn ois1n(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transfer complete interrupt enable"]
-            pub fn set_tcie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            #[doc = "Output Idle state 1"]
+            pub fn set_ois1n(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
             }
-            #[doc = "Peripheral flow controller"]
-            pub const fn pfctrl(&self) -> super::vals::Pfctrl {
-                let val = (self.0 >> 5usize) & 0x01;
-                super::vals::Pfctrl(val as u8)
+            #[doc = "Output Idle state 2"]
+            pub const fn ois2n(&self) -> bool {
+                let val = (self.0 >> 11usize) & 0x01;
+                val != 0
             }
-            #[doc = "Peripheral flow controller"]
-            pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
+            #[doc = "Output Idle state 2"]
+            pub fn set_ois2n(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
             }
-            #[doc = "Data transfer direction"]
-            pub const fn dir(&self) -> super::vals::Dir {
-                let val = (self.0 >> 6usize) & 0x03;
-                super::vals::Dir(val as u8)
+            #[doc = "Output Idle state 3"]
+            pub const fn ois3n(&self) -> bool {
+                let val = (self.0 >> 13usize) & 0x01;
+                val != 0
             }
-            #[doc = "Data transfer direction"]
-            pub fn set_dir(&mut self, val: super::vals::Dir) {
-                self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize);
+            #[doc = "Output Idle state 3"]
+            pub fn set_ois3n(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
             }
-            #[doc = "Circular mode"]
-            pub const fn circ(&self) -> super::vals::Circ {
+        }
+        impl Default for Cr2Adv {
+            fn default() -> Cr2Adv {
+                Cr2Adv(0)
+            }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct DierBasic(pub u32);
+        impl DierBasic {
+            #[doc = "Update interrupt enable"]
+            pub const fn uie(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update interrupt enable"]
+            pub fn set_uie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Update DMA request enable"]
+            pub const fn ude(&self) -> bool {
                 let val = (self.0 >> 8usize) & 0x01;
-                super::vals::Circ(val as u8)
+                val != 0
             }
-            #[doc = "Circular mode"]
-            pub fn set_circ(&mut self, val: super::vals::Circ) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
+            #[doc = "Update DMA request enable"]
+            pub fn set_ude(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Peripheral increment mode"]
-            pub const fn pinc(&self) -> super::vals::Inc {
-                let val = (self.0 >> 9usize) & 0x01;
-                super::vals::Inc(val as u8)
+        }
+        impl Default for DierBasic {
+            fn default() -> DierBasic {
+                DierBasic(0)
             }
-            #[doc = "Peripheral increment mode"]
-            pub fn set_pinc(&mut self, val: super::vals::Inc) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
+        }
+        #[doc = "event generation register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct EgrAdv(pub u32);
+        impl EgrAdv {
+            #[doc = "Update generation"]
+            pub const fn ug(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Memory increment mode"]
-            pub const fn minc(&self) -> super::vals::Inc {
+            #[doc = "Update generation"]
+            pub fn set_ug(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Capture/compare 1 generation"]
+            pub fn ccg(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/compare 1 generation"]
+            pub fn set_ccg(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare control update generation"]
+            pub const fn comg(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare control update generation"]
+            pub fn set_comg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Trigger generation"]
+            pub const fn tg(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger generation"]
+            pub fn set_tg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Break generation"]
+            pub const fn bg(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break generation"]
+            pub fn set_bg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+        }
+        impl Default for EgrAdv {
+            fn default() -> EgrAdv {
+                EgrAdv(0)
+            }
+        }
+        #[doc = "break and dead-time register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Bdtr(pub u32);
+        impl Bdtr {
+            #[doc = "Dead-time generator setup"]
+            pub const fn dtg(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
+            }
+            #[doc = "Dead-time generator setup"]
+            pub fn set_dtg(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            }
+            #[doc = "Lock configuration"]
+            pub const fn lock(&self) -> u8 {
+                let val = (self.0 >> 8usize) & 0x03;
+                val as u8
+            }
+            #[doc = "Lock configuration"]
+            pub fn set_lock(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
+            }
+            #[doc = "Off-state selection for Idle mode"]
+            pub const fn ossi(&self) -> super::vals::Ossi {
                 let val = (self.0 >> 10usize) & 0x01;
-                super::vals::Inc(val as u8)
+                super::vals::Ossi(val as u8)
             }
-            #[doc = "Memory increment mode"]
-            pub fn set_minc(&mut self, val: super::vals::Inc) {
+            #[doc = "Off-state selection for Idle mode"]
+            pub fn set_ossi(&mut self, val: super::vals::Ossi) {
                 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
             }
-            #[doc = "Peripheral data size"]
-            pub const fn psize(&self) -> super::vals::Size {
-                let val = (self.0 >> 11usize) & 0x03;
-                super::vals::Size(val as u8)
+            #[doc = "Off-state selection for Run mode"]
+            pub const fn ossr(&self) -> super::vals::Ossr {
+                let val = (self.0 >> 11usize) & 0x01;
+                super::vals::Ossr(val as u8)
             }
-            #[doc = "Peripheral data size"]
-            pub fn set_psize(&mut self, val: super::vals::Size) {
-                self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
+            #[doc = "Off-state selection for Run mode"]
+            pub fn set_ossr(&mut self, val: super::vals::Ossr) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
             }
-            #[doc = "Memory data size"]
-            pub const fn msize(&self) -> super::vals::Size {
-                let val = (self.0 >> 13usize) & 0x03;
-                super::vals::Size(val as u8)
+            #[doc = "Break enable"]
+            pub const fn bke(&self) -> bool {
+                let val = (self.0 >> 12usize) & 0x01;
+                val != 0
             }
-            #[doc = "Memory data size"]
-            pub fn set_msize(&mut self, val: super::vals::Size) {
-                self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
+            #[doc = "Break enable"]
+            pub fn set_bke(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
             }
-            #[doc = "Peripheral increment offset size"]
-            pub const fn pincos(&self) -> super::vals::Pincos {
+            #[doc = "Break polarity"]
+            pub const fn bkp(&self) -> bool {
+                let val = (self.0 >> 13usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break polarity"]
+            pub fn set_bkp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            }
+            #[doc = "Automatic output enable"]
+            pub const fn aoe(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Automatic output enable"]
+            pub fn set_aoe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            }
+            #[doc = "Main output enable"]
+            pub const fn moe(&self) -> bool {
                 let val = (self.0 >> 15usize) & 0x01;
-                super::vals::Pincos(val as u8)
+                val != 0
             }
-            #[doc = "Peripheral increment offset size"]
-            pub fn set_pincos(&mut self, val: super::vals::Pincos) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            #[doc = "Main output enable"]
+            pub fn set_moe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
             }
-            #[doc = "Priority level"]
-            pub const fn pl(&self) -> super::vals::Pl {
-                let val = (self.0 >> 16usize) & 0x03;
-                super::vals::Pl(val as u8)
+        }
+        impl Default for Bdtr {
+            fn default() -> Bdtr {
+                Bdtr(0)
             }
-            #[doc = "Priority level"]
-            pub fn set_pl(&mut self, val: super::vals::Pl) {
-                self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
+        }
+        #[doc = "counter"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cnt32(pub u32);
+        impl Cnt32 {
+            #[doc = "counter value"]
+            pub const fn cnt(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "Double buffer mode"]
-            pub const fn dbm(&self) -> super::vals::Dbm {
-                let val = (self.0 >> 18usize) & 0x01;
-                super::vals::Dbm(val as u8)
+            #[doc = "counter value"]
+            pub fn set_cnt(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
-            #[doc = "Double buffer mode"]
-            pub fn set_dbm(&mut self, val: super::vals::Dbm) {
-                self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
+        }
+        impl Default for Cnt32 {
+            fn default() -> Cnt32 {
+                Cnt32(0)
             }
-            #[doc = "Current target (only in double buffer mode)"]
-            pub const fn ct(&self) -> super::vals::Ct {
-                let val = (self.0 >> 19usize) & 0x01;
-                super::vals::Ct(val as u8)
+        }
+        #[doc = "auto-reload register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Arr32(pub u32);
+        impl Arr32 {
+            #[doc = "Auto-reload value"]
+            pub const fn arr(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "Current target (only in double buffer mode)"]
-            pub fn set_ct(&mut self, val: super::vals::Ct) {
-                self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
+            #[doc = "Auto-reload value"]
+            pub fn set_arr(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
-            #[doc = "Peripheral burst transfer configuration"]
-            pub const fn pburst(&self) -> super::vals::Burst {
-                let val = (self.0 >> 21usize) & 0x03;
-                super::vals::Burst(val as u8)
+        }
+        impl Default for Arr32 {
+            fn default() -> Arr32 {
+                Arr32(0)
             }
-            #[doc = "Peripheral burst transfer configuration"]
-            pub fn set_pburst(&mut self, val: super::vals::Burst) {
-                self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
+        }
+        #[doc = "control register 1"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr1Gp(pub u32);
+        impl Cr1Gp {
+            #[doc = "Counter enable"]
+            pub const fn cen(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Memory burst transfer configuration"]
-            pub const fn mburst(&self) -> super::vals::Burst {
-                let val = (self.0 >> 23usize) & 0x03;
-                super::vals::Burst(val as u8)
+            #[doc = "Counter enable"]
+            pub fn set_cen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Memory burst transfer configuration"]
-            pub fn set_mburst(&mut self, val: super::vals::Burst) {
-                self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize);
+            #[doc = "Update disable"]
+            pub const fn udis(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
             }
-            #[doc = "Channel selection"]
-            pub const fn chsel(&self) -> u8 {
-                let val = (self.0 >> 25usize) & 0x0f;
-                val as u8
+            #[doc = "Update disable"]
+            pub fn set_udis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Channel selection"]
-            pub fn set_chsel(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
+            #[doc = "Update request source"]
+            pub const fn urs(&self) -> super::vals::Urs {
+                let val = (self.0 >> 2usize) & 0x01;
+                super::vals::Urs(val as u8)
+            }
+            #[doc = "Update request source"]
+            pub fn set_urs(&mut self, val: super::vals::Urs) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
+            }
+            #[doc = "One-pulse mode"]
+            pub const fn opm(&self) -> super::vals::Opm {
+                let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Opm(val as u8)
+            }
+            #[doc = "One-pulse mode"]
+            pub fn set_opm(&mut self, val: super::vals::Opm) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Direction"]
+            pub const fn dir(&self) -> super::vals::Dir {
+                let val = (self.0 >> 4usize) & 0x01;
+                super::vals::Dir(val as u8)
+            }
+            #[doc = "Direction"]
+            pub fn set_dir(&mut self, val: super::vals::Dir) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
+            }
+            #[doc = "Center-aligned mode selection"]
+            pub const fn cms(&self) -> super::vals::Cms {
+                let val = (self.0 >> 5usize) & 0x03;
+                super::vals::Cms(val as u8)
+            }
+            #[doc = "Center-aligned mode selection"]
+            pub fn set_cms(&mut self, val: super::vals::Cms) {
+                self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize);
+            }
+            #[doc = "Auto-reload preload enable"]
+            pub const fn arpe(&self) -> super::vals::Arpe {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Arpe(val as u8)
+            }
+            #[doc = "Auto-reload preload enable"]
+            pub fn set_arpe(&mut self, val: super::vals::Arpe) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+            #[doc = "Clock division"]
+            pub const fn ckd(&self) -> super::vals::Ckd {
+                let val = (self.0 >> 8usize) & 0x03;
+                super::vals::Ckd(val as u8)
+            }
+            #[doc = "Clock division"]
+            pub fn set_ckd(&mut self, val: super::vals::Ckd) {
+                self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
             }
         }
-        impl Default for Cr {
-            fn default() -> Cr {
-                Cr(0)
+        impl Default for Cr1Gp {
+            fn default() -> Cr1Gp {
+                Cr1Gp(0)
             }
         }
-        #[doc = "interrupt register"]
+        #[doc = "DMA/Interrupt enable register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ixr(pub u32);
-        impl Ixr {
-            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
-            pub fn feif(&self, n: usize) -> bool {
+        pub struct DierAdv(pub u32);
+        impl DierAdv {
+            #[doc = "Update interrupt enable"]
+            pub const fn uie(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update interrupt enable"]
+            pub fn set_uie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Capture/Compare 1 interrupt enable"]
+            pub fn ccie(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 1usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
-            pub fn set_feif(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/Compare 1 interrupt enable"]
+            pub fn set_ccie(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 1usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
-            pub fn dmeif(&self, n: usize) -> bool {
+            #[doc = "COM interrupt enable"]
+            pub const fn comie(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "COM interrupt enable"]
+            pub fn set_comie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Trigger interrupt enable"]
+            pub const fn tie(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger interrupt enable"]
+            pub fn set_tie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Break interrupt enable"]
+            pub const fn bie(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break interrupt enable"]
+            pub fn set_bie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "Update DMA request enable"]
+            pub const fn ude(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update DMA request enable"]
+            pub fn set_ude(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Capture/Compare 1 DMA request enable"]
+            pub fn ccde(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 9usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
-            pub fn set_dmeif(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/Compare 1 DMA request enable"]
+            pub fn set_ccde(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 9usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
-            pub fn teif(&self, n: usize) -> bool {
+            #[doc = "COM DMA request enable"]
+            pub const fn comde(&self) -> bool {
+                let val = (self.0 >> 13usize) & 0x01;
+                val != 0
+            }
+            #[doc = "COM DMA request enable"]
+            pub fn set_comde(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            }
+            #[doc = "Trigger DMA request enable"]
+            pub const fn tde(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger DMA request enable"]
+            pub fn set_tde(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            }
+        }
+        impl Default for DierAdv {
+            fn default() -> DierAdv {
+                DierAdv(0)
+            }
+        }
+        #[doc = "capture/compare register 1"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ccr16(pub u32);
+        impl Ccr16 {
+            #[doc = "Capture/Compare 1 value"]
+            pub const fn ccr(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Capture/Compare 1 value"]
+            pub fn set_ccr(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Ccr16 {
+            fn default() -> Ccr16 {
+                Ccr16(0)
+            }
+        }
+        #[doc = "capture/compare enable register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct CcerGp(pub u32);
+        impl CcerGp {
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn cce(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 0usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
-            pub fn set_teif(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn set_cce(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 0usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
-            pub fn htif(&self, n: usize) -> bool {
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccp(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 1usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
-            pub fn set_htif(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccp(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 1usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
-            pub fn tcif(&self, n: usize) -> bool {
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccnp(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 3usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
-            pub fn set_tcif(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccnp(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let offs = 3usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Ixr {
-            fn default() -> Ixr {
-                Ixr(0)
+        impl Default for CcerGp {
+            fn default() -> CcerGp {
+                CcerGp(0)
+            }
+        }
+        #[doc = "DMA control register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Dcr(pub u32);
+        impl Dcr {
+            #[doc = "DMA base address"]
+            pub const fn dba(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x1f;
+                val as u8
+            }
+            #[doc = "DMA base address"]
+            pub fn set_dba(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+            }
+            #[doc = "DMA burst length"]
+            pub const fn dbl(&self) -> u8 {
+                let val = (self.0 >> 8usize) & 0x1f;
+                val as u8
+            }
+            #[doc = "DMA burst length"]
+            pub fn set_dbl(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+            }
+        }
+        impl Default for Dcr {
+            fn default() -> Dcr {
+                Dcr(0)
+            }
+        }
+        #[doc = "control register 2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr2Basic(pub u32);
+        impl Cr2Basic {
+            #[doc = "Master mode selection"]
+            pub const fn mms(&self) -> super::vals::Mms {
+                let val = (self.0 >> 4usize) & 0x07;
+                super::vals::Mms(val as u8)
+            }
+            #[doc = "Master mode selection"]
+            pub fn set_mms(&mut self, val: super::vals::Mms) {
+                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
+            }
+        }
+        impl Default for Cr2Basic {
+            fn default() -> Cr2Basic {
+                Cr2Basic(0)
+            }
+        }
+        #[doc = "DMA address for full transfer"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Dmar(pub u32);
+        impl Dmar {
+            #[doc = "DMA register for burst accesses"]
+            pub const fn dmab(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "DMA register for burst accesses"]
+            pub fn set_dmab(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Dmar {
+            fn default() -> Dmar {
+                Dmar(0)
             }
         }
     }
diff --git a/embassy-stm32/src/pac/stm32h723ve.rs b/embassy-stm32/src/pac/stm32h723ve.rs
index aedcde8e5..3952a98dc 100644
--- a/embassy-stm32/src/pac/stm32h723ve.rs
+++ b/embassy-stm32/src/pac/stm32h723ve.rs
@@ -229,12 +229,66 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +306,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h723vg.rs b/embassy-stm32/src/pac/stm32h723vg.rs
index aedcde8e5..3952a98dc 100644
--- a/embassy-stm32/src/pac/stm32h723vg.rs
+++ b/embassy-stm32/src/pac/stm32h723vg.rs
@@ -229,12 +229,66 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +306,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h723ze.rs b/embassy-stm32/src/pac/stm32h723ze.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h723ze.rs
+++ b/embassy-stm32/src/pac/stm32h723ze.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h723zg.rs b/embassy-stm32/src/pac/stm32h723zg.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h723zg.rs
+++ b/embassy-stm32/src/pac/stm32h723zg.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725ae.rs b/embassy-stm32/src/pac/stm32h725ae.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h725ae.rs
+++ b/embassy-stm32/src/pac/stm32h725ae.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725ag.rs b/embassy-stm32/src/pac/stm32h725ag.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h725ag.rs
+++ b/embassy-stm32/src/pac/stm32h725ag.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725ie.rs b/embassy-stm32/src/pac/stm32h725ie.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h725ie.rs
+++ b/embassy-stm32/src/pac/stm32h725ie.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725ig.rs b/embassy-stm32/src/pac/stm32h725ig.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h725ig.rs
+++ b/embassy-stm32/src/pac/stm32h725ig.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725re.rs b/embassy-stm32/src/pac/stm32h725re.rs
index aedcde8e5..ed3c37327 100644
--- a/embassy-stm32/src/pac/stm32h725re.rs
+++ b/embassy-stm32/src/pac/stm32h725re.rs
@@ -229,12 +229,58 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +298,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725rg.rs b/embassy-stm32/src/pac/stm32h725rg.rs
index aedcde8e5..ed3c37327 100644
--- a/embassy-stm32/src/pac/stm32h725rg.rs
+++ b/embassy-stm32/src/pac/stm32h725rg.rs
@@ -229,12 +229,58 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +298,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725ve.rs b/embassy-stm32/src/pac/stm32h725ve.rs
index aedcde8e5..3952a98dc 100644
--- a/embassy-stm32/src/pac/stm32h725ve.rs
+++ b/embassy-stm32/src/pac/stm32h725ve.rs
@@ -229,12 +229,66 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +306,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725vg.rs b/embassy-stm32/src/pac/stm32h725vg.rs
index aedcde8e5..3952a98dc 100644
--- a/embassy-stm32/src/pac/stm32h725vg.rs
+++ b/embassy-stm32/src/pac/stm32h725vg.rs
@@ -229,12 +229,66 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +306,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725ze.rs b/embassy-stm32/src/pac/stm32h725ze.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h725ze.rs
+++ b/embassy-stm32/src/pac/stm32h725ze.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h725zg.rs b/embassy-stm32/src/pac/stm32h725zg.rs
index aedcde8e5..f314aa31d 100644
--- a/embassy-stm32/src/pac/stm32h725zg.rs
+++ b/embassy-stm32/src/pac/stm32h725zg.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h730ab.rs b/embassy-stm32/src/pac/stm32h730ab.rs
index 589a1fd07..bb6a4d2cb 100644
--- a/embassy-stm32/src/pac/stm32h730ab.rs
+++ b/embassy-stm32/src/pac/stm32h730ab.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h730ib.rs b/embassy-stm32/src/pac/stm32h730ib.rs
index 589a1fd07..bb6a4d2cb 100644
--- a/embassy-stm32/src/pac/stm32h730ib.rs
+++ b/embassy-stm32/src/pac/stm32h730ib.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h730vb.rs b/embassy-stm32/src/pac/stm32h730vb.rs
index 589a1fd07..0a40d4028 100644
--- a/embassy-stm32/src/pac/stm32h730vb.rs
+++ b/embassy-stm32/src/pac/stm32h730vb.rs
@@ -229,12 +229,66 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +306,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h730zb.rs b/embassy-stm32/src/pac/stm32h730zb.rs
index 589a1fd07..bb6a4d2cb 100644
--- a/embassy-stm32/src/pac/stm32h730zb.rs
+++ b/embassy-stm32/src/pac/stm32h730zb.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h733vg.rs b/embassy-stm32/src/pac/stm32h733vg.rs
index 589a1fd07..0a40d4028 100644
--- a/embassy-stm32/src/pac/stm32h733vg.rs
+++ b/embassy-stm32/src/pac/stm32h733vg.rs
@@ -229,12 +229,66 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +306,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h733zg.rs b/embassy-stm32/src/pac/stm32h733zg.rs
index 589a1fd07..bb6a4d2cb 100644
--- a/embassy-stm32/src/pac/stm32h733zg.rs
+++ b/embassy-stm32/src/pac/stm32h733zg.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h735ag.rs b/embassy-stm32/src/pac/stm32h735ag.rs
index 589a1fd07..bb6a4d2cb 100644
--- a/embassy-stm32/src/pac/stm32h735ag.rs
+++ b/embassy-stm32/src/pac/stm32h735ag.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h735ig.rs b/embassy-stm32/src/pac/stm32h735ig.rs
index 589a1fd07..bb6a4d2cb 100644
--- a/embassy-stm32/src/pac/stm32h735ig.rs
+++ b/embassy-stm32/src/pac/stm32h735ig.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h735rg.rs b/embassy-stm32/src/pac/stm32h735rg.rs
index 589a1fd07..d522fba17 100644
--- a/embassy-stm32/src/pac/stm32h735rg.rs
+++ b/embassy-stm32/src/pac/stm32h735rg.rs
@@ -229,12 +229,58 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +298,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h735vg.rs b/embassy-stm32/src/pac/stm32h735vg.rs
index 589a1fd07..0a40d4028 100644
--- a/embassy-stm32/src/pac/stm32h735vg.rs
+++ b/embassy-stm32/src/pac/stm32h735vg.rs
@@ -229,12 +229,66 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +306,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h735zg.rs b/embassy-stm32/src/pac/stm32h735zg.rs
index 589a1fd07..bb6a4d2cb 100644
--- a/embassy-stm32/src/pac/stm32h735zg.rs
+++ b/embassy-stm32/src/pac/stm32h735zg.rs
@@ -229,12 +229,77 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -252,7 +317,7 @@ peripherals!(
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12,
     PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13,
-    PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK14, PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742ag.rs b/embassy-stm32/src/pac/stm32h742ag.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742ag.rs
+++ b/embassy-stm32/src/pac/stm32h742ag.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742ai.rs b/embassy-stm32/src/pac/stm32h742ai.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742ai.rs
+++ b/embassy-stm32/src/pac/stm32h742ai.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742bg.rs b/embassy-stm32/src/pac/stm32h742bg.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742bg.rs
+++ b/embassy-stm32/src/pac/stm32h742bg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742bi.rs b/embassy-stm32/src/pac/stm32h742bi.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742bi.rs
+++ b/embassy-stm32/src/pac/stm32h742bi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742ig.rs b/embassy-stm32/src/pac/stm32h742ig.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742ig.rs
+++ b/embassy-stm32/src/pac/stm32h742ig.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742ii.rs b/embassy-stm32/src/pac/stm32h742ii.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742ii.rs
+++ b/embassy-stm32/src/pac/stm32h742ii.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742vg.rs b/embassy-stm32/src/pac/stm32h742vg.rs
index 6277a595f..79e11dda0 100644
--- a/embassy-stm32/src/pac/stm32h742vg.rs
+++ b/embassy-stm32/src/pac/stm32h742vg.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742vi.rs b/embassy-stm32/src/pac/stm32h742vi.rs
index 6277a595f..79e11dda0 100644
--- a/embassy-stm32/src/pac/stm32h742vi.rs
+++ b/embassy-stm32/src/pac/stm32h742vi.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742xg.rs b/embassy-stm32/src/pac/stm32h742xg.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742xg.rs
+++ b/embassy-stm32/src/pac/stm32h742xg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742xi.rs b/embassy-stm32/src/pac/stm32h742xi.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742xi.rs
+++ b/embassy-stm32/src/pac/stm32h742xi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742zg.rs b/embassy-stm32/src/pac/stm32h742zg.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742zg.rs
+++ b/embassy-stm32/src/pac/stm32h742zg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h742zi.rs b/embassy-stm32/src/pac/stm32h742zi.rs
index 6277a595f..f676ff8e3 100644
--- a/embassy-stm32/src/pac/stm32h742zi.rs
+++ b/embassy-stm32/src/pac/stm32h742zi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743ag.rs b/embassy-stm32/src/pac/stm32h743ag.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743ag.rs
+++ b/embassy-stm32/src/pac/stm32h743ag.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743ai.rs b/embassy-stm32/src/pac/stm32h743ai.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743ai.rs
+++ b/embassy-stm32/src/pac/stm32h743ai.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743bg.rs b/embassy-stm32/src/pac/stm32h743bg.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743bg.rs
+++ b/embassy-stm32/src/pac/stm32h743bg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743bi.rs b/embassy-stm32/src/pac/stm32h743bi.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743bi.rs
+++ b/embassy-stm32/src/pac/stm32h743bi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743ig.rs b/embassy-stm32/src/pac/stm32h743ig.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743ig.rs
+++ b/embassy-stm32/src/pac/stm32h743ig.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743ii.rs b/embassy-stm32/src/pac/stm32h743ii.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743ii.rs
+++ b/embassy-stm32/src/pac/stm32h743ii.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743vg.rs b/embassy-stm32/src/pac/stm32h743vg.rs
index 47e811b48..b5a5698b0 100644
--- a/embassy-stm32/src/pac/stm32h743vg.rs
+++ b/embassy-stm32/src/pac/stm32h743vg.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743vi.rs b/embassy-stm32/src/pac/stm32h743vi.rs
index 47e811b48..b5a5698b0 100644
--- a/embassy-stm32/src/pac/stm32h743vi.rs
+++ b/embassy-stm32/src/pac/stm32h743vi.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743xg.rs b/embassy-stm32/src/pac/stm32h743xg.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743xg.rs
+++ b/embassy-stm32/src/pac/stm32h743xg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743xi.rs b/embassy-stm32/src/pac/stm32h743xi.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743xi.rs
+++ b/embassy-stm32/src/pac/stm32h743xi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743zg.rs b/embassy-stm32/src/pac/stm32h743zg.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743zg.rs
+++ b/embassy-stm32/src/pac/stm32h743zg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h743zi.rs b/embassy-stm32/src/pac/stm32h743zi.rs
index 47e811b48..38061bdb4 100644
--- a/embassy-stm32/src/pac/stm32h743zi.rs
+++ b/embassy-stm32/src/pac/stm32h743zi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745bg.rs b/embassy-stm32/src/pac/stm32h745bg.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745bg.rs
+++ b/embassy-stm32/src/pac/stm32h745bg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745bi.rs b/embassy-stm32/src/pac/stm32h745bi.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745bi.rs
+++ b/embassy-stm32/src/pac/stm32h745bi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745ig.rs b/embassy-stm32/src/pac/stm32h745ig.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745ig.rs
+++ b/embassy-stm32/src/pac/stm32h745ig.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745ii.rs b/embassy-stm32/src/pac/stm32h745ii.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745ii.rs
+++ b/embassy-stm32/src/pac/stm32h745ii.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745xg.rs b/embassy-stm32/src/pac/stm32h745xg.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745xg.rs
+++ b/embassy-stm32/src/pac/stm32h745xg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745xi.rs b/embassy-stm32/src/pac/stm32h745xi.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745xi.rs
+++ b/embassy-stm32/src/pac/stm32h745xi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745zg.rs b/embassy-stm32/src/pac/stm32h745zg.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745zg.rs
+++ b/embassy-stm32/src/pac/stm32h745zg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h745zi.rs b/embassy-stm32/src/pac/stm32h745zi.rs
index 3a92848f5..e21307b22 100644
--- a/embassy-stm32/src/pac/stm32h745zi.rs
+++ b/embassy-stm32/src/pac/stm32h745zi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747ag.rs b/embassy-stm32/src/pac/stm32h747ag.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747ag.rs
+++ b/embassy-stm32/src/pac/stm32h747ag.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747ai.rs b/embassy-stm32/src/pac/stm32h747ai.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747ai.rs
+++ b/embassy-stm32/src/pac/stm32h747ai.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747bg.rs b/embassy-stm32/src/pac/stm32h747bg.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747bg.rs
+++ b/embassy-stm32/src/pac/stm32h747bg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747bi.rs b/embassy-stm32/src/pac/stm32h747bi.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747bi.rs
+++ b/embassy-stm32/src/pac/stm32h747bi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747ig.rs b/embassy-stm32/src/pac/stm32h747ig.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747ig.rs
+++ b/embassy-stm32/src/pac/stm32h747ig.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747ii.rs b/embassy-stm32/src/pac/stm32h747ii.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747ii.rs
+++ b/embassy-stm32/src/pac/stm32h747ii.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747xg.rs b/embassy-stm32/src/pac/stm32h747xg.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747xg.rs
+++ b/embassy-stm32/src/pac/stm32h747xg.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747xi.rs b/embassy-stm32/src/pac/stm32h747xi.rs
index ade3d41dd..ca37684de 100644
--- a/embassy-stm32/src/pac/stm32h747xi.rs
+++ b/embassy-stm32/src/pac/stm32h747xi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h747zi.rs b/embassy-stm32/src/pac/stm32h747zi.rs
index ade3d41dd..3dbb88f18 100644
--- a/embassy-stm32/src/pac/stm32h747zi.rs
+++ b/embassy-stm32/src/pac/stm32h747zi.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h750ib.rs b/embassy-stm32/src/pac/stm32h750ib.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h750ib.rs
+++ b/embassy-stm32/src/pac/stm32h750ib.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h750vb.rs b/embassy-stm32/src/pac/stm32h750vb.rs
index cfaf3608c..4ed7e06b8 100644
--- a/embassy-stm32/src/pac/stm32h750vb.rs
+++ b/embassy-stm32/src/pac/stm32h750vb.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h750xb.rs b/embassy-stm32/src/pac/stm32h750xb.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h750xb.rs
+++ b/embassy-stm32/src/pac/stm32h750xb.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h750zb.rs b/embassy-stm32/src/pac/stm32h750zb.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h750zb.rs
+++ b/embassy-stm32/src/pac/stm32h750zb.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h753ai.rs b/embassy-stm32/src/pac/stm32h753ai.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h753ai.rs
+++ b/embassy-stm32/src/pac/stm32h753ai.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h753bi.rs b/embassy-stm32/src/pac/stm32h753bi.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h753bi.rs
+++ b/embassy-stm32/src/pac/stm32h753bi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h753ii.rs b/embassy-stm32/src/pac/stm32h753ii.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h753ii.rs
+++ b/embassy-stm32/src/pac/stm32h753ii.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h753vi.rs b/embassy-stm32/src/pac/stm32h753vi.rs
index cfaf3608c..4ed7e06b8 100644
--- a/embassy-stm32/src/pac/stm32h753vi.rs
+++ b/embassy-stm32/src/pac/stm32h753vi.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h753xi.rs b/embassy-stm32/src/pac/stm32h753xi.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h753xi.rs
+++ b/embassy-stm32/src/pac/stm32h753xi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h753zi.rs b/embassy-stm32/src/pac/stm32h753zi.rs
index cfaf3608c..3e60f9bf6 100644
--- a/embassy-stm32/src/pac/stm32h753zi.rs
+++ b/embassy-stm32/src/pac/stm32h753zi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h755bi.rs b/embassy-stm32/src/pac/stm32h755bi.rs
index 673440d22..8141aa290 100644
--- a/embassy-stm32/src/pac/stm32h755bi.rs
+++ b/embassy-stm32/src/pac/stm32h755bi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h755ii.rs b/embassy-stm32/src/pac/stm32h755ii.rs
index 673440d22..8141aa290 100644
--- a/embassy-stm32/src/pac/stm32h755ii.rs
+++ b/embassy-stm32/src/pac/stm32h755ii.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h755xi.rs b/embassy-stm32/src/pac/stm32h755xi.rs
index 673440d22..8141aa290 100644
--- a/embassy-stm32/src/pac/stm32h755xi.rs
+++ b/embassy-stm32/src/pac/stm32h755xi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h755zi.rs b/embassy-stm32/src/pac/stm32h755zi.rs
index 673440d22..8141aa290 100644
--- a/embassy-stm32/src/pac/stm32h755zi.rs
+++ b/embassy-stm32/src/pac/stm32h755zi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h757ai.rs b/embassy-stm32/src/pac/stm32h757ai.rs
index 66057ae06..bc78a72f4 100644
--- a/embassy-stm32/src/pac/stm32h757ai.rs
+++ b/embassy-stm32/src/pac/stm32h757ai.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h757bi.rs b/embassy-stm32/src/pac/stm32h757bi.rs
index 66057ae06..bc78a72f4 100644
--- a/embassy-stm32/src/pac/stm32h757bi.rs
+++ b/embassy-stm32/src/pac/stm32h757bi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h757ii.rs b/embassy-stm32/src/pac/stm32h757ii.rs
index 66057ae06..bc78a72f4 100644
--- a/embassy-stm32/src/pac/stm32h757ii.rs
+++ b/embassy-stm32/src/pac/stm32h757ii.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h757xi.rs b/embassy-stm32/src/pac/stm32h757xi.rs
index 66057ae06..bc78a72f4 100644
--- a/embassy-stm32/src/pac/stm32h757xi.rs
+++ b/embassy-stm32/src/pac/stm32h757xi.rs
@@ -239,12 +239,69 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +320,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h757zi.rs b/embassy-stm32/src/pac/stm32h757zi.rs
index 66057ae06..9eed14029 100644
--- a/embassy-stm32/src/pac/stm32h757zi.rs
+++ b/embassy-stm32/src/pac/stm32h757zi.rs
@@ -239,12 +239,58 @@ impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10);
 impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11);
 impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11);
 impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -263,7 +309,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3ag.rs b/embassy-stm32/src/pac/stm32h7a3ag.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3ag.rs
+++ b/embassy-stm32/src/pac/stm32h7a3ag.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3ai.rs b/embassy-stm32/src/pac/stm32h7a3ai.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3ai.rs
+++ b/embassy-stm32/src/pac/stm32h7a3ai.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3ig.rs b/embassy-stm32/src/pac/stm32h7a3ig.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3ig.rs
+++ b/embassy-stm32/src/pac/stm32h7a3ig.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3ii.rs b/embassy-stm32/src/pac/stm32h7a3ii.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3ii.rs
+++ b/embassy-stm32/src/pac/stm32h7a3ii.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3lg.rs b/embassy-stm32/src/pac/stm32h7a3lg.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3lg.rs
+++ b/embassy-stm32/src/pac/stm32h7a3lg.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3li.rs b/embassy-stm32/src/pac/stm32h7a3li.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3li.rs
+++ b/embassy-stm32/src/pac/stm32h7a3li.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3ng.rs b/embassy-stm32/src/pac/stm32h7a3ng.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3ng.rs
+++ b/embassy-stm32/src/pac/stm32h7a3ng.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3ni.rs b/embassy-stm32/src/pac/stm32h7a3ni.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3ni.rs
+++ b/embassy-stm32/src/pac/stm32h7a3ni.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3qi.rs b/embassy-stm32/src/pac/stm32h7a3qi.rs
index cc3b10a98..42b8a002f 100644
--- a/embassy-stm32/src/pac/stm32h7a3qi.rs
+++ b/embassy-stm32/src/pac/stm32h7a3qi.rs
@@ -246,12 +246,69 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +327,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3rg.rs b/embassy-stm32/src/pac/stm32h7a3rg.rs
index cc3b10a98..625450dbe 100644
--- a/embassy-stm32/src/pac/stm32h7a3rg.rs
+++ b/embassy-stm32/src/pac/stm32h7a3rg.rs
@@ -246,12 +246,61 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +319,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3ri.rs b/embassy-stm32/src/pac/stm32h7a3ri.rs
index cc3b10a98..625450dbe 100644
--- a/embassy-stm32/src/pac/stm32h7a3ri.rs
+++ b/embassy-stm32/src/pac/stm32h7a3ri.rs
@@ -246,12 +246,61 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +319,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3vg.rs b/embassy-stm32/src/pac/stm32h7a3vg.rs
index cc3b10a98..42b8a002f 100644
--- a/embassy-stm32/src/pac/stm32h7a3vg.rs
+++ b/embassy-stm32/src/pac/stm32h7a3vg.rs
@@ -246,12 +246,69 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +327,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3vi.rs b/embassy-stm32/src/pac/stm32h7a3vi.rs
index cc3b10a98..42b8a002f 100644
--- a/embassy-stm32/src/pac/stm32h7a3vi.rs
+++ b/embassy-stm32/src/pac/stm32h7a3vi.rs
@@ -246,12 +246,69 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +327,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3zg.rs b/embassy-stm32/src/pac/stm32h7a3zg.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3zg.rs
+++ b/embassy-stm32/src/pac/stm32h7a3zg.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7a3zi.rs b/embassy-stm32/src/pac/stm32h7a3zi.rs
index cc3b10a98..1f31a5da6 100644
--- a/embassy-stm32/src/pac/stm32h7a3zi.rs
+++ b/embassy-stm32/src/pac/stm32h7a3zi.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b0ab.rs b/embassy-stm32/src/pac/stm32h7b0ab.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b0ab.rs
+++ b/embassy-stm32/src/pac/stm32h7b0ab.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b0ib.rs b/embassy-stm32/src/pac/stm32h7b0ib.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b0ib.rs
+++ b/embassy-stm32/src/pac/stm32h7b0ib.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b0rb.rs b/embassy-stm32/src/pac/stm32h7b0rb.rs
index cba2c71b0..3880f8938 100644
--- a/embassy-stm32/src/pac/stm32h7b0rb.rs
+++ b/embassy-stm32/src/pac/stm32h7b0rb.rs
@@ -246,12 +246,61 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +319,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b0vb.rs b/embassy-stm32/src/pac/stm32h7b0vb.rs
index cba2c71b0..d0f3a0384 100644
--- a/embassy-stm32/src/pac/stm32h7b0vb.rs
+++ b/embassy-stm32/src/pac/stm32h7b0vb.rs
@@ -246,12 +246,69 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +327,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b0zb.rs b/embassy-stm32/src/pac/stm32h7b0zb.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b0zb.rs
+++ b/embassy-stm32/src/pac/stm32h7b0zb.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3ai.rs b/embassy-stm32/src/pac/stm32h7b3ai.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b3ai.rs
+++ b/embassy-stm32/src/pac/stm32h7b3ai.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3ii.rs b/embassy-stm32/src/pac/stm32h7b3ii.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b3ii.rs
+++ b/embassy-stm32/src/pac/stm32h7b3ii.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3li.rs b/embassy-stm32/src/pac/stm32h7b3li.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b3li.rs
+++ b/embassy-stm32/src/pac/stm32h7b3li.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3ni.rs b/embassy-stm32/src/pac/stm32h7b3ni.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b3ni.rs
+++ b/embassy-stm32/src/pac/stm32h7b3ni.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3qi.rs b/embassy-stm32/src/pac/stm32h7b3qi.rs
index cba2c71b0..d0f3a0384 100644
--- a/embassy-stm32/src/pac/stm32h7b3qi.rs
+++ b/embassy-stm32/src/pac/stm32h7b3qi.rs
@@ -246,12 +246,69 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +327,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3ri.rs b/embassy-stm32/src/pac/stm32h7b3ri.rs
index cba2c71b0..3880f8938 100644
--- a/embassy-stm32/src/pac/stm32h7b3ri.rs
+++ b/embassy-stm32/src/pac/stm32h7b3ri.rs
@@ -246,12 +246,61 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +319,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3vi.rs b/embassy-stm32/src/pac/stm32h7b3vi.rs
index cba2c71b0..d0f3a0384 100644
--- a/embassy-stm32/src/pac/stm32h7b3vi.rs
+++ b/embassy-stm32/src/pac/stm32h7b3vi.rs
@@ -246,12 +246,69 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +327,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/pac/stm32h7b3zi.rs b/embassy-stm32/src/pac/stm32h7b3zi.rs
index cba2c71b0..6d01166cc 100644
--- a/embassy-stm32/src/pac/stm32h7b3zi.rs
+++ b/embassy-stm32/src/pac/stm32h7b3zi.rs
@@ -246,12 +246,80 @@ impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10);
 impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10);
 impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10);
 impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+impl_spi_pin!(SPI1, MosiPin, PD7, 5);
+impl_spi_pin!(SPI1, SckPin, PG11, 5);
+impl_spi_pin!(SPI1, MisoPin, PG9, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MosiPin, PC1, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, MosiPin, PB2, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 7);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+impl_spi_pin!(SPI5, MosiPin, PJ10, 5);
+impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
+impl_spi_pin!(SPI5, SckPin, PK0, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
+impl_spi!(SPI6, APB4);
+impl_spi_pin!(SPI6, SckPin, PA5, 8);
+impl_spi_pin!(SPI6, MisoPin, PA6, 8);
+impl_spi_pin!(SPI6, MosiPin, PA7, 8);
+impl_spi_pin!(SPI6, SckPin, PB3, 8);
+impl_spi_pin!(SPI6, MisoPin, PB4, 8);
+impl_spi_pin!(SPI6, MosiPin, PB5, 8);
+impl_spi_pin!(SPI6, SckPin, PC12, 5);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
 pub use regs::dma_v2 as dma;
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
 pub use regs::rng_v1 as rng;
 pub use regs::sdmmc_v2 as sdmmc;
+pub use regs::spi_v3 as spi;
 pub use regs::syscfg_h7 as syscfg;
 mod regs;
 use embassy_extras::peripherals;
@@ -270,7 +338,7 @@ peripherals!(
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
     PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
     PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
-    PK15, RNG, SDMMC1, SDMMC2, SYSCFG
+    PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
 );
 
 pub mod interrupt {
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 9f62a5ec9..09a9d702f 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -2,6 +2,7 @@
 
 #[cfg_attr(feature = "_spi_v1", path = "v1.rs")]
 #[cfg_attr(feature = "_spi_v2", path = "v2.rs")]
+#[cfg_attr(feature = "_spi_v3", path = "v3.rs")]
 mod _version;
 pub use _version::*;
 
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index a464c4275..d1f0473cc 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -5,6 +5,7 @@ use crate::pac::spi;
 use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
 use crate::time::Hertz;
 use core::marker::PhantomData;
+use core::ptr;
 use embassy::util::Unborrow;
 use embassy_extras::unborrow;
 pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
@@ -53,7 +54,7 @@ impl<'d, T: Instance> Spi<'d, T> {
         let miso = miso.degrade();
 
         unsafe {
-            T::regs().cr2().write(|w| {
+            T::regs().cr2().modify(|w| {
                 w.set_ssoe(false);
             });
         }
@@ -61,7 +62,7 @@ impl<'d, T: Instance> Spi<'d, T> {
         let br = Self::compute_baud_rate(pclk, freq.into());
 
         unsafe {
-            T::regs().cr1().write(|w| {
+            T::regs().cr1().modify(|w| {
                 w.set_cpha(
                     match config.mode.phase == Phase::CaptureOnSecondTransition {
                         true => spi::vals::Cpha::SECONDEDGE,
@@ -151,7 +152,8 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u8;
+                ptr::write_volatile(dr, *word);
             }
             loop {
                 let sr = unsafe { regs.sr().read() };
@@ -186,12 +188,19 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u8;
+                ptr::write_volatile(dr, *word);
             }
+
             while unsafe { !regs.sr().read().rxne() } {
                 // spin waiting for inbound to shift in.
             }
-            *word = unsafe { regs.dr().read().0 as u8 };
+
+            unsafe {
+                let dr = regs.dr().ptr() as *const u8;
+                *word = ptr::read_volatile(dr);
+            }
+
             let sr = unsafe { regs.sr().read() };
             if sr.fre() {
                 return Err(Error::Framing);
@@ -220,7 +229,8 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u16;
+                ptr::write_volatile(dr, *word);
             }
             loop {
                 let sr = unsafe { regs.sr().read() };
@@ -255,12 +265,17 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u16;
+                ptr::write_volatile(dr, *word);
             }
             while unsafe { !regs.sr().read().rxne() } {
                 // spin waiting for inbound to shift in.
             }
-            *word = unsafe { regs.dr().read().0 as u16 };
+            unsafe {
+                let dr = regs.dr().ptr() as *const u16;
+                *word = ptr::read_volatile(dr);
+            }
+
             let sr = unsafe { regs.sr().read() };
             if sr.fre() {
                 return Err(Error::Framing);
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index b6ae8b275..393adc4e9 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -4,9 +4,10 @@ use crate::gpio::{AnyPin, Pin};
 use crate::pac::gpio::vals::{Afr, Moder};
 use crate::pac::gpio::Gpio;
 use crate::pac::spi;
-use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize};
+use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
 use crate::time::Hertz;
 use core::marker::PhantomData;
+use core::ptr;
 use embassy::util::Unborrow;
 use embassy_extras::unborrow;
 pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
@@ -52,25 +53,22 @@ impl<'d, T: Instance> Spi<'d, T> {
         unborrow!(sck, mosi, miso);
 
         unsafe {
-            Self::configure_pin(sck.block(), sck.pin() as _, sck.af());
-            Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af());
-            Self::configure_pin(miso.block(), miso.pin() as _, miso.af());
+            Self::configure_pin(sck.block(), sck.pin() as _, sck.af_num());
+            Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af_num());
+            Self::configure_pin(miso.block(), miso.pin() as _, miso.af_num());
         }
 
         let sck = sck.degrade();
         let mosi = mosi.degrade();
         let miso = miso.degrade();
 
-        unsafe {
-            T::regs().cr2().write(|w| {
-                w.set_ssoe(false);
-            });
-        }
-
         let br = Self::compute_baud_rate(pclk, freq.into());
 
         unsafe {
-            T::regs().cr1().write(|w| {
+            T::regs().cr2().modify(|w| {
+                w.set_ssoe(false);
+            });
+            T::regs().cr1().modify(|w| {
                 w.set_cpha(
                     match config.mode.phase == Phase::CaptureOnSecondTransition {
                         true => spi::vals::Cpha::SECONDEDGE,
@@ -84,7 +82,6 @@ impl<'d, T: Instance> Spi<'d, T> {
 
                 w.set_mstr(spi::vals::Mstr::MASTER);
                 w.set_br(spi::vals::Br(br));
-                w.set_spe(true);
                 w.set_lsbfirst(match config.byte_order {
                     ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST,
                     ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST,
@@ -93,6 +90,7 @@ impl<'d, T: Instance> Spi<'d, T> {
                 w.set_ssm(true);
                 w.set_crcen(false);
                 w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL);
+                w.set_spe(true);
             });
         }
 
@@ -131,9 +129,15 @@ impl<'d, T: Instance> Spi<'d, T> {
 
     fn set_word_size(word_size: WordSize) {
         unsafe {
-            T::regs().cr2().write(|w| {
-                w.set_ds(word_size.ds());
+            T::regs().cr1().modify(|w| {
+                w.set_spe(false);
+            });
+            T::regs().cr2().modify(|w| {
                 w.set_frxth(word_size.frxth());
+                w.set_ds(word_size.ds());
+            });
+            T::regs().cr1().modify(|w| {
+                w.set_spe(true);
             });
         }
     }
@@ -149,12 +153,6 @@ impl<'d, T: Instance> Drop for Spi<'d, T> {
     }
 }
 
-pub enum Error {
-    Framing,
-    Crc,
-    Overrun,
-}
-
 impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
     type Error = Error;
 
@@ -162,12 +160,13 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
         Self::set_word_size(WordSize::EightBit);
         let regs = T::regs();
 
-        for word in words.iter() {
+        for (i, word) in words.iter().enumerate() {
             while unsafe { !regs.sr().read().txe() } {
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u8;
+                ptr::write_volatile(dr, *word);
             }
             loop {
                 let sr = unsafe { regs.sr().read() };
@@ -197,17 +196,33 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
         Self::set_word_size(WordSize::EightBit);
         let regs = T::regs();
 
-        for word in words.iter_mut() {
+        for (i, word) in words.iter_mut().enumerate() {
             while unsafe { !regs.sr().read().txe() } {
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u8;
+                ptr::write_volatile(dr, *word);
             }
-            while unsafe { !regs.sr().read().rxne() } {
-                // spin waiting for inbound to shift in.
+            loop {
+                let sr = unsafe { regs.sr().read() };
+                if sr.rxne() {
+                    break;
+                }
+                if sr.fre() {
+                    return Err(Error::Framing);
+                }
+                if sr.ovr() {
+                    return Err(Error::Overrun);
+                }
+                if sr.crcerr() {
+                    return Err(Error::Crc);
+                }
+            }
+            unsafe {
+                let dr = regs.dr().ptr() as *const u8;
+                *word = ptr::read_volatile(dr);
             }
-            *word = unsafe { regs.dr().read().0 as u8 };
             let sr = unsafe { regs.sr().read() };
             if sr.fre() {
                 return Err(Error::Framing);
@@ -236,7 +251,8 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u16;
+                ptr::write_volatile(dr, *word);
             }
             loop {
                 let sr = unsafe { regs.sr().read() };
@@ -271,12 +287,16 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
                 // spin
             }
             unsafe {
-                regs.dr().write(|reg| reg.0 = *word as u32);
+                let dr = regs.dr().ptr() as *mut u16;
+                ptr::write_volatile(dr, *word);
             }
             while unsafe { !regs.sr().read().rxne() } {
                 // spin waiting for inbound to shift in.
             }
-            *word = unsafe { regs.dr().read().0 as u16 };
+            unsafe {
+                let dr = regs.dr().ptr() as *const u16;
+                *word = ptr::read_volatile(dr);
+            }
             let sr = unsafe { regs.sr().read() };
             if sr.fre() {
                 return Err(Error::Framing);
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
new file mode 100644
index 000000000..c3f66430c
--- /dev/null
+++ b/embassy-stm32/src/spi/v3.rs
@@ -0,0 +1,360 @@
+#![macro_use]
+
+use crate::gpio::{AnyPin, Pin};
+use crate::pac::gpio::vals::{Afr, Moder};
+use crate::pac::gpio::Gpio;
+use crate::pac::spi;
+use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
+use crate::time::Hertz;
+use core::marker::PhantomData;
+use core::ptr;
+use embassy::util::Unborrow;
+use embassy_extras::unborrow;
+pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+
+impl WordSize {
+    fn dsize(&self) -> u8 {
+        match self {
+            WordSize::EightBit => 0b0111,
+            WordSize::SixteenBit => 0b1111,
+        }
+    }
+
+    fn frxth(&self) -> spi::vals::Fthlv {
+        match self {
+            WordSize::EightBit => spi::vals::Fthlv::ONEFRAME,
+            WordSize::SixteenBit => spi::vals::Fthlv::ONEFRAME,
+        }
+    }
+}
+
+pub struct Spi<'d, T: Instance> {
+    //peri: T,
+    sck: AnyPin,
+    mosi: AnyPin,
+    miso: AnyPin,
+    phantom: PhantomData<&'d mut T>,
+}
+
+impl<'d, T: Instance> Spi<'d, T> {
+    pub fn new<F>(
+        pclk: Hertz,
+        peri: impl Unborrow<Target = T> + 'd,
+        sck: impl Unborrow<Target = impl SckPin<T>>,
+        mosi: impl Unborrow<Target = impl MosiPin<T>>,
+        miso: impl Unborrow<Target = impl MisoPin<T>>,
+        freq: F,
+        config: Config,
+    ) -> Self
+    where
+        F: Into<Hertz>,
+    {
+        unborrow!(peri);
+        unborrow!(sck, mosi, miso);
+
+        unsafe {
+            Self::configure_pin(sck.block(), sck.pin() as _, sck.af_num());
+            //sck.block().otyper().modify(|w| w.set_ot(sck.pin() as _, crate::pac::gpio::vals::Ot::PUSHPULL));
+            Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af_num());
+            //mosi.block().otyper().modify(|w| w.set_ot(mosi.pin() as _, crate::pac::gpio::vals::Ot::PUSHPULL));
+            Self::configure_pin(miso.block(), miso.pin() as _, miso.af_num());
+        }
+
+        let sck = sck.degrade();
+        let mosi = mosi.degrade();
+        let miso = miso.degrade();
+
+        let br = Self::compute_baud_rate(pclk, freq.into());
+        unsafe {
+            T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
+            T::regs().cfg2().modify(|w| {
+                //w.set_ssoe(true);
+                w.set_ssoe(false);
+                w.set_cpha(
+                    match config.mode.phase == Phase::CaptureOnSecondTransition {
+                        true => spi::vals::Cpha::SECONDEDGE,
+                        false => spi::vals::Cpha::FIRSTEDGE,
+                    },
+                );
+                w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
+                    true => spi::vals::Cpol::IDLEHIGH,
+                    false => spi::vals::Cpol::IDLELOW,
+                });
+                w.set_lsbfrst(match config.byte_order {
+                    ByteOrder::LsbFirst => spi::vals::Lsbfrst::LSBFIRST,
+                    ByteOrder::MsbFirst => spi::vals::Lsbfrst::MSBFIRST,
+                });
+                w.set_ssm(true);
+                w.set_master(spi::vals::Master::MASTER);
+                w.set_comm(spi::vals::Comm::FULLDUPLEX);
+                w.set_ssom(spi::vals::Ssom::ASSERTED);
+                w.set_midi(0);
+                w.set_mssi(0);
+                w.set_afcntr(spi::vals::Afcntr::CONTROLLED);
+                w.set_ssiop(spi::vals::Ssiop::ACTIVEHIGH);
+            });
+            T::regs().cfg1().modify(|w| {
+                w.set_crcen(false);
+                w.set_mbr(spi::vals::Mbr(br));
+                w.set_dsize(WordSize::EightBit.dsize());
+                //w.set_fthlv(WordSize::EightBit.frxth());
+            });
+            T::regs().cr2().modify(|w| {
+                w.set_tsize(0);
+                w.set_tser(0);
+            });
+            T::regs().cr1().modify(|w| {
+                w.set_ssi(false);
+                w.set_spe(true);
+            });
+        }
+
+        Self {
+            //peri,
+            sck,
+            mosi,
+            miso,
+            phantom: PhantomData,
+        }
+    }
+
+    unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
+        let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
+        block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
+        block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
+        block
+            .ospeedr()
+            .modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED));
+    }
+
+    unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
+        block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG));
+    }
+
+    fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
+        match clocks.0 / freq.0 {
+            0 => unreachable!(),
+            1..=2 => 0b000,
+            3..=5 => 0b001,
+            6..=11 => 0b010,
+            12..=23 => 0b011,
+            24..=39 => 0b100,
+            40..=95 => 0b101,
+            96..=191 => 0b110,
+            _ => 0b111,
+        }
+    }
+
+    fn set_word_size(word_size: WordSize) {
+        unsafe {
+            T::regs().cr1().modify(|w| {
+                w.set_csusp(true);
+            });
+            while T::regs().sr().read().eot() {}
+            T::regs().cr1().modify(|w| {
+                w.set_spe(false);
+            });
+            T::regs().cfg1().modify(|w| {
+                w.set_dsize(word_size.dsize());
+            });
+            T::regs().cr1().modify(|w| {
+                w.set_spe(true);
+            });
+        }
+    }
+}
+
+impl<'d, T: Instance> Drop for Spi<'d, T> {
+    fn drop(&mut self) {
+        unsafe {
+            Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _);
+            Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _);
+            Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _);
+        }
+    }
+}
+
+impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
+    type Error = Error;
+
+    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        Self::set_word_size(WordSize::EightBit);
+        let regs = T::regs();
+
+        for word in words.iter() {
+            while unsafe { !regs.sr().read().txp() } {
+                // spin
+            }
+            unsafe {
+                let txdr = regs.txdr().ptr() as *mut u8;
+                ptr::write_volatile(txdr, *word);
+                regs.cr1().modify(|reg| reg.set_cstart(true));
+            }
+            loop {
+                let sr = unsafe { regs.sr().read() };
+                if sr.tifre() {
+                    return Err(Error::Framing);
+                }
+                if sr.ovr() {
+                    return Err(Error::Overrun);
+                }
+                if sr.crce() {
+                    return Err(Error::Crc);
+                }
+                if !sr.txp() {
+                    // loop waiting for TXE
+                }
+            }
+        }
+
+        Ok(())
+    }
+}
+
+impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
+    type Error = Error;
+
+    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
+        Self::set_word_size(WordSize::EightBit);
+        let regs = T::regs();
+
+        for (i, word) in words.iter_mut().enumerate() {
+            unsafe {
+                regs.cr1().modify(|reg| {
+                    reg.set_ssi(false);
+                });
+            }
+            while unsafe { !regs.sr().read().txp() } {
+                // spin
+            }
+            unsafe {
+                let txdr = regs.txdr().ptr() as *mut u8;
+                ptr::write_volatile(txdr, *word);
+                regs.cr1().modify(|reg| reg.set_cstart(true));
+            }
+            loop {
+                let sr = unsafe { regs.sr().read() };
+
+                if sr.rxp() {
+                    break;
+                }
+                if sr.tifre() {
+                    return Err(Error::Framing);
+                }
+                if sr.ovr() {
+                    return Err(Error::Overrun);
+                }
+                if sr.crce() {
+                    return Err(Error::Crc);
+                }
+            }
+            unsafe {
+                let rxdr = regs.rxdr().ptr() as *const u8;
+                *word = ptr::read_volatile(rxdr);
+            }
+            let sr = unsafe { regs.sr().read() };
+            if sr.tifre() {
+                return Err(Error::Framing);
+            }
+            if sr.ovr() {
+                return Err(Error::Overrun);
+            }
+            if sr.crce() {
+                return Err(Error::Crc);
+            }
+        }
+
+        Ok(words)
+    }
+}
+
+impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
+    type Error = Error;
+
+    fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
+        Self::set_word_size(WordSize::SixteenBit);
+        let regs = T::regs();
+
+        for word in words.iter() {
+            while unsafe { !regs.sr().read().txp() } {
+                // spin
+            }
+            unsafe {
+                let txdr = regs.txdr().ptr() as *mut u16;
+                ptr::write_volatile(txdr, *word);
+                regs.cr1().modify(|reg| reg.set_cstart(true));
+            }
+            loop {
+                let sr = unsafe { regs.sr().read() };
+                if sr.tifre() {
+                    return Err(Error::Framing);
+                }
+                if sr.ovr() {
+                    return Err(Error::Overrun);
+                }
+                if sr.crce() {
+                    return Err(Error::Crc);
+                }
+                if !sr.txp() {
+                    // loop waiting for TXE
+                }
+            }
+        }
+
+        Ok(())
+    }
+}
+
+impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> {
+    type Error = Error;
+
+    fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
+        Self::set_word_size(WordSize::SixteenBit);
+        let regs = T::regs();
+
+        for word in words.iter_mut() {
+            while unsafe { !regs.sr().read().txp() } {
+                // spin
+            }
+            unsafe {
+                let txdr = regs.txdr().ptr() as *mut u16;
+                ptr::write_volatile(txdr, *word);
+                regs.cr1().modify(|reg| reg.set_cstart(true));
+            }
+
+            loop {
+                let sr = unsafe { regs.sr().read() };
+
+                if sr.rxp() {
+                    break;
+                }
+                if sr.tifre() {
+                    return Err(Error::Framing);
+                }
+                if sr.ovr() {
+                    return Err(Error::Overrun);
+                }
+                if sr.crce() {
+                    return Err(Error::Crc);
+                }
+            }
+
+            unsafe {
+                let rxdr = regs.rxdr().ptr() as *const u16;
+                *word = ptr::read_volatile(rxdr);
+            }
+            let sr = unsafe { regs.sr().read() };
+            if sr.tifre() {
+                return Err(Error::Framing);
+            }
+            if sr.ovr() {
+                return Err(Error::Overrun);
+            }
+            if sr.crce() {
+                return Err(Error::Crc);
+            }
+        }
+
+        Ok(words)
+    }
+}
diff --git a/embassy-stm32/stm32-data b/embassy-stm32/stm32-data
-Subproject 67db3905b34f062c55ceff09b1beac8444b78ca
+Subproject 982713663b9e7359ca0acd55231bb90dfc25e68